# # Interposer Connectors J4 & J5 Most Nets # -------------------------------------------- # # # Disco-Kraken Key In Net List # ------------------------------- # # # Initial Rev. 30-Nov-2023 # Current Rev. 2-July-2024 # # # # This net list holds the Interposer Connectors J4 & J5 # --------------------------------- # # # J4 connects to Interposer "A" i.e. This Hemisphere # J5 connects to Interposer "B" i.e. the Other Hemisphere # # # NOTE: In this file net-names are assigned to only # the following 34 Interposer Connector pins: # # 18, 20, 22, 24 SPI Bus # # 23, 27, 28 Address Lines # # 19 CTRL_Reset_B # # 11, 12 Piezo Signals # # 7 FLASH_Pulse_p single ended 3V3 CMOS to Interposer # 8 FLASH_Pulse_n this pin is Grounded # # 15 FLASH_TDC 3V3 CMOS from Interposer # # 31 uBase_UART_Tx # 32 uBase_UART-Rx # # 33 Muon_S1 \ # 35 Muon_S2 | Muon Scintillator Signals # 36 Muon_S3 | 3V3 CMOS from Interposer "B" only # 37 Muon_S4 / # # 5, 6, 9, 10 Grounds # 13, 14, 16, 17 Grounds # 21, 25, 26, 29 Grounds # 30, 34, 38 Grounds # # # # # From Adam's drawing from 20-Oct-2023: 87833-4020 # # # 1 1V8 2 1V8 # 3 3V3 4 3V3 # 5 Gnd 6 Gnd # 7 FLASH_Pulse_p 8 FLASH_Pulse_n # 9 Gnd 10 Gnd # # 11 PIEZO_p 12 PIEZO_n # 13 Gnd 14 Gnd # 15 FLASH_TDC 16 Gnd # 17 Gnd 18 SPI_CLK # 19 CTRL_RST 20 SPI_MISO # # 21 Gnd 22 SPI_MOSI # 23 A0 24 SPI_CS # 25 Gnd 26 Gnd # 27 A2 28 A1 # 29 Gnd 30 Gnd # # 31 uBase_UART_Tx 32 uBase_UART-Rx # 33 SMUT_S1 34 Gnd # 35 SMUT_S2 36 SMUT_S3 # 37 SMUT_S4 38 Gnd # 39 5V0 40 5V0 # # # SPI Signals to Interposer "A" J4 THIS Hemisphere: # ---------------------------------------------------------------- # NET 'INTERP_1_Conn_SCLK' J4-18 # SPI CLK to Interposer #1 Pin 18 NET 'INTERP_1_Conn_MOSI' J4-22 # SPI MOSI to Interposer #1 Pin 22 NET 'INTERP_1_Conn_MISO' J4-20 # SPI MISO from Interposer #1 Pin 20 NET 'INTERP_1_Conn_CS_B' J4-24 # SPI CS_B to Interposer #1 Pin 24 # # Address Signals to Interposer "A" J4 THIS Hemisphere: # ------------------------------------------------------------ # NET 'INTERP_1_Conn_CS_A0' J4-23 # CS_A0 to Interposer #1 Pin 23 NET 'INTERP_1_Conn_CS_A1' J4-28 # CS_A1 to Interposer #1 Pin 28 NET 'INTERP_1_Conn_CS_A2' J4-27 # CS_A2 to Interposer #1 Pin 27 NET 'INTERP_1_Conn_CTRL_Reset_B' J4-19 # CTRL_Reset_B to Interposer #1 Pin 19 # # SPI Signals to Interposer "B" J5 OTHER Hemisphere: # ----------------------------------------------------------------- # NET 'INTERP_2_Conn_SCLK' J5-18 # SPI CLK to Interposer #2 Pin 18 NET 'INTERP_2_Conn_MOSI' J5-22 # SPI MOSI to Interposer #2 Pin 22 NET 'INTERP_2_Conn_MISO' J5-20 # SPI MISO from Interposer #2 Pin 20 NET 'INTERP_2_Conn_CS_B' J5-24 # SPI CS_B to Interposer #2 Pin 24 # # Address Signals to Interposer "B" J5 OTHER Hemisphere: # ------------------------------------------------------------- # NET 'INTERP_2_Conn_CS_A0' J5-23 # CS_A0 to Interposer #2 Pin 23 NET 'INTERP_2_Conn_CS_A1' J5-28 # CS_A1 to Interposer #2 Pin 28 NET 'INTERP_2_Conn_CS_A2' J5-27 # CS_A2 to Interposer #2 Pin 27 NET 'INTERP_2_Conn_CTRL_Reset_B' J5-19 # CTRL_Reset_B to Interposer #2 Pin 19 # # Piezo Input Signals to BB Audio ADC for Interposer #1 & #2: # ----------------------------------------------------------------- # NET 'Interposer_1_Audio_DIR' J4-11 # Interposer "A" Audio Signal DIR aka PIEZO_p NET 'Interposer_1_Audio_CMP' J4-12 # Interposer "A" Audio Signal CMP aka PIEZO_n NET 'Interposer_2_Audio_DIR' J5-11 # Interposer "B" Audio Signal DIR aka PIEZO_p NET 'Interposer_2_Audio_CMP' J5-12 # Interposer "B" Audio Signal CMP aka PIEZO_n # # PMT uBase UART Tx and Rx Connections for Interposer #1 & #2: # --------------------------------------------------------------------- # NET 'Interposer_1_UART_Tx' J4-31 # uBase_UART Tx Data from Interposer "A" NET 'Interposer_1_UART_Rx' J4-32 # uBase_UART Rx Data to Interposer "A" NET 'Interposer_2_UART_Tx' J5-31 # uBase_UART Tx Data from Interposer "B" NET 'Interposer_2_UART_Rx' J5-32 # uBase_UART Rx Data to Interposer "B" # # FLASH_PULSE 3V3 CMOS signal to Interposer #1 & #2: # --------------------------------------------------------- # NET 'Interposer_1_Flash_Pulse' J4-7 # Flash_Pulse 3V3 aka FLASH_Pulse_p NET 'GROUND' J4-8 # Grounded pin called FLASH_Pulse_n NET 'Interposer_2_Flash_Pulse' J5-7 # Flash_Pulse 3V3 aka FLASH_Pulse_p NET 'GROUND' J5-8 # Grounded pin called FLASH_Pulse_n # # FLASH_TDC 3V3 CMOS signals from Interposer #1 & #2: # ---------------------------------------------------------- # NET 'Interposer_1_Flash_TDC' J4-15 # Flash_TDC 3V3 signal from the Interposer #1 NET 'Interposer_2_Flash_TDC' J5-15 # Flash_TDC 3V3 signal from the Interposer #2 # # Muon Scintillator S1...S4 3V3 CMOS signals from Interposer #2 only: # ----------------------------------------------------------------------------- # NET 'NO_CONN_Interposer_1_Muon_S1' J4-33 # Muon Scintillator S1 Interposer #1 3V3 CMOS NET 'NO_CONN_Interposer_1_Muon_S2' J4-35 # Muon Scintillator S2 Interposer #1 from Interposer NET 'NO_CONN_Interposer_1_Muon_S3' J4-36 # Muon Scintillator S3 Interposer #1 NO CONNECTION NET 'NO_CONN_Interposer_1_Muon_S4' J4-37 # Muon Scintillator S4 Interposer #1 on the DK Board NET 'Interposer_2_Muon_S1' J5-33 # Muon Scintillator S1 Interposer #2 3V3 CMOS NET 'Interposer_2_Muon_S2' J5-35 # Muon Scintillator S1 Interposer #2 from the NET 'Interposer_2_Muon_S3' J5-36 # Muon Scintillator S1 Interposer #2 Interposer NET 'Interposer_2_Muon_S4' J5-37 # Muon Scintillator S1 Interposer #2 from "B" only # # GROUND Pins on the Interposer Connectors: # ------------------------------------------- # NET 'GROUND' J4-5 J4-6 J4-9 J4-10 # Grounds on J4 NET 'GROUND' J4-13 J4-14 J4-16 J4-17 # Grounds on J4 NET 'GROUND' J4-21 J4-25 J4-26 J4-29 # Grounds on J4 NET 'GROUND' J4-30 J4-34 J4-38 # Grounds on J4 NET 'GROUND' J5-5 J5-6 J5-9 J5-10 # Grounds on J5 NET 'GROUND' J5-13 J5-14 J5-16 J5-17 # Grounds on J5 NET 'GROUND' J5-21 J5-25 J5-26 J5-29 # Grounds on J5 NET 'GROUND' J5-30 J5-34 J5-38 # Grounds on J5