# # JTAG for the DK's FPGA/CPU Nets # -------------------------------------- # # # Disco-Kraken Key In Net List # ------------------------------- # # # Initial Rev. 30-Nov-2023 # Current Rev. 20-Dec-2023 # # # # This net list holds the JTAG for the DK's FPGA/CPU # ------------------------------ # # The components for the # JTAG for the DK's FPGA/CPU # are in the range 1401 to 1449. # # # NOTE: the hex inverter U1402 officially belongs to # this net list file that covers the DK FPGA/CPU # JTAG circuits but that one section in the U1402 # hex inverter is used to handle inverting the # DK_CPU_Is_Awake_B signal in the Startup and Resets # net list file. # # # The JTAG connection to the FPGA/CPU on the DK board is made # via the first 10 pin on the DK J12 Access Connector. # # Access Connector J12 Pinout (first 10 pins) # ------------------------------------------------- # # 1. JTAG_TCLK 2. GROUND # 3. JTAG_TDO 4. NO_CONN # 5. JTAG_TMS 6. JTAG_3V3 # 7. NO_CONN 8. JTAG_TRSTB # 9. JTAG_TDI 10. GROUND # # # This JTAG pinout matches the MicroChip "standard" for their # PolarFire SoC parts as shown on page 15 of their, "Board # Design Guidelines" document. # # NOTE - This document is NOT consistent: # # For the TRSTB signal this document shows a 1k Ohm pull-down # resistor and the text says, "Must be connected to VDDI3 through # a 1k Ohm resistor" and it also says "TRSTB must be held Low # during device operation". What operation - normal operation # or JTAG operation ??? # # For the TCLK signal this document shows a 1k Ohm pull-down # resistor and the text says, "Must be connected to VSS through # a 10k Ohm resistor". # # See also sheets 12 and 24 of the schematics for the # PolarFire SoC SEV Kit demo board. # # From reading various other JTAG documents and checking their # demo-board schematics I will do the following on the DK board: # # TCLK Pull-Down # TMS Pull-Up # TDI Pull-Up # TDO Series Terminator # TRSTB Pull-Down # # # TCLK Input Signal to the DK Board: # --------------------------------------- # NET 'JTAG_TCLK_INPUT' J12-1 R1401-1 U1401-1 # TCLK Input to Pull-Down and 1st Buffer NET 'JTAG_TCLK_1st_2nd' U1401-2 U1401-3 # TCLK 1st Buf Output to 2nd Buf Input NET 'JTAG_TCLK_2nd_TERM' U1401-4 R1405-2 # TCLK 2nd Buf Output to Series Term NET 'JTAG_TCLK_TERM_FPGA' R1405-1 U1-H12 # TCLK Series Term to FPGA Input NET 'GROUND' R1401-2 # Pull-Down Anchor # # TMS Input Signal to the DK Board: # -------------------------------------- # NET 'JTAG_TMS_INPUT' J12-5 R1402-1 U1401-13 # TMS Input to Pull-Up and 1st Buffer NET 'JTAG_TMS_1st_2nd' U1401-12 U1401-11 # TMS 1st Buf Output to 2nd Buf Input NET 'JTAG_TMS_2nd_TERM' U1401-10 R1406-2 # TMS 2nd Buf Output to Series Term NET 'JTAG_TMS_TERM_FPGA' R1406-1 U1-J12 # TMS Series Term to FPGA Input NET 'BULK_3V3' R1402-2 # Pull-Up 3V3 Source # # TDI Input Signal to the DK Board: # -------------------------------------- # NET 'JTAG_TDI_INPUT' J12-9 R1403-1 U1401-9 # TDI Input to Pull-Up and 1st Buffer NET 'JTAG_TDI_1st_2nd' U1401-8 U1401-5 # TDI 1st Buf Output to 2nd Buf Input NET 'JTAG_TDI_2nd_TERM' U1401-6 R1407-2 # TDI 2nd Buf Output to Series Term NET 'JTAG_TDI_TERM_FPGA' R1407-1 U1-H11 # TDI Series Term to FPGA Input NET 'BULK_3V3' R1403-2 # Pull-Up 3V3 Source # # TDO Output Signal from the DK Board: # ----------------------------------------- # NET 'JTAG_TDO_FPGA_1st_TERM' U1-J11 R1409-1 # TDO FPGA Output to 1st Series Term NET 'JTAG_TDO_1st_TERM_1st_Buf' R1409-2 U1402-3 # TDO 1st Term to 1st Buf Input NET 'JTAG_TDO_1st_2nd' U1402-4 U1402-5 # TDO 1st Buf Output to 2nd Buf Input NET 'JTAG_TDO_2nd_Buf_2nd_TERM' U1402-6 R1408-2 # TDO 2nd Buf Output to 2nd Term NET 'JTAG_TDO_OUTPUT' R1408-1 J12-3 # 2nd Series Term to TDO Output Pin # # TRST_B Input Signal to the DK Board: # -------------------------------------- # NET 'JTAG_TRST_B_INPUT' J12-8 R1404-1 U1402-11 # TRST_B Input to Pull-Down and 1st Buffer NET 'JTAG_TRST_B_1st_2nd' U1402-10 U1402-9 # TRST_B 1st Buf Output to 2nd Buf Input NET 'JTAG_TRST_B_2nd_FPGA' U1402-8 U1-J10 # TRST_B 2nd Buf Output to FPGA Input NET 'GROUND' R1404-2 # Pull-Down Anchor # # 3.3 Volt Power and Grounds to the JTAG part of the J12 Access Connector: # ----------------------------------------------------------------------------- # NET 'BULK_3V3' F1401-2 # Bulk_3V3 power to the JTAG Fuse NET 'JTAG_3V3' F1401-1 J12-6 # 3V3 Power to the JTAG Connector NET 'GROUND' J12-2 J12-10 # Ground pins in the JTAG part of J12 NET 'NO_CONN_J12_Pin_4' J12-4 # No Connect Pin #4 in J12 NET 'NO_CONN_J12_Pin_7' J12-7 # No Connect Pin #7 in J12 # # 3.3 Volt Power and Grounds to the JTAG Buffer Chips: # -------------------------------------------------------- # NET 'BULK_3V3' C1401-1 C1402-1 C1403-1 # 3V3 Bypass Caps NET 'GROUND' C1401-2 C1402-2 C1403-2 # Ground Side of Bypass Caps NET 'BULK_3V3' U1401-14 U1402-14 # 3V3 Power to the Buffer Chips NET 'GROUND' U1401-7 U1402-7 # Ground pins on the Buffer Chips NET 'GROUND' U1402-13 # Ground unused input to Buffer U1402