#
#         PMT ADC  High Speed Serial Links  to
#        the FPGA High Speed Serial Transceivers
#       -----------------------------------------
#
#
#                                       Original Rev.  29-Dec-2022
#                                        Current Rev.  22-Feb-2022
#
#
#   This Net List file gives the four JESD204B links from
#   the PMT ADC to four High-Speed Transceivers on the FPGA.
#
#
#    ADC High-Speed Serial Data Input to the FPGA:
#    ---------------------------------------------
#
#     The high-speed serial data from the PMT ADC is carried
#     on four JESD204B links.  These links are received by
#     four high-speed serial receivers in the FPGA-CPU.
#     For pcb routing it looks best to use the receivers in
#     high-speed transceiver number 1.
#
#       ADC  SEROUT0_DIR  D2    to    FPGA  XCVR_1_RX0_DIR  F26
#       ADC  SEROUT0_CMP  D1    to    FPGA  XCVR_1_RX0_CMP  F25
#
#       ADC  SEROUT1_DIR  E2    to    FPGA  XCVR_1_RX1_DIR  H26
#       ADC  SEROUT1_CMP  E1    to    FPGA  XCVR_1_RX1_CMP  H25
#
#       ADC  SEROUT2_DIR  F2    to    FPGA  XCVR_1_RX2_DIR  K26
#       ADC  SEROUT2_CMP  F1    to    FPGA  XCVR_1_RX2_CMP  K25
#
#       ADC  SEROUT3_DIR  G2    to    FPGA  XCVR_1_RX3_DIR  N28
#       ADC  SEROUT3_CMP  G1    to    FPGA  XCVR_1_RX3_CMP  N27
#
#     This routing does not have any lane cross-overs
#     and  the pins of XCVR_1 look more isolated than
#     the pins of XCVR_0.
#


NET  'ADC_SEROUT0_DIR'       C671-2             #  ADC   Lane 0 Out Dir
NET  'FPGA_XCVR_1_RX0_DIR'   C671-1   U1-F26    #  FPGA  XCVR_1_RX0_DIR

NET  'ADC_SEROUT0_CMP'       C672-2             #  ADC   Lane 0 Out CMP
NET  'FPGA_XCVR_1_RX0_CMP'   C672-1   U1-F25    #  FPGA  XCVR_1_RX0_CMP



NET  'ADC_SEROUT1_DIR'       C673-2             #  ADC   Lane 1 Out Dir
NET  'FPGA_XCVR_1_RX1_DIR'   C673-1   U1-H26    #  FPGA  XCVR_1_RX1_DIR

NET  'ADC_SEROUT1_CMP'       C674-2             #  ADC   Lane 1 Out CMP
NET  'FPGA_XCVR_1_RX1_CMP'   C674-1   U1-H25    #  FPGA  XCVR_1_RX1_CMP



NET  'ADC_SEROUT2_DIR'       C675-2             #  ADC   Lane 2 Out Dir
NET  'FPGA_XCVR_1_RX2_DIR'   C675-1   U1-K26    #  FPGA  XCVR_1_RX2_DIR

NET  'ADC_SEROUT2_CMP'       C676-2             #  ADC   Lane 2 Out CMP
NET  'FPGA_XCVR_1_RX2_CMP'   C676-1   U1-K25    #  FPGA  XCVR_1_RX2_CMP



NET  'ADC_SEROUT3_DIR'       C677-2             #  ADC   Lane 3 Out Dir
NET  'FPGA_XCVR_1_RX3_DIR'   C677-1   U1-N28    #  FPGA  XCVR_1_RX3_DIR

NET  'ADC_SEROUT3_CMP'       C678-2             #  ADC   Lane 3 Out CMP
NET  'FPGA_XCVR_1_RX3_CMP'   C678-1   U1-N27    #  FPGA  XCVR_1_RX3_CMP