# # PMT ADC Sundry Net List # --------------------------- # # # Original Rev. 23-Feb-2023 # Current Rev. 6-Dec-2023 # # PMT ADC Sundry Nets # # # PMT ADC Temperature Diode and Power Down / Standby # --------------------------------------------------------- # NET 'PMT_ADC_Temp_Diode' TP601-1 # Temp Diode Signal to Single SMD Pad # The HI Active PMT ADC Power_Down/Standby pin # is Grounded in the Net List file for the ADC itself. # # SPI Bus Connection between FPGA/CPU and PMT ADC 3-Wire SPI # ----------------------------------------------------------------- # # List the NetNames of the Signals that must be # connected to FPGA Floating Pins. Here just list # the NetNames - the actual connections to these # FPGA Floating pins are made in the Nets File: # fpga_cpu_floating_connection_nets.txt # ---------------------------------------------------- # # # All of these are 1V8 signals: PMT ADC SPI Bus # -------------------------------------------------- # # NET 'PMT_ADC_CHIP_SELECT_B' # ADC SPI Chip Select Active LOW # NET 'PMT_ADC_SPI_CLOCK' # ADC SPI Clock # NET 'PMT_ADC_SPI_DATA_IO' # ADC SPI Data I/O # # # CLOCK Type Signals that are sent to the PMT ADC from Timing Generator & FPGA # ----------------------------------------------------------------------------------- # # # Review of the Clock type signals that are inputs to the AD9083 # # See pages: 10, 15, 25, 26 of the AD9083 Datasheet # # Clock is 100 Ohm internally terminated, Clamp is 1 diode above AVDD, # ------- the input has a weak self DC Biased of 0.5 Volts, # the input should be AC coupled, # the Input Amplitude should be 800 to 1800 mV pk-pk # # System_Reference is 100 Ohm internally terminated, Clamp is 1 diode above AVDD, # ---------------- the input has a weak self DC Biased of 0.5 Volts, # the Input Common Mode should be 0.5 V # the Input Amplitude should be 700 to 1100 mV pk-pk # AD says this input is LVDS compatable # # Trigger is 100 Ohm internally terminated, Clamp is 1 diode above AVDD, # ------- the input has a weak self DC Biased of 0.5 Volts, # the Input Common Mode should be 0.5 V # the Input Amplitude should be 700 to 1100 mV pk-pk # AD says this input is LVDS compatable # # Sync_Enb_B is 100K Ohm internally terminated, Clamp is 2 diodes above DVDD1P8, # ---------- the Input Common Mode should be 0.45 V # in its the Input Amplitude should be 700 to 1900 mV pk-pk # Diff Mode AD says this input is LVDS compatable # # # Concerns: AD calls the System_Reference and Trigger inputs "LVDS" # but they are not normal LVDS because their Common Mode is # too Low. Concern - are the 3V3 LVDS outputs from the FPGA/CPU # really true 3 mA Current Mode outputs or are they some # LVDS Like volltage mode thing that will over drive these # AD9083 inputs ? E.G. should I use series resistors ? # # Sync_Enb_B needs an external 100 Ohm terminator - R602. # # The PMT ADC CLOCK signal is AC coupled and # comes from the Timing Generator Output 0-A NET 'PMT_ADC_CLOCK_DIR' C941-2 # ADC Converter Clock DIR Timing Generator Output NET 'PMT_ADC_CLOCK_CMP' C942-2 # ADC Converter Clock CMP 0-A AC Cooupling Caps # The PMT ADC SYSTEM REFERENCE signal is DC coupled # and comes from the Timing Generator Output 0-B # # This connection is made in the Net List file for the ADC itself. # # 'ADC System Reference DIR' U601-K2 # DC Coupled signal from the # 'ADC System Reference CMP' U601-J2 # Timing Generator Output 0-B # The PMT ADC SYNC_Enb_B signal is DC coupled # and comes from a LVDS output on the FPGA/CPU. # # Note that SYNC_Enb_B needs an external 100 Ohm Terminator # when this input is used in its LVDS mode. This 100 Ohm # terminator, R602, is connected here. # # 'PMT_ADC_SYNC_ENB_B_DIR' U601-A2 # ADC JESD204B Sync Enb B DIR # 'PMT_ADC_SYNC_ENB_B_CMP' U601-A3 # ADC JESD204B Sync Enb B CMP # NET 'PMT_ADC_SYNC_ENB_B_DIR' R602-1 # Terminator on Sync_Enb_B NET 'PMT_ADC_SYNC_ENB_B_CMP' R602-2 # Terminator on Sync_Enb_B # The PMT ADC TRIGGER signal is DC coupled and # comes from a LVDS output on the FPGA/CPU. # # 'PMT_ADC_Trigger_DIR' U601-H1 # ADC Trigger Dir Input # 'PMT_ADC_Trigger_CMP' U601-J1 # ADC Trigger Cmp Input # # Clock type Signals from the FPGA/CPU to the PMT ADC # ----------------------------------------------------------- # # List the NetNames of the Signals that must be # connected to FPGA Floating Pins. Here just list # the NetNames - the actual connections to these # FPGA Floating pins are made in the Nets File: # fpga_cpu_floating_connection_nets.txt # ---------------------------------------------------- # # # All of these are LVDS signals: PMT ADC Clock Type Signals # -------------------------------------------------------------- # # NET 'PMT_ADC_SYNC_ENB_B_DIR' # ADC JESD204B Sync Enb B DIR # NET 'PMT_ADC_SYNC_ENB_B_CMP' # ADC JESD204B Sync Enb B CMP # # NET 'PMT_ADC_Trigger_DIR' # ADC Trigger Dir Input # NET 'PMT_ADC_Trigger_CMP' # ADC Trigger Cmp Input # # # End of this big section about CLOCK Type Signals # ----------------------------------------------------- # # # Clock Multiplier PLL Voltage Regulator Bypass Capacitors # NET 'ADC_PLL_REG_BYPASS' C689-1 C699-1 # Clock Multiplier PLL NET 'GROUND' C689-2 C699-2 # Voltage Regulator # Bypass Capacitors # # Clock Multiplier PLL Coarse Tuning Loop Filter Capacitor # NET 'ADC_PLL_COARSE_FILTER' C709-1 # Clock Multiplier PLL NET 'GROUND' C709-2 # Coarse Tuning Loop # Filter Capacitor # # Current Reference Resistor # NET 'ADC_CURRENT_REFERENCE' R601-1 # ADC Current Reference NET 'GROUND' R601-2 # Resistor