# # PMT ADC Sundry Net List # --------------------------- # # # Original Rev. 23-Feb-2023 # Current Rev. 11-July-2024 # # PMT ADC Sundry Nets # # Recall that all 100 pins on the PMT ADC are defined, # i.e. all pins are assigned net names, in the file: # # pmt_adc_pin_net_list.txt # # # PMT ADC Temperature Diode and Power Down / Standby # --------------------------------------------------------- # NET 'PMT_ADC_Temp_Diode' TP601-1 # Temp Diode Signal to Single SMD Pad # The HI Active PMT ADC Power_Down/Standby pin # is Grounded in the Net List file for the ADC itself. # # SPI Bus Connection between FPGA/CPU and PMT ADC 3-Wire SPI # ----------------------------------------------------------------- # # List the NetNames of the Signals that must be # connected to FPGA Floating Pins. Here just list # the NetNames - the actual connections to these # FPGA Floating pins are made in the Nets File: # # fpga_cpu_floating_connection_nets.txt # # ---------------------------------------------------- # # # All of these are 1V8 signals: PMT ADC SPI Bus # -------------------------------------------------- # # NET 'PMT_ADC_CHIP_SELECT_B' # ADC SPI Chip Select Active LOW # NET 'PMT_ADC_SPI_CLOCK' # ADC SPI Clock # NET 'PMT_ADC_SPI_DATA_IO' # ADC SPI Data I/O # # # CLOCK Type Signals that are sent to the PMT ADC from Timing Generator & FPGA # ----------------------------------------------------------------------------------- # # # Review of the Clock type signals that are inputs to the AD9083 # # See pages: 10, 15, 25, 26 of the AD9083 Datasheet # # Clock is 100 Ohm internally terminated, Clamp is 1 diode above AVDD, # ------- the input has a weak self DC Biased of 0.5 Volts, # the input should be AC coupled, # the Input Amplitude should be 800 to 1800 mV pk-pk # # System_Reference is 100 Ohm internally terminated, Clamp is 1 diode above AVDD, # ---------------- the input has a weak self DC Biased of 0.5 Volts, # the Input Common Mode should be 0.5 V # the Input Amplitude should be 700 to 1100 mV pk-pk # AD says this input is LVDS compatable # # Trigger is 100 Ohm internally terminated, Clamp is 1 diode above AVDD, # ------- the input has a weak self DC Biased of 0.5 Volts, # the Input Common Mode should be 0.5 V # the Input Amplitude should be 700 to 1100 mV pk-pk # AD says this input is LVDS compatable # # Sync_In_B has an internal 100 Ohm terminated that can be enabled, # --------- Clamp is 2 diodes above DVDD1P8, # in its the Input Common Mode should be 0.45 V # Diff Mode the Input Amplitude should be 700 to 1900 mV pk-pk # AD says this input is LVDS compatable # # # Concerns: AD calls the System_Reference and Trigger inputs "LVDS" # but they are not normal LVDS because their Common Mode is # too Low. Concern - are the 3V3 LVDS outputs from the FPGA/CPU # really true 3 mA Current Mode outputs or are they some # LVDS Like volltage mode thing that will over drive these # AD9083 inputs ? E.G. should I use series resistors ? # # See the AD Engineering Note about the "LVDS" inputs to # the AD9083 ADC. This note is on the MSU DK web site. # # # The PMT ADC CLOCK signal is AC coupled and # comes from the Timing Generator Output 0-A # NET 'PMT_ADC_CLOCK_DIR' C941-2 # ADC Converter Clock DIR Timing Generator Output NET 'PMT_ADC_CLOCK_CMP' C942-2 # ADC Converter Clock CMP 0-A AC Cooupling Caps # # The PMT ADC SYSTEM REFERENCE signal is DC coupled # and comes from the Timing Generator Output 0-B # NET 'PMT_ADC_SYS_REF_DIR' R925-2 # DC Coupled signal from the NET 'PMT_ADC_SYS_REF_CMP' R926-2 # Timing Generator Output 0-B # # The PMT ADC SYNC_In_B signal is DC coupled # and comes from a LVDS output on the FPGA/CPU. # # Note that SYNC_In_B does not need an external 100 Ohm Terminator. # The ADC has an internal 100 Ohm terminator for Sync_In_B that # can be enabled by a control register. # # Signal PMT_ADC_SYNC_In_B_DIR is PMT ADC pin A2 ADC JESD204B Sync In B DIR # Signal PMT_ADC_SYNC_In_B_CMP is PMT ADC pin A3 ADC JESD204B Sync In B CMP # # # The PMT ADC TRIGGER signal is not used in the DK design # PMT ADC TRIGGER is tied off to hold it at a Logic Low. # NET 'PMT_ADC_Trigger_DIR' R603-2 # ADC Trigger Dir Input NET 'PMT_ADC_Trigger_CMP' R604-2 # ADC Trigger Cmp Input NET 'GROUND' R603-1 # Pull Down on the Hi side of the Trigger input NET 'ADC_DIGITAL_1V0' R604-1 # Pull Up on the Low side of the Trigger input # # Clock type Signals from the FPGA/CPU to the PMT ADC # ----------------------------------------------------------- # # List the NetNames of the Signals that must be # connected to FPGA Floating Pins. Here just list # the NetNames - the actual connections to these # FPGA Floating pins are made in the Nets File: # # fpga_cpu_bank_9_floating_nets_fcg1152.txt # # ---------------------------------------------------- # # # All of these are LVDS signals: PMT ADC Clock Type Signals # -------------------------------------------------------------- # # NET 'PMT_ADC_SYNC_IN_B_DIR' # ADC JESD204B Sync In B DIR # NET 'PMT_ADC_SYNC_IN_B_CMP' # ADC JESD204B Sync In B CMP # # # End of this big section about CLOCK Type Signals # ----------------------------------------------------- # # # Clock Multiplier PLL Voltage Regulator Bypass Capacitors # NET 'ADC_PLL_REG_BYPASS' C689-1 C690-2 C699-2 # Clock Multiplier PLL NET 'GROUND' C689-2 C690-1 C699-1 # Voltage Regulator # Bypass Capacitors # # Clock Multiplier PLL Coarse Tuning Loop Filter Capacitor # NET 'ADC_PLL_COARSE_FILTER' C709-2 # Clock Multiplier PLL NET 'GROUND' C709-1 # Coarse Tuning Loop # Filter Capacitor # # Current Reference Resistor # NET 'ADC_CURRENT_REFERENCE' R601-2 # ADC Current Reference NET 'GROUND' R601-1 # Resistor