# # SFP Connector & Cage Pin Net List # ------------------------------------- # # # Original Rev. 23-Feb-2023 # Current Rev. 26-Dec-2023 # # # This Net List file assigns net names and makes # connections to all pins on the SFP Connector and # the SFP Cage. # # NOTE: Currently (11-Dec-2023) my understanding is that # any/all SFP Modules that are used with the DK Board # do include their own AC Coupling capacitors. # # Thus external AC Coupling caps on the DK board itself # have NOT been included in the DK design for either # Rx or Tx channel for either the Timing or Ethernet # SFP modules. # # # This Net List file includes most of the connections to the # PCA9546A I2C Bus Fan-Out chip. This I2C Fan-Out is used # to allow the I2C Controller #0 in the FPGA/CPU to talk to: # both of the SFP Modules on the DK and to the AD9546 # Timing Generator. There is an un-used 4th port on this # Fan-Out (port #3) where it can be left parked to provide # a layer of isolation and protection to important control # registers, e.g. in the Timing Generator. # # This Net List file includes many connections to "Floating" # pins on the FPGA/CPU. The Floating pin connections are # all listed together at the end of this Net List file. # These Floating pins on the FPGA/CPU are assigned to # specific physical pins in the Net List file: # fpga_cpu_floating_connection_nets.txt # # NOTE: Two section of the U1602 Quad NAND are used for # functions that are not directly related to the # SFP Modules: U1602 4,5,6 is used to make the # DK_CPU_Is_Sane_B signal that is used by the # Emergency Rescue circuits and U1602 8,9,10 # is used to make a Spare Run signal in the # Startup and Resets net lists. # # # Timing SFP J13 Rx and Tx Data Connections with NO External AC Coupling caps # ------------------------------------------------------------------------------------ # # SFP_Time_RD_DIR J13-13 # Receiver DIR data output to Time Gen Ref A Input DIR # SFP_Time_RD_CMP J13-12 # Receiver CMP data output to Time Gen Ref A Input CMP # # The Timing SFP Receiver Output is connected to the # Timing Generator Reference A Input. This connection # is made in the timing_generator_nets.txt file. # SFP_Time_TD_DIR J13-18 # Transmitter DIR data input from Time Gen Output 0-C DIR # SFP_Time_TD_CMP J13-19 # Transmitter CMP data input from Time Gen Output 0-C CMP # # The Timing SFP Transmitter Input is connected to the # Timing Generator Output 0-C. This connection # is made in the timing_generator_nets.txt file. # # Ethernet SFP J14 Rx and Tx Data Connections with NO External AC Coupling caps # -------------------------------------------------------------------------------------- # NET 'SFP_ENet_RD_DIR' U1-T26 # Receiver DIR data output to FPGA XCVR_0_Rx_1_Dir NET 'SFP_ENet_RD_CMP' U1-T25 # Receiver CMP data output to FPGA XCVR_0_Rx_1_Cmp # The ENet SFP Receiver Output is routed to the # XCVR_0 Rx_1 Input on the FPGA/CPU. # XCVR_0_Rx_1_Dir is pin T26 # XCVR_0_Rx_1_Cmp is pin T25 NET 'SFP_ENet_TD_DIR' U1-U28 # Transmitter DIR data input from FPGA XCVR_0_Tx_1_Dir NET 'SFP_ENet_TD_CMP' U1-U27 # Transmitter CMP data input from FPGA XCVR_0_Tx_1_Cmp # The ENet SFP Transmitter Input is routed from # the XCVR_0 Tx_1 Output of the FPGA/CPU. # XCVR_0_Tx_1_Dir is pin U28 # XCVR_0_Tx_1_Cmp is pin U27 # # Pull-Up Resistors and Connections to: Tx_Fault, Mod_Present, Rx_Loss # ------------------------------------------------------------------------- # # These 3 pins are Outputs from each SFP module are routed to # "Floating" GPIO Input pins on the FPGA/CPU. All of the # connections in this Net List files that are made to Floating # pins on the FPGA/CPU are summerized in a section below. # # The actual assignment of these signals to a physical pins # on the FPGA/CPU is made in the Net List file: # fpga_cpu_floating_connection_nets.txt # # Timing SFP J13 Connections for: Tx_Fault, Mod_Present, Rx_Loss NET 'SFP_Time_TX_Fault' R1605-2 # Module Tx Fault to FPGA/CPU GPIO 3V3 Input NET 'SFP_Time_MOD_ABS' R1602-2 # Module Absent to FPGA/CPU GPIO 3V3 Input NET 'SFP_Time_RX_LOS' R1601-2 # Rx Signal Loss to FPGA/CPU GPIO 3V3 Input NET 'BULK_3V3' R1601-1 R1602-1 R1605-1 # Pull-Up 3V3 Source # Ethernet SFP J14 Connections for: Tx_Fault, Mod_Present, Rx_Loss NET 'SFP_ENet_TX_Fault' R1610-2 # Module Tx Fault to FPGA/CPU GPIO 3V3 Input NET 'SFP_ENet_MOD_ABS' R1607-2 # Module Absent to FPGA/CPU GPIO 3V3 Input NET 'SFP_ENet_RX_LOS' R1606-2 # Rx Signal Loss to FPGA/CPU GPIO 3V3 Input NET 'BULK_3V3' R1606-1 R1607-1 R1610-1 # Pull-Up 3V3 Source # # SFP Connector Pins: Tx_Disable, Rate_Select_0, Rate_Select_1 # ------------------------------------------------------------------------- # # These 3 pins are Inputs to each SFP module. # # For our use on the DK Board the Tx_Disable needs to be # controlled by a GPIO output signal from the FPGA/CPU. # I will include a series terminator in this line as it # may need to be banged about quite a bit. # # Normally the two Rate_Select pins are not used - but # because of the special types of SFP modules that may be # used on the DK board I will also route the two Rate_Select # pins from the SFP connectors to GPIO pins on the FPGA/CPU. # # The Tx_Disable and the Rate_Select connections to the # FPGA/CPU are to Floating GPIO pin assignments. # # The actual assignment of these signals to a physical pins # on the FPGA/CPU is made in the Net List file: # fpga_cpu_floating_connection_nets.txt # # # The Tx_Disable has 2 jumper selectable options: # # - Install the Ground jumper (JMP1601 JMP1603) # and the Tx Laser is forced ON continuously. # # - Install the FPGA/CPU control jumper (JMP1602 # JMP1604) to require both the DK_CPU_Is_Sane # signal AND the SFP_x_Trans_Enable signal from # the FPGA/CPU to both be HI in order for the # SFP module Tx Laser to come ON. # NOTE: The control signal from the FPGA/CPU is # an "Enable" type signal (not a disable). # # # Tx Disable for the Timing SFP: # --------------------------======------------------ # NET 'SFP_Time_Trans_Enable' R1615-2 # Time SFP Tx Enable from FPGA/CPU GPIO Output NET 'SFP_Time_Tx_Enb_Term' R1615-1 U1602-2 # Time SFP Tx Enable to NAND Gate NET 'SFP_Time_Tx_Enb_Jmpr' U1602-3 JMP1602-1 # Time SFP Tx Enable to Jumper NET 'SFP_Time_TX_Disable' JMP1601-1 JMP1602-2 # Time SFP Tx Disabled Pin #3 NET 'GROUND' JMP1601-2 # Ground Jumper Laser forced ON # # Tx Disable for the Ethernet SFP: # --------------------------========---------------- # NET 'SFP_ENet_Trans_Enable' R1616-2 # ENet SFP Tx Enable from FPGA/CPU GPIO Output NET 'SFP_ENet_Tx_Enb_Term' R1616-1 U1602-12 # ENet SFP Tx Enable to NAND Gate NET 'SFP_ENet_Tx_Enb_Jmpr' U1602-11 JMP1604-1 # ENet SFP Tx Enable to Jumper NET 'SFP_ENet_TX_Disable' JMP1603-1 JMP1604-2 # ENet SFP Tx Disabled Pin #3 NET 'GROUND' JMP1603-2 # Ground Jumper Laser forced ON # # DK_CPU_Is_Sane Distribution to the Tx Disable Circuits: # ------------------------------------------------------------------ # NET 'DK_CPU_Is_Sane' U1602-1 U1602-13 # CPU_Sane to the Tx Disable Gates NET 'DK_CPU_Is_Sane' U1602-4 U1602-5 # CPU_Sane to the Inverter Gate NET 'DK_CPU_Is_Sane' U1602-10 # CPU_Sane to the TOMCat Reset Gate NET 'DK_CPU_Is_Sane_B' U1602-6 # CPU_Sane_B to the Emergency Rescue Circuits # # Tx Disable NAND Gate Power and Ground: # -------------------------------------------------- # NET 'BULK_3V3' C1615-2 U1602-14 # Bulk_3V3 Bypass and Power NET 'GROUND' C1615-1 U1602-7 # Ground the Bypass and Chip # # Pull-Up Resistors and Connection for the: SFP <--> I2C Fan-Out I2C Links # ------------------------------------------------------------------------------- # # Timing SFP J13 Connection for: I2C Link to the I2C Fan-Out Ch #1 NET 'SFP_Time_SCL' R1603-2 U1601-7 # Time SFP I2C SCLK to Fan-Out Channel 1 NET 'SFP_Time_SDA' R1604-2 U1601-6 # Time SFP I2C SDATA to Fan-Out Channel 1 NET 'BULK_3V3' R1603-1 R1604-1 # Pull-Up 3V3 Source # Ethernet SFP J14 Connection for: I2C Link to the I2C Fan-Out Ch #2 NET 'SFP_ENet_SCL' R1608-2 U1601-10 # ENet SFP I2C SCLK to Fan-Out Channel 2 NET 'SFP_ENet_SDA' R1609-2 U1601-9 # ENet SFP I2C SDATA to Fan-Out Channel 2 NET 'BULK_3V3' R1608-1 R1609-1 # Pull-Up 3V3 Source # # I2C Fan-Out Channel Ch #0 Connection to the Timing Generator U901 # --------------------------------------------------------------------------- # # This Net List file just defines the Channel #0 pins on the # I2C Fan-Out chip that provide the I2C Bus to setup and monitor # the AD9546 Timing Generator. The pull-up resistors for this # I2C link and the connections to the Timing Generator are all # made in the Net List file: timing_generator_nets.txt NET 'TG_I2C_SCLK' U1601-5 # I2C Fan-Out Ch #0 SCLK to the Timing Generator NET 'TG_I2C_SDATA' U1601-4 # I2C Fan-Out Ch #0 SDATA to the Timing Generator # # Pull-Up Resistors for the Un-Used I2C Fan-Out Channel Ch #3 # --------------------------------------------------------------------------- # NET 'I2C_CTRL_0_FAN_Ch_3_SCL' R1613-2 U1601-12 # Un-Used I2C_Fan-Out Channel 3 SCLK NET 'I2C_CTRL_0_FAN_Ch_3_SDA' R1614-2 U1601-11 # Un-Used I2C_Fan-Out Channel 3 SDATA NET 'BULK_3V3' R1613-1 R1614-1 # Pull-Up 3V3 Source # # Pull-Up Resistors and Connection for the: FPGA/CPU <--> I2C Fan-Out I2C Link # ----------------------------------------------------------------------------------- # NET 'CPU_I2C_Ctrl_0_SCL' R1611-2 U1601-14 # FPGA/CPU Controller 0 I2C SCLK to Fan-Out NET 'CPU_I2C_Ctrl_0_SDA' R1612-2 U1601-15 # FPGA/CPU Controller 0 I2C SDATA to Fan-Out NET 'BULK_3V3' R1611-1 R1612-1 # Pull-Up 3V3 Source # # I2C Fan-Out Address Pins # --------------------------------------------------------------------------- # # The 3 Address pins on the PCA9546A I2C Fan-out chip are # all tied to ground. These connections are made on the PCB # with sufficiently long runs so that they may be changed in # an emergency. # # This gives the I2C Fan-Out chip itself an Address of 0x70 # when written as 3 MS Bit and 4 LS Bit expressed in hex. # NET 'GROUND' U1601-1 U1601-2 U1601-13 # Ground all 3 Address pins # # I2C Fan-Out RESET_B Pin # --------------------------------------------------------------------------- # # The RESET_B pin on the PCA9546A is controlled by the signal # from a GPIO pin on the FPGA/CPU. This connection is to a # Floating pin on the FPGA/CPU NET 'CPU_I2C_Ctrl_0_Fan_Out_RESET_B' U1601-3 # I2C Fanout Reset_B from FPGA/CPU GPIO # # Power and Ground to the I2C Fan-Out: # ------------------------------------------------------------------------- # NET 'BULK_3V3' C1614-2 C1613-2 U1601-16 # Bulk_3V3 Bypass and Power NET 'GROUND' C1614-1 C1613-1 U1601-8 # Ground the Bypass and Chip # # Timing SFP J13 Connector Pins # --------------------------------- # NET 'GROUND' J13-1 # Module Transmitter Ground NET 'SFP_Time_TX_Fault' J13-2 # Module Transmitter Fault NET 'SFP_Time_TX_Disable' J13-3 # Transmitter Disabled NET 'SFP_Time_SDA' J13-4 # 2-wire Serial Data NET 'SFP_Time_SCL' J13-5 # 2-wire Serial Clock NET 'SFP_Time_MOD_ABS' J13-6 # Module Absent NET 'SFP_Time_RS_0' J13-7 # Rate Select 0 NET 'SFP_Time_RX_LOS' J13-8 # Receiver Loss of Signal Indication NET 'SFP_Time_RS_1' J13-9 # Rate Select 1 NET 'GROUND' J13-10 # Module Receiver Ground NET 'GROUND' J13-11 # Module Receiver Ground NET 'SFP_Time_RD_CMP' J13-12 # Receiver Inverted Data Output NET 'SFP_Time_RD_DIR' J13-13 # Receiver NonInverted Data Output NET 'GROUND' J13-14 # Module Receiver Ground NET 'SFP_Time_VccR' J13-15 # Module Receiver 3.3 V Supply NET 'SFP_Time_VccT' J13-16 # Module Transmitter 3.3 V Supply NET 'GROUND' J13-17 # Module Transmitter Ground NET 'SFP_Time_TD_DIR' J13-18 # Transmitter NonInverted Data Input NET 'SFP_Time_TD_CMP' J13-19 # Transmitter Inverted Data Input NET 'GROUND' J13-20 # Module Transmitter Ground # # EtherNet SFP J14 Connector Pins # ----------------------------------- # NET 'GROUND' J14-1 # Module Transmitter Ground NET 'SFP_ENet_TX_Fault' J14-2 # Module Transmitter Fault NET 'SFP_ENet_TX_Disable' J14-3 # Transmitter Disabled NET 'SFP_ENet_SDA' J14-4 # 2-wire serial Data NET 'SFP_ENet_SCL' J14-5 # 2-wire serial Clock NET 'SFP_ENet_MOD_ABS' J14-6 # Module Absent NET 'SFP_ENet_RS_0' J14-7 # Rate Select 0 NET 'SFP_ENet_RX_LOS' J14-8 # Receiver Loss of Signal Indication NET 'SFP_ENet_RS_1' J14-9 # Rate Select 1 NET 'GROUND' J14-10 # Module Receiver Ground NET 'GROUND' J14-11 # Module Receiver Ground NET 'SFP_ENet_RD_CMP' J14-12 # Receiver Inverted Data Output NET 'SFP_ENet_RD_DIR' J14-13 # Receiver NonInverted Data Output NET 'GROUND' J14-14 # Module Receiver Ground NET 'SFP_ENet_VccR' J14-15 # Module Receiver 3.3 V Supply NET 'SFP_ENet_VccT' J14-16 # Module Transmitter 3.3 V Supply NET 'GROUND' J14-17 # Module Transmitter Ground NET 'SFP_ENet_TD_DIR' J14-18 # Transmitter NonInverted Data Input NET 'SFP_ENet_TD_CMP' J14-19 # Transmitter Inverted Data Input NET 'GROUND' J14-20 # Module Transmitter Ground # # Power Feeds to the SFP Connectors # ------------------------------------- # # Timing SFP J13 Receiver NET 'BULK_3V3' L1601-1 C1601-1 # Power Feed to Rx Filter NET 'GROUND' C1601-2 # Ground this Bypass Cap NET 'SFP_Time_VccR' L1601-2 # Power Feed to J13 Rx NET 'SFP_Time_VccR' C1605-2 C1606-2 # Bypass on J13 Rx NET 'GROUND' C1605-1 C1606-1 # Ground these Bypass Caps # Timing SFP J13 Transmitter NET 'BULK_3V3' L1602-1 C1602-1 # Power Feed to Tx Filter NET 'GROUND' C1602-2 # Ground this Bypass Cap NET 'SFP_Time_VccT' L1602-2 # Power Feed to J13 Tx NET 'SFP_Time_VccT' C1607-2 C1608-2 # Bypass on J13 Tx NET 'GROUND' C1607-1 C1608-1 # Ground these Bypass Caps # Ethernet SFP J14 Receiver NET 'BULK_3V3' L1603-1 C1603-1 # Power Feed to Rx Filter NET 'GROUND' C1603-2 # Ground this Bypass Cap NET 'SFP_ENet_VccR' L1603-2 # Power Feed to J14 Rx NET 'SFP_ENet_VccR' C1609-2 C1610-2 # Bypass on J14 Rx NET 'GROUND' C1609-1 C1610-1 # Ground these Bypass Caps # Ethernet SFP J14 Transmitter NET 'BULK_3V3' L1604-1 C1604-1 # Power Feed to Tx Filter NET 'GROUND' C1604-2 # Ground this Bypass Cap NET 'SFP_ENet_VccT' L1604-2 # Power Feed to J14 Tx NET 'SFP_ENet_VccT' C1611-2 C1612-2 # Bypass on J14 Tx NET 'GROUND' C1611-1 C1612-1 # Ground these Bypass Caps # # SFP Twin Cage Ground Pins # ----------------------------- # NET 'GROUND' CAGE_1-1 CAGE_1-2 CAGE_1-3 CAGE_1-4 CAGE_1-5 NET 'GROUND' CAGE_1-6 CAGE_1-7 CAGE_1-8 CAGE_1-9 CAGE_1-10 NET 'GROUND' CAGE_1-11 CAGE_1-12 CAGE_1-13 CAGE_1-14 CAGE_1-15 NET 'GROUND' CAGE_1-16 CAGE_1-17 CAGE_1-18 CAGE_1-19 CAGE_1-20 NET 'GROUND' CAGE_1-21 CAGE_1-22 CAGE_1-23 CAGE_1-24 CAGE_1-25 # # List the NetNames of the Signals that must be # connected to FPGA Floating Pins. Here just list # the NetNames - the actual connections to these # FPGA Floating pins are made in the Nets File: # fpga_cpu_floating_connection_nets.txt # ---------------------------------------------------- # # # All of these are 3V3 signals: SFP Control and Monitor and # FPGA/CPU I2C Controller #0 # --------------------------------------------------------------------------- # # # NET 'SFP_Time_TX_Fault' # Time SFP Tx Fault to FPGA/CPU GPIO Input # NET 'SFP_Time_MOD_ABS' # Time SFP Module Absent to FPGA/CPU GPIO Input # NET 'SFP_Time_RX_LOS' # Time SFP Rx Signal Loss to FPGA/CPU GPIO Input # # NET 'SFP_Time_Trans_Enable' # Time SFP Tx Enable from FPGA/CPU GPIO Output # # NET 'SFP_Time_RS_0' # Time SFP Rate Select 0 <--> FPGA/CPU GPIO I/O # NET 'SFP_Time_RS_1' # Time SFP Rate Select 1 <--> FPGA/CPU GPIO I/O # # # NET 'SFP_ENet_TX_Fault' # ENet SFP Tx Fault to FPGA/CPU GPIO Input # NET 'SFP_ENet_MOD_ABS' # ENet SFP Module Absent to FPGA/CPU GPIO Input # NET 'SFP_ENet_RX_LOS' # ENet SFP Rx Signal Loss to FPGA/CPU GPIO Input # # NET 'SFP_ENet_Trans_Enable' # ENET SFP Tx Enable from FPGA/CPU GPIO Output # # NET 'SFP_ENet_RS_0' # Time SFP Rate Select 0 <--> FPGA/CPU GPIO I/O # NET 'SFP_ENet_RS_1' # Time SFP Rate Select 1 <--> FPGA/CPU GPIO I/O # # # NET 'CPU_I2C_Ctrl_0_SCL' # FPGA/CPU Controller 0 I2C SCLK to Fan-Out # NET 'CPU_I2C_Ctrl_0_SDA' # FPGA/CPU Controller 0 I2C SDATA to Fan-Out # # NET 'CPU_I2C_Ctrl_0_Fan_Out_RESET_B' # I2C Fanout Reset_B from FPGA/CPU GPIO # # # Below here is some SFP reference information # ---------------------------------------------- # # # Note that Pin #9 has a different function # in the SFP vs SFP+ pinouts # # # SFP Network Port Connector Pinout # --------------------------------- # # 1 VeeT Module transmitter ground # 2 TX_Fault Module transmitter fault # 3 TX_Disable Transmitter disabled # 4 SDA 2-wire serial interface data line # 5 SCL 2-wire serial interface clock # # 6 MOD_ABS Module absent # 7 RS Rate select # 8 RX_LOS Receiver loss of signal indication # 9 VeeR Module receiver ground # 10 VeeR Module receiver ground # # 11 VeeR Module receiver ground # 12 RD- Receiver inverted data output # 13 RD+ Receiver noninverted data output # 14 VeeR Module receiver ground # 15 VccR Module receiver 3.3 V supply # # 16 VccT Module transmitter 3.3 V supply # 17 VeeT Module transmitter ground # 18 TD+ Transmitter noninverted data input # 19 TD- Transmitter inverted data input # 20 VeeT Module transmitter ground # # # # SFP+ Network Port Connector Pinout # ---------------------------------- # # 1 VeeT Module transmitter ground # 2 TX_Fault Module transmitter fault # 3 TX_Disable Transmitter disabled # 4 SDA 2-wire serial interface data line # 5 SCL 2-wire serial interface clock # # 6 MOD_ABS Module absent # 7 RS0 Rate select 0, optionally controls SFP+ module receiver # 8 RX_LOS Receiver loss of signal indication # 9 RS1 Rate select 1, optionally controls SFP+ transmitter # 10 VeeR Module receiver ground # # 11 VeeR Module receiver ground # 12 RD- Receiver inverted data output # 13 RD+ Receiver noninverted data output # 14 VeeR Module receiver ground # 15 VccR Module receiver 3.3-V supply # # 16 VccT Module transmitter 3.3-V supply # 17 VeeT Module transmitter ground # 18 TD+ Transmitter noninverted data input # 19 TD- Transmitter inverted data input # 20 VeeT Module transmitter ground #