# # Startup and Reset Nets # --------------------------- # # # Disco-Kraken Key In Net List # ------------------------------- # # # Initial Rev. 15-Dec-2022 # Current Rev. 4-Jan-2024 # # # This net list holds the Startup and Reset # nets. # # The components in the Startup and Reset # section of the design have reference # designators in the range 1151 :1199 # # NOTE: below the use of one section in the U1402 hex inverter # to handle inverting the DK_CPU_Is_Awake_B signal. # U1402 officially belongs to the DK FPGA/CPU JTAG # circuits and appears in that net list file. # # NOTES: The Startup and Resets ICs U1151 through U1155 are # powered by the "always ON" CNST_3V3 supply where as # the associated Pull-Up resistors R1171 & R1172 are # powered by BULK_3V3 because there is no need or # desire for the signals pulled up by these resistors # to be in the HI state before the BULK_3V3 has # finished its ramp up. # # U1156 and the Pull-Up Resistor R1177 are powered by # the BULK_5V0 supply because this circuit must supply # a glitch free Master_Reset_B to the Barnacle Interface # as the BULK_5V0 supply ramps up. # # Two section of the U1602 Quad NAND (which is officially # part of the SFP control circuits) are used by the # Startup and Reset circuits that are described below. # U1602 4,5,6 is used to make the DK_CPU_Is_Sane_B # signal that is used by the Emergency Rescue circuits # and U1602 8,9,10 is used to make a Spare Run signal. # # # Startup Delay TPS3808s U1151 - Senses the Bulk_5V0 and # --------------- Makes the DCDC Converter "Track Bus": # ----------------------------------------------------------------------------- # NET 'BULK_5V0' R1161-1 # Bulk 5V0 to the Sense Resistor Divider NET 'Start_Delay_Sense' R1161-2 R1162-1 # Sense Input to the Startup Delay NET 'Start_Delay_Sense' U1151-5 C1161-1 # Sense Input to the Startup Delay NET 'GROUND' R1162-2 C1161-2 # Ground Volt Divider and Filter Cap NET 'Start_Delay_Cap_T' U1151-4 C1162-1 # Start Delay Timing Cap NET 'GROUND' C1162-2 # Ground Timing Cap NET 'NO_CONN_U1151_Pin_3' U1151-3 # Un-Used Start Delay MR_B pin NET 'DCDC_Conv_Track' U1151-1 # Start Delay Reset_B pin # "Track Bus" to the 7 DCDC converters # # All Power Good TPS3808s U1152 - Senses the Bulk_3V3 and # ---------------- Makes the Delayed_All_Power_Good signal: # ----------------------------------------------------------------------------------- # NET 'BULK_3V3' R1163-1 # Bulk 3V3 to the Sense Resistor Divider NET 'All_Good_Delay_Sense' R1163-2 R1164-1 # Sense Input to the All_Power_Good Delay NET 'All_Good_Delay_Sense' U1152-5 C1163-1 # Sense Input to the All_Power_Good Delay NET 'GROUND' R1164-2 C1163-2 # Ground Volt Divider and Filter Cap NET 'All_Good_Delay_Cap_T' U1152-4 C1164-1 # All_Power_Good Delay Timing Cap NET 'GROUND' C1164-2 # Ground Timing Cap NET 'NO_CONN_U1152_Pin_3' U1152-3 # Un-Used All Power Good MR_B pin NET 'Delayed_All_Power_Good' U1152-1 # All Power Good Delay Reset_B pin # Delayed_All_Power_Good to the Reset Circuits # # Make the "CPU IS SANE" and "FPGA/CPU_Reset_B" signals: # -------------------------------------------------------------- # # NOTE: the use of one section in the U1402 hex inverter # to handle inverting the DK_CPU_Is_Awake_B signal. # U1402 officially belongs to the DK FPGA/CPU JTAG # circuits and appears in that net list file. # # The DK_CPU_Is_Sane signal is made below by U1153 # and DK_CPU_Is_Sane_B is made in the SFP net list file # by U1602. # NET 'Delayed_All_Power_Good' R1171-1 U1153-5 U1155-1 # Pull-Up on Delayed All Power Good NET 'BULK_3V3' R1171-2 # 3V3 Pull-Up Source NET 'FPGA_CPU_RESET_B' R1172-1 U1-H9 U1155-2 # Reset to the FPGA/CPU NET 'BULK_3V3' R1172-2 # 3V3 Pull-Up Source NET 'DK_CPU_Is_Awake' R1173-1 U1153-2 # CPU is Awake & its Pull-Down NET 'GROUND' R1173-2 # Pull-Down Anchor NET 'DK_CPU_Is_Awake_B' R1174-1 U1402-1 # CPU is Awake_B to Inverter & Pull-Up NET 'CNST_3V3' R1174-2 # 3V3 Pull-Up Source NET 'DK_CPU_Is_Awake_B_INV' U1402-2 U1153-1 # Inverted Awake_B to AND NET 'DK_CPU_Awake_AND_B' U1153-3 U1153-4 # Awake & _B to AND with Delayed All Good NET 'DK_CPU_Is_Sane' R1178-1 U1153-6 # DK_CPU_Is_Sane for Distribution NET 'GROUND' R1178-2 # Pull-Down on DK_CPU_Is_Sane with 4.7k # so that it is defined even before the # CNST_3V3 supply is fully ramped up. # In this way the Barnacle_Master_Reset_B # is defined Low while the BULK_5V0 ramps. # # Make the PMT_ADC_Reset_B this is a 1V8 Low Active signal: # ------------------------------------------------------------------ NET 'Run_PMT_ADC' U1153-9 # Run_PMT_ADC signal from CPU NET 'DK_CPU_Is_Sane' U1153-10 # AND with DK_CPU_Is_Sane NET 'DK_Sane__Run_PMT' U1153-8 U1155-3 # AND of Sane and Run_PMT NET 'PMT_ADC_Reset_B' U1155-4 R1175-1 # PMT_ADC_Reset_B signal NET 'BULK_1V8' R1175-2 # Pull-Up 1V8 Source # # Make the BB_Audio_ADC_Reset_B this is a 1V8 Low Active signal: # ----------------------------------------------------------------------- NET 'Run_BB_Audio_ADC' U1153-13 # Run_BB_Audio_ADC signal from CPU NET 'DK_CPU_Is_Sane' U1153-12 # AND with DK_CPU_Is_Sane NET 'DK_Sane__Run_BB_ADC' U1153-11 U1155-5 # AND of Sane and Run_BB_Audio_ADC NET 'BB_Audio_ADC_Reset_B' U1155-6 R1176-1 # BB_Audio_ADC_Reset_B signal NET 'BULK_1V8' R1176-2 # Pull-Up 1V8 Source # # Make the Clock_Generator_Reset_B this is a 3V3 Low Active signal: # -------------------------------------------------------------------------- NET 'Run_Clock_Generator' U1154-5 # Run_BB_Audio_ADC signal from CPU NET 'DK_CPU_Is_Sane' U1154-4 # AND with DK_CPU_Is_Sane NET 'Clock_Gen_Reset_B' U1154-6 # Clock_Gen_Reset_B signal # # Make the USB_Reset_B this is a 3V3 Low Active signal: # -------------------------------------------------------------- NET 'Run_USB_Interface' U1154-1 # Run_USB_Interface signal from CPU NET 'DK_CPU_Is_Sane' U1154-2 # AND with DK_CPU_Is_Sane NET 'USB_Reset_B' U1154-3 # USB_Reset_B signal # # Make a SPARE_Reset signal this is a 3V3 Hi Active signal: # # This Run Spare circuit uses U1602 which is officially # part of the SFP control circuits. In the SFP control # circuit net list file the DK_CPU_Is_Sane signal is # connected to pin U1602-10. # ------------------------------------------------------------------ NET 'Run_SPARE' U1602-9 # Run_Spare signal from CPU NET 'SPARE_Reset' U1602-8 # SPARE_Reset signal 3V3 Hi Active # Currently this Reset signal is not used. # # Make the Barnacle_Control_ 1 and 2 signals # # They are Open-Drain Outputs with Pull-Up Resistors on the Barnacle: # ----------------------------------------------------------------------- NET 'Barnacle_Control_1' U1154-13 # Barnacle_Control_1 signal from CPU NET 'DK_CPU_Is_Sane' U1154-12 # AND with DK_CPU_Is_Sane NET 'DK_Sane__Barn_Ctrl_1' U1154-11 U1155-13 # AND of Sane and Barn_Ctrl_1 NET 'DK_Control_1_to_Barnacle' U1155-12 # Control_1 signal to the Barnacle NET 'Barnacle_Control_2' U1154-9 # Barnacle_Control_2 signal from CPU NET 'DK_CPU_Is_Sane' U1154-10 # AND with DK_CPU_Is_Sane NET 'DK_Sane__Barn_Ctrl_2' U1154-8 U1155-11 # AND of Sane and Barn_Ctrl_2 NET 'DK_Control_2_to_Barnacle' U1155-10 # Control_2 signal to the Barnacle # # Make the Barnacle_Master_Reset_B signal # # This is an Open-Drain Output with its Pull-Up Resistor on the Barnacle: # Limit the Pull-Up current on the Barnacle to 500 uAmps # --------------------------------------------------------------------------- # NET 'DK_CPU_Is_Sane' R1165-1 # DK_CPU_Is_Sane CMOS Logic signal # input to voltage divider that NET 'Barn_Sense_Pin' R1165-2 R1166-1 # feeds the Sense pin on the NET 'Barn_Sense_Pin' C1165-1 U1156-5 # Barnacle_Master_Reset_B TPS3808 NET 'GROUND' C1165-2 R1166-2 # Ground low side divider and fltr cap NET 'Run_Barnacle' U1155-9 # Run_Barnacle 3V3 signal from the FPGA/CPU # input to the O.D. Buffer for conversion NET 'Run_Barn_5V' U1155-8 R1177-1 # to a 5V logic signal to feed the MR_B NET 'Run_Barn_5V' U1156-3 # input on the Barn_Master_Reset_B TPS3808 NET 'Bulk_5V0' R1177-2 # Pull-Up Source to Bulk_5V0 NET 'NO_CONN_Barnacle_U1156_pin_4' U1156-4 # Open TPS3808 Timing Pin ---> 20 msec. NET 'Barnacle_Master_Reset_B' U1156-1 # Master_Reset_B to the Barnacle # # Power and Ground to the ICs and their Bypass Caps: # ------------------------------------------------------- # NET 'CNST_3V3' U1151-6 U1152-6 # CNST_3V3 to the two Startup TPS3808s NET 'GROUND' U1151-2 U1152-2 # and their Ground NET 'CNST_3V3' U1153-14 U1154-14 U1155-14 # CNST_3V3 to the three Reset ICs NET 'GROUND' U1153-7 U1154-7 U1155-7 # and their Ground NET 'CNST_3V3' C1151-1 C1152-1 C1153-1 # CNST_3V3 to Bypass Caps NET 'GROUND' C1151-2 C1152-2 C1153-2 # and the Bypass Grounds NET 'CNST_3V3' C1154-1 C1155-1 # CNST_3V3 to Bypass Caps NET 'GROUND' C1154-2 C1155-2 # and the Bypass Grounds NET 'BULK_5V0' U1156-6 # 5V0 to the Barnacle Reset TPS3808 NET 'GROUND' U1156-2 # and its Ground NET 'BULK_5V0' C1156-1 # 5V0 to a Bypass Cap NET 'GROUND' C1156-2 # and that Bypass Ground # # List the NetNames of the Signals that must be # connected to FPGA Floating Pins. Here just list # the NetNames - the actual connections to these # FPGA Floating pins are made in the Nets File: # fpga_cpu_floating_connection_nets.txt # ---------------------------------------------------- # # # These are 3V3 signals: DK_CPU_Is_Awake (_B) and the RUN signals # ----------------------------------------------------------------------- # # NET 'DK_CPU_Is_Awake' # CPU is Awake signal # NET 'DK_CPU_Is_Awake_B' # CPU is Awake_B signal # # NET 'Run_PMT_ADC' # LOW ---> Reset the AD9083 PMT ADC # NET 'Run_Clock_Generator' # LOW ---> Reset the AD9546 Clock Generator # NET 'Run_USB_Interface' # LOW ---> Reset the USB3340 USB Transceiver # NET 'Run_BB_Audio_ADC' # LOW ---> Reset the TLV320ADC6140 BB Audio ADC # NET 'Run_SPARE' # Currently 26-Dec-2023 this signal is not used # # NET 'Run_Barnacle' # LOW ---> Barnacle Power Down and Master_Reset_B # NET 'Barnacle_Control_1' # Barnacle Control Signal 1 default is Low # NET 'Barnacle_Control_2' # Barnacle Control Signal 2 default is Low #