#   NET  'CPU_UART_0_Tx__to__Access'        # CPU UART 0 Tx Data  to  Access Connector
#   NET  'CPU_UART_0_Rx_from_Access'        # CPU UART 0 Rx Data from Access Connector
#   NET  'CPU_UART_1_Tx__to__ER_uProc'        # CPU UART 1 Tx Data  to  Emergency Rescue uProc
#   NET  'CPU_UART_1_Rx_from_ER_uProc'        # CPU UART 1 Rx Data from Emergency Rescue uProc
#   NET  'Access_Signal_1'      # Access Connector FPGA Signal #1 
#   NET  'Access_Signal_2'      # Access Connector FPGA Signal #2 
#   NET  'Access_Signal_3'      # Access Connector FPGA Signal #3 
#   NET  'Access_Signal_4'      # Access Connector FPGA Signal #4 
#   NET  'Access_Signal_5'      # Access Connector FPGA Signal #5 
#   NET  'Access_Diff_Pair_1_Dir'      # Access Connector FPGA Differential Pair #1 DIR
#   NET  'Access_Diff_Pair_1_Cmp'      # Access Connector FPGA Differential Pair #1 CMP
#   NET  'Access_Diff_Pair_2_Dir'      # Access Connector FPGA Differential Pair #2 DIR
#   NET  'Access_Diff_Pair_2_Cmp'      # Access Connector FPGA Differential Pair #2 CMP
#   NET  'CPU_UART_Tx__to__Barnacle'       # DK CPU UART Tx Data  to  Barnacle
#   NET  'CPU_UART_Rx_from_Barnacle'       # DK CPU UART Rx Data from Barnacle
#   NET  'FPGA_BB_ADC_CLK_Out'        # FPGA BB Audio ADC CLK  to  Term Resistor
#   NET  'FPGA_BB_ADC_SDATA_IN'       # Term Resistor  to  FPGA BB ADC SData Input
#   NET  'FPGA_BB_ADC_BCLK_IN'        # Term Resistor  to  FPGA BB ADC BCLK Input
#   NET  'FPGA_BB_ADC_FSYNC_IN'       # Term Resistor  to  FPGA BB ADC FSYNC Input
#   NET  'I2C_DATA_SENSOR_BB_ADC'      # Sensor & BB ADC  I2C Bus Data
#   NET  'I2C_SCLK_SENSOR_BB_ADC'      # Sensor & BB ADC  I2C Bus Clock
     NET  'Poser_SCLK_FPGA_to_Term'    U1-A10    # SCLK FPGA to Series Term
     NET  'Poser_MOSI_FPGA_to_Term'    U1-A12    # MOSI FPGA to Series Term
     NET  'Poser_MISO_Term_to_FPGA'    U1-A13    # MISO Mux Term to FPGA
#   NET  'Poser_CS_1_B'        # FPGA Signal to Enable Interposer #1 Mux _B
#   NET  'Poser_CS_2_B'        # FPGA Signal to Enable Interposer #2 Mux _B
#   NET  'Poser_CS_Adrs_0'     # CS Address 0   FPGA to Mux
#   NET  'Poser_CS_Adrs_1'     # CS Address 1   FPGA to Mux
#   NET  'Poser_CS_Adrs_2'     # CS Address 2   FPGA to Mux
#   NET  'CPU_UART_3_Tx__to__Poser_1'      # Tx UART 3 Data  to  Interposer_1 via Buffer
#   NET  'CPU_UART_3_Rx_from_Poser_1'      # Rx UART 3 Data from Interposer_1 via Buffer
#   NET  'CPU_UART_4_Tx__to__Poser_2'      # Tx UART 4 Data  to  Interposer_2 via Buffer
#   NET  'CPU_UART_4_Rx_from_Poser_2'      # Rx UART 4 Data from Interposer_2 via Buffer
#   NET  'Flash_Now'                       # Flash_Now   from the FPGA/CPU   to both
#   NET  'Interposer_Ctrl_Reset'           # Control Reset   to Both Interposers   from FPGA/CPU
#   NET  'SMUT_S1_Other_Hemi'              # Muon SMUT signal S1  from Other Hemisphere  to FPGA/CPU
#   NET  'SMUT_S2_Other_Hemi'              # Muon SMUT signal S2  from Other Hemisphere  to FPGA/CPU
#   NET  'SMUT_S3_Other_Hemi'              # Muon SMUT signal S3  from Other Hemisphere  to FPGA/CPU
#   NET  'SMUT_S4_Other_Hemi'              # Muon SMUT signal S4  from Other Hemisphere  to FPGA/CPU
#   NET  'PMT_ADC_CHIP_SELECT_B'       #  ADC SPI Chip Select  Active LOW
#   NET  'PMT_ADC_SPI_CLOCK'           #  ADC SPI Clock
#   NET  'PMT_ADC_SPI_DATA_IO'         #  ADC SPI Data I/O
#   NET  'PMT_ADC_SYNC_ENB_B_DIR'    #  ADC JESD204B Sync Enb B DIR
#   NET  'PMT_ADC_SYNC_ENB_B_CMP'    #  ADC JESD204B Sync Enb B CMP
#   NET  'PMT_ADC_Trigger_DIR'       #  ADC Trigger Dir Input
#   NET  'PMT_ADC_Trigger_CMP'       #  ADC Trigger Cmp Input
#   NET  'SFP_Time_TX_Fault'         # Time SFP Tx Fault        to  FPGA/CPU GPIO Input
#   NET  'SFP_Time_MOD_ABS'          # Time SFP Module Absent   to  FPGA/CPU GPIO Input
#   NET  'SFP_Time_RX_LOS'           # Time SFP Rx Signal Loss  to  FPGA/CPU GPIO Input
#   NET  'SFP_Time_Trans_Enable'     # Time SFP Tx Enable  from  FPGA/CPU GPIO Output
#   NET  'SFP_Time_RS_0'             # Time SFP Rate Select 0  <-->  FPGA/CPU GPIO I/O
#   NET  'SFP_Time_RS_1'             # Time SFP Rate Select 1  <-->  FPGA/CPU GPIO I/O
#   NET  'SFP_ENet_TX_Fault'         # ENet SFP Tx Fault        to  FPGA/CPU GPIO Input
#   NET  'SFP_ENet_MOD_ABS'          # ENet SFP Module Absent   to  FPGA/CPU GPIO Input
#   NET  'SFP_ENet_RX_LOS'           # ENet SFP Rx Signal Loss  to  FPGA/CPU GPIO Input
#   NET  'SFP_ENet_Trans_Enable'     # ENET SFP Tx Enable  from  FPGA/CPU GPIO Output
#   NET  'SFP_ENet_RS_0'             # Time SFP Rate Select 0  <-->  FPGA/CPU GPIO I/O
#   NET  'SFP_ENet_RS_1'             # Time SFP Rate Select 1  <-->  FPGA/CPU GPIO I/O
#   NET  'CPU_I2C_Ctrl_0_SCL'        # FPGA/CPU  Controller 0  I2C SCLK  to Fan-Out
#   NET  'CPU_I2C_Ctrl_0_SDA'        # FPGA/CPU  Controller 0  I2C SDATA to Fan-Out
#   NET  'CPU_I2C_Ctrl_0_Fan_Out_RESET_B'    # I2C Fanout Reset_B  from  FPGA/CPU GPIO
#   NET  'DK_CPU_Is_Awake'          # CPU is Awake   signal
#   NET  'DK_CPU_Is_Awake_B'        # CPU is Awake_B signal
#   NET  'Run_PMT_ADC'                # LOW ---> Reset the AD9083 PMT ADC
#   NET  'Run_Clock_Generator'        # LOW ---> Reset the AD9546 Clock Generator
#   NET  'Run_USB_Interface'          # LOW ---> Reset the USB3340 USB Transceiver
#   NET  'Run_BB_Audio_ADC'           # LOW ---> Reset the TLV320ADC6140 BB Audio ADC
#   NET  'Run_SPARE'                  # Currently  26-Dec-2023  this signal is not used
#   NET  'Run_Barnacle'              # LOW ---> Barnacle Power Down and Master_Reset_B
#   NET  'Barnacle_Control_1'        # Barnacle Control Signal 1   default is Low
#   NET  'Barnacle_Control_2'        # Barnacle Control Signal 2   default is Low
#   NET  'FPGA_Ref_Clk_to_USB_Phy'        # FPGA Clk Output to USB Phy Ref Clk Input