# # Timing Generator Net List # --------------------------------- # # # Initial Rev. 15-Nov-2022 # Current Rev. 12-Jan-2024 # # # This net list holds the Timing Generator # Net List. # # # The components for the Timing Generator # are in the range 901 to 949. # # # Timing Generator: Main Timing Inputs: # ------------------------------------------ # # Reference Input "A" Differential is # DK design pin names: TG_Ref_IN_A_Dir and TG_Ref_IN_A_Cmp # # Timing Generator Reference Input A is driven by the # output of the Timing SFP Receiver in SFP connector J13. # # An external 100 Ohm terminator is required # at this Timing Generator Input (R921) and this # Timing Generator Input must be set for AC Coupled # so that it supplies its own Common Mode voltage. # No External AC Coupling Capacitors are used. NET 'SFP_Time_RD_DIR' R921-1 U901-47 # Input TG_Ref_IN_A_Dir NET 'SFP_Time_RD_CMP' R921-2 U901-46 # Input TG_Ref_IN_A_Cmp NET 'TG_Ref_IN_B_Dir' U901-38 R925-1 # Unused REFB Input - Tie it Off NET 'TG_Ref_IN_B_Cmp' U901-39 R926-1 # Unused REFBB Input - Tie it Off # # The Timing Generator Reference Input B is not used. # Tie it Off so that this Differential Input is a valid Low. # NET 'TIME_GEN_1V8' R925-2 # 1V8 Source for the Tie Off Pull-Up NET 'GROUND' R926-2 # Ground Anchor on the Tie Off Pull-Down # # Timing Generator: Auxiliary Inputs: # ---------------------------------------- # # The VDDIOA and VDDIOB power feeds to the AD9546 Timing Generator # are 3V3 so these single ended inputs are 3V3 CMOS logic level. # # M0 is not used and is Tied Off Low # M1 is for Timing the FPGA "Flash Now" signal # M2 is for Timing the "Flash Seen" signal from Interposer #1 # M3 is for Timing the "Flash Seen" signal from Interposer #2 NET 'TG_Aux_IN_M0' U901-32 R924-1 # Tie Off Pull-Down connection to M0 NET 'TG_Aux_IN_M1' U901-33 NET 'TG_Aux_IN_M2' U901-35 NET 'TG_Aux_IN_M3' U901-36 NET 'GROUND' R924-2 # Ground Anchor on the Tie Off Pull-Down # # Timing Generator: Crystal Oscillator: # -------------------------------------- # NET 'TG_Crystal_XOA' U901-42 Y901-1 C951-1 # TG XOA Pin NET 'TG_Crystal_XOB' U901-43 Y901-3 C952-1 # TG XOA Pin NET 'GROUND' Y901-2 Y901-4 # Ground XTAL Pkg Pins NET 'GROUND' C951-2 C952-2 # Ground Tuning Caps # # Timing Generator: I2C Control Bus and Pull-Ups: # ------------------------------------------------------ # # The I2C bus for the Timing Generator comes from # the FPGA/CPU I2C Controller #0 Fan-Out (U1601) # and it is Channel #0 on this I2C Fan-Out chip. # NET 'TG_I2C_SCLK' U901-2 R922-1 # SCLK with I2C Controller #0 Fan-Out Ch #0 NET 'TG_I2C_SDATA' U901-4 R923-1 # SDATA with I2C Controller #0 Fan-Out Ch #0 NET 'BULK_3V3' R922-2 R923-2 # Pull-Up 3V3 Source # # Timing Generator: RESET Pin # ---------------------------- NET 'Clock_Gen_Reset_B' U901-48 # # Timing Generator: Do Not Connect Pins: # --------------------------------------- NET 'NO_CONN_TG_DNC_16' U901-16 NET 'NO_CONN_TG_DNC_21' U901-21 NET 'NO_CONN_TG_DNC_44' U901-44 # # Timing Generator: Outputs, Pull-Up Rs, and AC Coupling Cs: # -------------------------------------------------------------- # NET 'TG_Output_0A_Dir' U901-11 R911-1 C941-1 # Output 0A Dir NET 'TG_Output_0A_Cmp' U901-12 R912-1 C942-1 # Output 0A Cmp NET 'TG_Output_0B_Dir' U901-14 R913-1 # Output 0B Dir NET 'TG_Output_0B_Cmp' U901-15 R914-1 # Output 0B Cmp # Timing Generator Output 0-C is connected to the # Timing SFP Transmitter. This is the Return signal # to the Source of timing for the AD9546 Timing Generator. # No External AC Coupling Capacitors are used, no C945, C946. NET 'SFP_Time_TD_DIR' U901-17 R915-1 # Output 0C Dir TG_Output_0C_Dir NET 'SFP_Time_TD_CMP' U901-18 R916-1 # Output 0C Cmp TG_Output_0C_Cmp NET 'TG_Output_1A_Dir' U901-25 R917-1 C947-1 # Output 1A Dir NET 'TG_Output_1A_Cmp' U901-26 R918-1 C948-1 # Output 1A Cmp NET 'TG_Output_1B_Dir' U901-22 R919-1 C949-1 # Output 1B Dir NET 'TG_Output_1B_Cmp' U901-23 R920-1 C950-1 # Output 1B Cmp # # Connect the Timing Generator Outputs 1A and 1B to: AC Coupled # # Time Gen Output 1A to XCVR_1A_REF_CLK_IN L23, L24 JESD Clock # # Time Gen Output 1B to CCC_SE_CLK_IN_S_9 J14, H14 a Spare Clk # GPIO11PB1/CLKIN_S_9 Bank #1 # NET 'XCVR_1A_REF_CLK_IN_Dir' C947-2 U1-L23 # XCVR_1A_REF_CLK_IN_Dir JESD Clock NET 'XCVR_1A_REF_CLK_IN_Cmp' C948-2 U1-L24 # XCVR_1A_REF_CLK_IN_Cmp JESD Clock NET 'FPGA_CCC_SE_CLK_IN_S_9_Dir' C949-2 U1-J14 # Spare Clock Time Gen to FPGA Dir NET 'FPGA_CCC_SE_CLK_IN_S_9_Cmp' C950-2 U1-H14 # Spare Clock Time Gen to FPGA Cmp NET 'TIME_GEN_1V8' R911-2 R912-2 # Connect the NET 'TIME_GEN_1V8' R913-2 R914-2 # Output Pull-Up NET 'TIME_GEN_1V8' R915-2 R916-2 # Resistors to the NET 'TIME_GEN_1V8' R917-2 R918-2 # Timing_Generator NET 'TIME_GEN_1V8' R919-2 R920-2 # 1V8 Power Rail # # Rs and Cs for: Setup, Internal Supplies, and Loop Filters: # ---------------------------------------------------------- # NET 'Time_Gen_M4_Pull_Up' R901-1 U901-37 # Pull-Up the M4 pin NET 'Time_Gen_M5_Pull_Dn' R902-1 U901-1 # Pull-Down the M5 pin NET 'Time_Gen_M6_Pull_Dn' R903-1 U901-5 # Pull-Down the M6 pin NET 'TIME_GEN_3V3' R901-2 # Pull-Uo 3V3 Power NET 'GROUND' R902-2 R903-2 # Pull-Down Ground NET 'Time_Gen_LF_0' C932-1 U901-8 # 3.9 nFd Cap to LF_0 NET 'Time_Gen_LDO_0' C931-1 C932-2 U901-7 # Both Caps to LDO_0 NET 'GROUND' C931-2 # 220 nFd Cap to Ground NET 'Time_Gen_LF_1' C934-1 U901-29 # 3.9 nFd Cap to LF_1 NET 'Time_Gen_LDO_1' C933-1 C934-2 U901-30 # Both Caps to LDO_1 NET 'GROUND' C933-2 # 220 nFd Cap to Ground # # 1.8 Volt Power to the AD9546: # NET 'BULK_1V8' L901-2 # Bulk_1V8 Power to Filter NET 'TIME_GEN_1V8' L901-1 # Filtered Timing Gen 1V8 Power NET 'TIME_GEN_1V8' C901-1 C902-1 C903-1 C904-1 # 1V8 Bypass Caps NET 'GROUND' C901-2 C902-2 C903-2 C904-2 # Ground Side of Filter Caps NET 'TIME_GEN_1V8' C905-1 C906-1 C907-1 C908-1 # 1V8 Bypass Caps NET 'GROUND' C905-2 C906-2 C907-2 C908-2 # Ground Side of Filter Caps NET 'TIME_GEN_1V8' C909-1 C910-1 C911-1 C912-1 # 1V8 Bypass Caps NET 'GROUND' C909-2 C910-2 C911-2 C912-2 # Ground Side of Filter Caps NET 'TIME_GEN_1V8' C913-1 C914-1 C915-1 C916-1 # 1V8 Bypass Caps NET 'GROUND' C913-2 C914-2 C915-2 C916-2 # Ground Side of Filter Caps NET 'TIME_GEN_1V8' U901-6 U901-9 U901-20 U901-28 # 1V8 to the Timing Generator NET 'TIME_GEN_1V8' U901-31 U901-40 U901-41 U901-45 # 1V8 to the Timing Generator # # 1.8 Volt Power to the AD9546's Differential Output Drivers: # NET 'TIME_GEN_1V8' L903-1 L904-1 L905-1 # 1V8 power to Diff Output Inductors NET 'TIME_GEN_1V8' L906-1 L907-1 # 1V8 power to Diff Output Inductors NET 'Diff_Out_0A_Power' L903-2 U901-10 # 1V8 power to Diff Output 0A NET 'Diff_Out_0B_Power' L904-2 U901-13 # 1V8 power to Diff Output 0B NET 'Diff_Out_0C_Power' L905-2 U901-19 # 1V8 power to Diff Output 0C NET 'Diff_Out_1A_Power' L906-2 U901-27 # 1V8 power to Diff Output 1A NET 'Diff_Out_1B_Power' L907-2 U901-24 # 1V8 power to Diff Output 1B # # 3.3 Volt Power to the AD9546: # NET 'BULK_3V3' L902-2 # Bulk_3V3 Power to Filter NET 'TIME_GEN_3V3' L902-1 # Filtered Timing Gen 1V8 Power NET 'TIME_GEN_3V3' C921-1 C922-1 C923-1 C924-1 # 3V3 Bypass Caps NET 'GROUND' C921-2 C922-2 C923-2 C924-2 # Ground Side of Filter Caps NET 'TIME_GEN_3V3' C925-1 # 3V3 Bypass Caps NET 'GROUND' C925-2 # Ground Side of Filter Caps NET 'TIME_GEN_3V3' U901-3 U901-34 # 3V3 to the Timing Generator # # Grounds to the AD9546's Thermal Pad 25 ground connections: # NET 'GROUND' U901-51 U901-52 U901-53 U901-54 # Grounds to the AD9546 NET 'GROUND' U901-55 U901-56 U901-57 U901-58 # Grounds to the AD9546 NET 'GROUND' U901-59 U901-60 U901-61 U901-62 # Grounds to the AD9546 NET 'GROUND' U901-63 U901-64 U901-65 U901-66 # Grounds to the AD9546 NET 'GROUND' U901-67 U901-68 U901-69 U901-70 # Grounds to the AD9546 NET 'GROUND' U901-71 U901-72 U901-73 U901-74 # Grounds to the AD9546 NET 'GROUND' U901-75 # Grounds to the AD9546