# # USB Phy Nets and Connection to the DK's CPU # ----------------------------------------------- # # # Disco-Kraken Key In Net List # ------------------------------- # # # Initial Rev. 24-Nov-2022 # Current Rev. 5-Dec-2023 # # # This net list holds the USB Phy and Its Connection # to the DK's CPU and the USB Power nets. # # # The components for the USB Phy and Its Power and # connection to the DK's CPU are in the range 1051 to 1099. # # # USB Phy to/from DK CPU Connections this is the ULPI Interface: # ---------------------------------------------------------------------- # NET 'CPU_USB_CLK' U1-N2 R1051-2 # CPU USB_CLK to Term Resistor NET 'USB_PHY_CLK' U1051-1 R1051-1 # Phy USB_CLK from Term Resistor NET 'CPU_USB_DIR' U1-N3 R1052-2 # CPU USB_DIR to Term Resistor NET 'USB_PHY_DIR' U1051-31 R1052-1 # Phy USB_RIR from Term Resistor NET 'CPU_USB_NXT' U1-M4 R1053-2 # CPU USB_NXT to Term Resistor NET 'USB_PHY_NXT' U1051-2 R1053-1 # Phy USB_NXT from Term Resistor NET 'CPU_USB_STP' U1-M5 R1054-2 # CPU USB_STP to Term Resistor NET 'USB_PHY_STP' U1051-29 R1054-1 # Phy USB_STP from Term Resistor NET 'CPU_USB_DATA_0' U1-N1 R1055-2 # CPU USB_DATA_0 to Term Resistor NET 'USB_PHY_DATA_0' U1051-3 R1055-1 # Phy USB_DATA_0 from Term Resistor NET 'CPU_USB_DATA_1' U1-M1 R1056-2 # CPU USB_DATA_1 to Term Resistor NET 'USB_PHY_DATA_1' U1051-4 R1056-1 # Phy USB_DATA_1 from Term Resistor NET 'CPU_USB_DATA_2' U1-L3 R1057-2 # CPU USB_DATA_2 to Term Resistor NET 'USB_PHY_DATA_2' U1051-5 R1057-1 # Phy USB_DATA_2 from Term Resistor NET 'CPU_USB_DATA_3' U1-L4 R1058-2 # CPU USB_DATA_3 to Term Resistor NET 'USB_PHY_DATA_3' U1051-6 R1058-1 # Phy USB_DATA_3 from Term Resistor NET 'CPU_USB_DATA_4' U1-M2 R1059-2 # CPU USB_DATA_4 to Term Resistor NET 'USB_PHY_DATA_4' U1051-7 R1059-1 # Phy USB_DATA_4 from Term Resistor NET 'CPU_USB_DATA_5' U1-L2 R1060-2 # CPU USB_DATA_5 to Term Resistor NET 'USB_PHY_DATA_5' U1051-9 R1060-1 # Phy USB_DATA_5 from Term Resistor NET 'CPU_USB_DATA_6' U1-L5 R1061-2 # CPU USB_DATA_6 to Term Resistor NET 'USB_PHY_DATA_6' U1051-10 R1061-1 # Phy USB_DATA_6 from Term Resistor NET 'CPU_USB_DATA_7' U1-M6 R1062-2 # CPU USB_DATA_7 to Term Resistor NET 'USB_PHY_DATA_7' U1051-13 R1062-1 # Phy USB_DATA_7 from Term Resistor # # Reference Clock from a PLL in the FPGA to the USB Phy Reference Clock Input Pin: # ------------------------------------------------------------------------------------ NET 'FPGA_Ref_Clk_to_USB_Phy' R1063-2 # FPGA USB Phy Ref Clk to Series Term NET 'USB_PHY_Ref_Clk_Input' U1051-26 R1063-1 # Series Term to USB Phy Ref Clk Input # # USB RESET Signal: # ------------------- # NET 'USB_RESET_B' U1051-27 # USB_Reset_B signal to USB Phy chip NET 'USB_RESET_B' U1052-1 # USB_Reset_B signal to USB High Side Switch # # USB Phy Chip - No_Conn and Pad Pins: # -------------------------------------- # NET 'NO_CONN_USB_Pin_12' U1051-12 # USB No_Conn Pin 12 NC NET 'NO_CONN_USB_Pin_15' U1051-15 # USB No_Conn Pin 15 SPK_L NET 'NO_CONN_USB_Pin_16' U1051-16 # USB No_Conn Pin 16 SPK_R NET 'NO_CONN_USB_Pin_25' U1051-25 # USB No_Conn Pin 25 XO NET 'NO_CONN_USB_Pin_30' U1051-30 # USB No_Conn Pin 30 NC NET 'USB_PHY_CPEN_OUTPUT' U1051-17 TP1051-1 # USB Phy Pin 17 CPEN Output # routed to a Test Point Pad # # USB Phy Chip - Jumper Setup and Control Pins: # ----------------------------------------------- # # USB Phy Reference Frequency Select Jumpers NET 'USB_PHY_REF_SEL_0' U1051-8 # USB Phy Ref Select 0 Pin NET 'USB_PHY_REF_SEL_1' U1051-11 # USB Phy Ref Select 1 Pin NET 'USB_PHY_REF_SEL_2' U1051-14 # USB Phy Ref Select 2 Pin NET 'USB_PHY_REF_SEL_0' JMP1051-1 JMP1052-2 # USB Phy Reference Frequency Select 0 NET 'USB_PHY_REF_SEL_1' JMP1053-1 JMP1054-2 # USB Phy Reference Frequency Select 1 NET 'USB_PHY_REF_SEL_2' JMP1055-1 JMP1056-2 # USB Phy Reference Frequency Select 2 NET 'USB_PHY_3V3' JMP1051-2 JMP1053-2 JMP1055-2 # Pull-Up Source to Jumpers NET 'GROUND' JMP1052-1 JMP1054-1 JMP1056-1 # Ground Anchor to Jumpers # USB Phy ID Select Jumpers NET 'USB_PHY_ID_SEL' U1051-23 # USB Phy ID Pin NET 'USB_PHY_ID_SEL' JMP1057-1 JMP1058-2 # USB Phy ID Select Jumpers NET 'USB_PHY_3V3' JMP1057-2 # Pull-Up Source to Jumpers NET 'GROUND' JMP1058-1 # Ground Anchor to Jumpers # USB Phy VBUS Select Resistors NET 'USB_PHY_VBUS_SEL' U1051-22 # USB Phy VBUS Select Pin NET 'USB_PHY_VBUS_SEL' R1065-1 R1066-2 # USB Phy VBUS Select Resistors NET 'USB_PHY_3V3' R1065-2 # Pull-Up Source to Resistor NET 'GROUND' R1066-1 # Ground Anchor to Resistor # # USB Connector Pin Connections: # -------------------------------- # NET 'USB_Data_Dir' J15-3 # USB Data Direct NET 'USB_Data_Cmp' J15-2 # USB Data Complement NET 'USB_Switched_Pos_Power' J15-1 # USB Switched Positive Power NET 'GROUND' J15-4 # USB Power Return NET 'GROUND' J15-5 J15-6 # USB Connector Shield NET 'GROUND' J15-7 J15-8 # USB Connector Shield # # USB Phy Chip Data to/from USB Connector: # -------------------------------------------- # NET 'USB_Data_Dir' U1051-18 TVS1052-1 # USB Direct Data NET 'USB_Data_Cmp' U1051-19 TVS1051-1 # USB Complement Data NET 'GROUND' TVS1051-2 TVS1052-2 # Ground the ESD Suppressors # # USB High Side Switch Input Power & Control: # ---------------------------------------------- # NET 'BULK_5V0' F1051-1 # Bulk Power Fuse to High-Side Swch NET 'USB_HS_5V0' F1051-2 L1052-2 # Fused Power to High-Side Swch Filter NET 'USB_FLTR_5V0' C1057-1 L1052-1 U1052-7 # Filtered Power to High-Side Swch NET 'GROUND' C1057-2 # Gnd the Filter Bypass Cap for HS Swch NET 'GROUND' U1052-3 # Gnd of the USB High-Side Switch NET 'USB_HS_SWCH_FLAG' R1068-2 U1052-2 # USB High-Side Swch FLAG pin NET 'USB_FLTR_5V0' R1068-1 # Pull-Up Source for FLAG PU Resistor NET 'USB_HS_SWCH_ILIM' R1067-2 U1052-4 # USB HS Swch I_Limit Resistor NET 'GROUND' R1067-1 # Ground the I_Limit Resistor NET 'NO_CONN_USB_HS_SWCH_5' U1052-5 # No_Conn Pin 5 on the USB HS Swch # # USB High Side Switch Power to USB Connector: # ------------------------------------------------ # NET 'USB_SWITCHED_POS_POWER' U1052-6 U1052-8 # Switched USB Power to Connector NET 'USB_SWITCHED_POS_POWER' C1058-1 # Switched USB Power to Connector NET 'GROUND' C1058-2 # Ground the USB Conn Power Cap # # Internal PS and Bias Connections for the USB Phy Chip: # --------------------------------------------------------- # NET 'USB_PHY_Int_3V3' U1051-20 C1055-1 # Bypass USB Phy Internal 3V3 NET 'USB_PHY_Int_1V8' U1051-28 C1056-1 # Bypass USB Phy Internal 1V8 NET 'GROUND' C1055-2 C1056-2 # Ground Side of Bypass Caps NET 'USB_PHY_Int_BIAS' U1051-24 R1064-2 # USB Phy BIAS Set Resistor NET 'GROUND' R1064-1 # Ground Side of Bias Set Resistor # # 3.3 Volt Power and Grounds to USB Phy Chip: # ----------------------------------------------- # NET 'BULK_3V3' L1051-1 # Bulk_3V3 Power to Filter NET 'USB_PHY_3V3' L1051-2 # Filtered USB 3V3 Power NET 'USB_PHY_3V3' C1051-2 C1052-2 # 3V3 Bypass Caps NET 'GROUND' C1051-1 C1052-1 # Ground Side of Filter Caps NET 'USB_PHY_3V3' U1051-32 # 3V3 Power to the USB Phy Chip NET 'GROUND' U1051-33 U1051-34 U1051-35 # Grounds to the USB Phy Chip NET 'GROUND' U1051-36 U1051-37 U1051-38 # Grounds to the USB Phy Chip NET 'GROUND' U1051-39 U1051-40 U1051-41 # Grounds to the USB Phy Chip # # 5.0 Volt Power to USB Phy Chip: # ----------------------------------- # NET 'BULK_5V0' C1053-1 C1054-1 # 5V0 Bypass Caps NET 'GROUND' C1053-2 C1054-2 # Ground Side of Filter Caps NET 'BULK_5V0' U1051-21 # 5V0 Power to the USB Phy Chip # # List the NetNames of the Signals that must be # connected to FPGA Floating Pins. Here just list # the NetNames - the actual connections to these # FPGA Floating pins are made in the Nets File: # fpga_cpu_floating_connection_nets.txt # ---------------------------------------------------- # # # This is a 3V3 signal: Reference Clock to the USB Phy chip # ------------------------------------------------------------- # # # NET 'FPGA_Ref_Clk_to_USB_Phy' # FPGA USB Phy Ref Clk to Series Term # #