Bank 6 from Nathan's 15-Sept-2023 Pin Report 73 pins shown here ALERT_N V6 Yes MSS_DDR_ALERT_N Bank6 MSS_DDR_A[0] V1 Yes MSS_DDR_A0 Bank6 MSS_DDR_A[1] V2 Yes MSS_DDR_A1 Bank6 MSS_DDR_A[2] Y1 Yes MSS_DDR_A2 Bank6 MSS_DDR_A[3] W1 Yes MSS_DDR_A3 Bank6 MSS_DDR_A[4] W3 Yes MSS_DDR_A4 Bank6 MSS_DDR_A[5] W4 Yes MSS_DDR_A5 Bank6 MSS_DDR_A[6] W5 Yes MSS_DDR_A6 Bank6 MSS_DDR_A[7] Y6 Yes MSS_DDR_A7 Bank6 MSS_DDR_A[8] W6 Yes MSS_DDR_A8 Bank6 MSS_DDR_A[9] Y5 Yes MSS_DDR_A9 Bank6 MSS_DDR_A[10] V9 Yes MSS_DDR_A10 Bank6 MSS_DDR_A[11] U9 Yes MSS_DDR_A11 Bank6 MSS_DDR_A[12] V7 Yes MSS_DDR_A12 Bank6 MSS_DDR_A[13] V8 Yes MSS_DDR_A13 Bank6 MSS_DDR_ACT_N U5 Yes MSS_DDR_ACT_N Bank6 MSS_DDR_BA[0] U11 Yes MSS_DDR_BA0 Bank6 MSS_DDR_BA[1] W10 Yes MSS_DDR_BA1 Bank6 MSS_DDR_BG0 U2 Yes MSS_DDR_BG0 Bank6 MSS_DDR_CAS_N U7 Yes MSS_DDR_A15 Bank6 MSS_DDR_CK0 Y3 Yes MSS_DDR_CK0/DDR_PLL0_OUT0 Bank6 MSS_DDR_CK0_N Y2 Yes MSS_DDR_CK_N0 Bank6 MSS_DDR_CKE0 V4 Yes MSS_DDR_CKE0 Bank6 MSS_DDR_CS0_N T4 Yes MSS_DDR_CS0 Bank6 MSS_DDR_DM[0] AC3 Yes MSS_DDR_DM0 Bank6 MSS_DDR_DM[1] AC9 Yes MSS_DDR_DM1 Bank6 MSS_DDR_DM[2] AE1 Yes MSS_DDR_DM2 Bank6 MSS_DDR_DM[3] AH4 Yes MSS_DDR_DM3 Bank6 MSS_DDR_DQ[0] AB5 Yes MSS_DDR_DQ0 Bank6 MSS_DDR_DQ[1] AB4 Yes MSS_DDR_DQ1 Bank6 MSS_DDR_DQ[2] AA4 Yes MSS_DDR_DQ2 Bank6 MSS_DDR_DQ[3] AA3 Yes MSS_DDR_DQ3 Bank6 MSS_DDR_DQ[4] AA2 Yes MSS_DDR_DQ4 Bank6 MSS_DDR_DQ[5] AC4 Yes MSS_DDR_DQ5 Bank6 MSS_DDR_DQ[6] AC1 Yes MSS_DDR_DQ6 Bank6 MSS_DDR_DQ[7] AC2 Yes MSS_DDR_DQ7 Bank6 MSS_DDR_DQ[8] AB7 Yes MSS_DDR_DQ8 Bank6 MSS_DDR_DQ[9] AC6 Yes MSS_DDR_DQ9 Bank6 MSS_DDR_DQ[10] AC7 Yes MSS_DDR_DQ10 Bank6 MSS_DDR_DQ[11] AA5 Yes MSS_DDR_DQ11 Bank6 MSS_DDR_DQ[12] AB6 Yes MSS_DDR_DQ12 Bank6 MSS_DDR_DQ[13] AC8 Yes MSS_DDR_DQ13 Bank6 MSS_DDR_DQ[14] AA9 Yes MSS_DDR_DQ14 Bank6 MSS_DDR_DQ[15] AB9 Yes MSS_DDR_DQ15 Bank6 MSS_DDR_DQ[16] AD6 Yes MSS_DDR_DQ16 Bank6 MSS_DDR_DQ[17] AE5 Yes MSS_DDR_DQ17 Bank6 MSS_DDR_DQ[18] AD5 Yes MSS_DDR_DQ18 Bank6 MSS_DDR_DQ[19] AD4 Yes MSS_DDR_DQ19 Bank6 MSS_DDR_DQ[20] AF5 Yes MSS_DDR_DQ20 Bank6 MSS_DDR_DQ[21] AE6 Yes MSS_DDR_DQ21 Bank6 MSS_DDR_DQ[22] AE2 Yes MSS_DDR_DQ22 Bank6 MSS_DDR_DQ[23] AD1 Yes MSS_DDR_DQ23 Bank6 MSS_DDR_DQ[24] AF4 Yes MSS_DDR_DQ24 Bank6 MSS_DDR_DQ[25] AF3 Yes MSS_DDR_DQ25 Bank6 MSS_DDR_DQ[26] AF1 Yes MSS_DDR_DQ26 Bank6 MSS_DDR_DQ[27] AG1 Yes MSS_DDR_DQ27 Bank6 MSS_DDR_DQ[28] AH2 Yes MSS_DDR_DQ28 Bank6 MSS_DDR_DQ[29] AH3 Yes MSS_DDR_DQ29 Bank6 MSS_DDR_DQ[30] AG5 Yes MSS_DDR_DQ30 Bank6 MSS_DDR_DQ[31] AG4 Yes MSS_DDR_DQ31 Bank6 MSS_DDR_DQS[0] AB2 Yes MSS_DDR_DQS_P0 Bank6 MSS_DDR_DQS[1] AA7 Yes MSS_DDR_DQS_P1 Bank6 MSS_DDR_DQS[2] AD3 Yes MSS_DDR_DQS_P2 Bank6 MSS_DDR_DQS[3] AF2 Yes MSS_DDR_DQS_P3 Bank6 MSS_DDR_DQS_N[0] AB1 Yes MSS_DDR_DQS_N0 Bank6 MSS_DDR_DQS_N[1] AA8 Yes MSS_DDR_DQS_N1 Bank6 MSS_DDR_DQS_N[2] AE3 Yes MSS_DDR_DQS_N2 Bank6 MSS_DDR_DQS_N[3] AG2 Yes MSS_DDR_DQS_N3 Bank6 MSS_DDR_ODT0 V3 Yes MSS_DDR_ODT0 Bank6 MSS_DDR_PAR U6 Yes MSS_DDR_PARITY Bank6 MSS_DDR_RAS_N U10 Yes MSS_DDR_A16 Bank6 MSS_DDR_RESET_N U1 Yes MSS_DDR_RAM_RST_N/DDR_PLL0_OUT1 Bank6 MSS_DDR_WE_N T7 Yes MSS_DDR_A14 Bank6