---------------------------------------------------------------- -Pin Report - Date: Fri Sep 15 11:15:33 2023 Pinchecksum: NOT-AVAILABLE -Product: Designer -Release: v2023.1 -Version: 2023.1.0.6 -Design Name: DK_TOP -Family: PolarFireSoC -Die: MPFS250T -Package: FCVG784 ----------------------------------------------------------------- Port |Pin |Fixed |Function |Bank |I/O Std |Direction |Used I/O Reg |User I/O Lock Down |Clamp Diode |Resistor Pull |Use I/O Calibration from the lane |Schmitt Trigger |Vcm Input Range |On Die Termination |Odt Value (Ohm) |Input Delay |Slew |Output Drive (mA) |Impedance (ohm) |Output Load (pF) |Source Termination (Ohm) |Output Delay |MSS Resistor Pull |MSS Clamp Diode |MSS Persist |MSS User I/O Lock Down |MSS Odt (Ohm) |MSS Thevenin (Ohm) |MSS Schmitt Trigger |MSS Vcm Input Range |MSS Low Power Mode Input Receiver |MSS Low Power Mode Output Buffer |MSS Output Drive (mA) |MSS Source Termination (Ohm) | -------------------------|-----|------|--------------------------------------------------------|---------|----------|-------------|-------------------|-------------------|--------------|----------------------------------|----------------------------------|----------------|-------------------|-------------------|----------------|------------|------------------|------------------|-----------------|-------------------------|-------------------------|------------------|------------------|----------------|-----------------------|-----------------------|-------------------|--------------------|--------------------|----------------------------------|----------------------------------|---------------------------------|-----------------------------|-----------------------------| ADC_SYNC_N C28 Yes GPIO59NB9 Bank9 LVDS18G Output None No OFF None No --- --- --- 100 --- OFF 6 --- 5 OFF OFF ADC_SYNC_P B28 Yes GPIO59PB9/CLKIN_S_13/CCC_SE_CLKIN_S_13 Bank9 LVDS18G Output None No OFF None No --- --- --- 100 --- OFF 6 --- 5 OFF OFF ALERT_N V6 Yes MSS_DDR_ALERT_N Bank6 HSTL12I Input --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- --- --- FAB_DDR_A[0] AG28 Yes HSIO81NB0/DQS Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_A[1] Y22 Yes HSIO73NB0 Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_A[2] AC26 Yes HSIO66NB0 Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_A[3] Y23 Yes HSIO72NB0 Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_A[4] AE26 Yes HSIO78PB0/CLKIN_N_7 Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_A[5] AC27 Yes HSIO66PB0/CCC_NE_CLKIN_N_11 Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_A[6] AG27 Yes HSIO81PB0/DQS Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_A[7] AC22 Yes HSIO75NB0/DQS Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_A[8] Y21 Yes HSIO77PB0 Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_A[9] AC28 Yes HSIO67NB0 Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_A[10] AE25 Yes HSIO78NB0 Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_A[11] W21 Yes HSIO77NB0 Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_A[12] AA22 Yes HSIO76PB0 Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_A[13] AB22 Yes HSIO76NB0 Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_ACT_N AD25 Yes HSIO70NB0 Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_BA[0] AD24 Yes HSIO71PB0 Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_BA[1] AD28 Yes HSIO67PB0/CCC_NE_PLL0_OUT1 Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_BG AF24 Yes HSIO80PB0/CLKIN_N_6 Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_CAS_N AF28 Yes HSIO79NB0 Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_CK0 AB25 Yes HSIO68PB0/CCC_NE_CLKIN_N_10/CCC_NE_PLL0_OUT0 Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_CK0_N AB24 Yes HSIO68NB0 Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_CKE AG26 Yes HSIO83NB0 Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_CS_N AH27 Yes HSIO82NB0 Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_DM_N[0] AG22 Yes HSIO89PB0 Bank0 POD12I Output None No ON None No --- --- --- 60 --- OFF --- 40 5 --- OFF FAB_DDR_DM_N[1] AE18 Yes HSIO95PB0/CCC_NW_CLKIN_N_0 Bank0 POD12I Output None No ON None No --- --- --- 60 --- OFF --- 40 5 --- OFF FAB_DDR_DM_N[2] AA18 Yes HSIO101NB0 Bank0 POD12I Output None No ON None No --- --- --- 60 --- OFF --- 40 5 --- OFF FAB_DDR_DM_N[3] AC17 Yes HSIO107NB0 Bank0 POD12I Output None No ON None No --- --- --- 60 --- OFF --- 40 5 --- OFF FAB_DDR_DQ[0] AG24 Yes HSIO84NB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[1] AE23 Yes HSIO85NB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[2] AF23 Yes HSIO85PB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[3] AH23 Yes HSIO86NB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[4] AH22 Yes HSIO86PB0/CLKIN_N_4 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[5] AG21 Yes HSIO88NB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[6] AH21 Yes HSIO88PB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[7] AF22 Yes HSIO89NB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[8] AG20 Yes HSIO90NB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[9] AD19 Yes HSIO91NB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[10] AC19 Yes HSIO91PB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[11] AG19 Yes HSIO92NB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[12] AF19 Yes HSIO92PB0/CLKIN_N_2/CCC_NW_CLKIN_N_2 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[13] AH19 Yes HSIO94NB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[14] AH18 Yes HSIO94PB0/CCC_NW_CLKIN_N_1 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[15] AF18 Yes HSIO95NB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[16] AC21 Yes HSIO96NB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[17] AB21 Yes HSIO96PB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[18] Y20 Yes HSIO97NB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[19] W20 Yes HSIO97PB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[20] Y19 Yes HSIO98NB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[21] W19 Yes HSIO98PB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[22] AA19 Yes HSIO100NB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[23] AB19 Yes HSIO100PB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[24] AE16 Yes HSIO102NB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[25] AD16 Yes HSIO102PB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[26] AC18 Yes HSIO103NB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[27] AD18 Yes HSIO103PB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[28] AH17 Yes HSIO104NB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[29] AG17 Yes HSIO104PB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[30] AH16 Yes HSIO106NB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQ[31] AG16 Yes HSIO106PB0 Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQS[0] AE21 Yes HSIO87PB0/DQS Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQS[1] AE20 Yes HSIO93PB0/DQS Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQS[2] AB20 Yes HSIO99PB0/DQS Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQS[3] AE17 Yes HSIO105PB0/DQS Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQS_N[0] AE22 Yes HSIO87NB0/DQS Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQS_N[1] AD20 Yes HSIO93NB0/DQS Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQS_N[2] AA20 Yes HSIO99NB0/DQS Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_DQS_N[3] AF17 Yes HSIO105NB0/DQS Bank0 POD12I Inout None No ON None No OFF MID ON 60 --- OFF --- 40 5 --- --- FAB_DDR_ODT AH26 Yes HSIO82PB0 Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_PAR AC24 Yes HSIO71NB0 Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_RAS_N AF27 Yes HSIO79PB0 Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_RESET_N AD21 Yes HSIO75PB0/DQS/CCC_NE_PLL1_OUT0 Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_DDR_SHIELD0 AH24 Yes HSIO84PB0/CLKIN_N_5 Bank0 SHIELD12 Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- FAB_DDR_SHIELD1 AF20 Yes HSIO90PB0/CLKIN_N_3/CCC_NW_CLKIN_N_3 Bank0 SHIELD12 Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- FAB_DDR_SHIELD2 Y18 Yes HSIO101PB0 Bank0 SHIELD12 Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- FAB_DDR_SHIELD3 AC16 Yes HSIO107PB0 Bank0 SHIELD12 Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- FAB_DDR_TEN AA23 Yes HSIO72PB0/CLKIN_N_9/CCC_NE_CLKIN_N_9 Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- OFF FAB_DDR_WE_N AF25 Yes HSIO80NB0 Bank0 HSTL12I Output None No ON None No --- --- --- 50 --- OFF --- 50 5 --- --- FAB_REF_CLK_PAD_N N24 Fixed XCVR_0C_REFCLK_N --- FAB_REF_CLK_PAD_P N23 Fixed XCVR_0C_REFCLK_P --- FLASH_NOW_N A19 Yes GPIO45NB9 Bank9 LVDS18G Output None No OFF None No --- --- --- 100 --- OFF 6 --- 5 OFF OFF FLASH_NOW_P B19 Yes GPIO45PB9 Bank9 LVDS18G Output None No OFF None No --- --- --- 100 --- OFF 6 --- 5 OFF OFF HYDROPHONE_12_346MHz_CLK B16 Yes GPIO20NB9/DQS Bank9 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF HYDROPHONE_ADC_RESET_N C17 Yes GPIO23PB9 Bank9 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF HYDROPHONE_BCLK B15 Yes GPIO20PB9/DQS Bank9 LVCMOS18 Input None No ON Up No OFF --- OFF 120 OFF --- --- --- --- --- --- HYDROPHONE_FSYNC B17 Yes GPIO23NB9 Bank9 LVCMOS18 Input None No ON Up No OFF --- OFF 120 OFF --- --- --- --- --- --- HYDROPHONE_SDIN C16 Yes GPIO22NB9 Bank9 LVCMOS18 Input None No ON Up No OFF --- OFF 120 OFF --- --- --- --- --- --- INTERPOSER_CS_A0 D14 Yes GPIO8PB1/DQS Bank1 LVCMOS33 Output None No ON None No --- --- --- --- --- OFF 8 --- 5 --- OFF INTERPOSER_CS_A1 C14 Yes GPIO15PB1/CCC_SE_CLKIN_S_10 Bank1 LVCMOS33 Output None No ON None No --- --- --- --- --- OFF 8 --- 5 --- OFF INTERPOSER_CS_A2 B14 Yes GPIO15NB1 Bank1 LVCMOS33 Output None No ON None No --- --- --- --- --- OFF 8 --- 5 --- OFF JESD_REF_CLK_PAD_N L24 Fixed XCVR_1A_REFCLK_N --- JESD_REF_CLK_PAD_P L23 Fixed XCVR_1A_REFCLK_P --- LANE0_RXD_N F25 Fixed XCVR_1_RX0_N --- LANE0_RXD_P F26 Fixed XCVR_1_RX0_P --- LANE1_RXD_N H25 Fixed XCVR_1_RX1_N --- LANE1_RXD_P H26 Fixed XCVR_1_RX1_P --- LANE2_RXD_N K25 Fixed XCVR_1_RX2_N --- LANE2_RXD_P K26 Fixed XCVR_1_RX2_P --- LANE3_RXD_N N27 Fixed XCVR_1_RX3_N --- LANE3_RXD_P N28 Fixed XCVR_1_RX3_P --- MMUART_0_RXD_F2M E1 Yes GPIO170PB1/DQS/CCC_SW_PLL1_OUT0 Bank1 LVCMOS33 Input None No ON Up No OFF --- --- --- OFF --- --- --- --- --- --- MMUART_0_TXD_M2F D1 Yes GPIO170NB1/DQS Bank1 LVCMOS33 Output None No ON None No --- --- --- --- --- OFF 8 --- 5 --- OFF MMUART_1_RXD_F2M C1 Yes GPIO172PB1/CCC_SW_PLL1_OUT1 Bank1 LVCMOS33 Input None No ON Up No OFF --- --- --- OFF --- --- --- --- --- --- MMUART_1_TXD_M2F B1 Yes GPIO172NB1 Bank1 LVCMOS33 Output None No ON None No --- --- --- --- --- OFF 8 --- 5 --- OFF MMUART_2_RXD_F2M E2 Yes GPIO169NB1 Bank1 LVCMOS33 Input None No ON Up No OFF --- --- --- OFF --- --- --- --- --- --- MMUART_2_TXD_M2F E3 Yes GPIO169PB1/CCC_SW_CLKIN_S_1 Bank1 LVCMOS33 Output None No ON None No --- --- --- --- --- OFF 8 --- 5 --- OFF MMUART_3_RXD_F2M A14 Yes GPIO19PB9 Bank9 LVCMOS18 Input None No ON Up No OFF --- OFF 120 OFF --- --- --- --- --- --- MMUART_3_TXD_M2F A15 Yes GPIO19NB9 Bank9 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF MMUART_4_RXD_F2M A17 Yes GPIO43PB9 Bank9 LVCMOS18 Input None No ON Up No OFF --- OFF 120 OFF --- --- --- --- --- --- MMUART_4_TXD_M2F A18 Yes GPIO43NB9 Bank9 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF MSS_DDR_A[0] V1 Yes MSS_DDR_A0 Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 34 --- MSS_DDR_A[1] V2 Yes MSS_DDR_A1 Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 34 --- MSS_DDR_A[2] Y1 Yes MSS_DDR_A2 Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 34 --- MSS_DDR_A[3] W1 Yes MSS_DDR_A3 Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 34 --- MSS_DDR_A[4] W3 Yes MSS_DDR_A4 Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 34 --- MSS_DDR_A[5] W4 Yes MSS_DDR_A5 Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 34 --- MSS_DDR_A[6] W5 Yes MSS_DDR_A6 Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 34 --- MSS_DDR_A[7] Y6 Yes MSS_DDR_A7 Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 34 --- MSS_DDR_A[8] W6 Yes MSS_DDR_A8 Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 34 --- MSS_DDR_A[9] Y5 Yes MSS_DDR_A9 Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 34 --- MSS_DDR_A[10] V9 Yes MSS_DDR_A10 Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 34 --- MSS_DDR_A[11] U9 Yes MSS_DDR_A11 Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 34 --- MSS_DDR_A[12] V7 Yes MSS_DDR_A12 Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 34 --- MSS_DDR_A[13] V8 Yes MSS_DDR_A13 Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 34 --- MSS_DDR_ACT_N U5 Yes MSS_DDR_ACT_N Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 34 --- MSS_DDR_BA[0] U11 Yes MSS_DDR_BA0 Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 34 --- MSS_DDR_BA[1] W10 Yes MSS_DDR_BA1 Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 34 --- MSS_DDR_BG0 U2 Yes MSS_DDR_BG0 Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 34 --- MSS_DDR_CAS_N U7 Yes MSS_DDR_A15 Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 34 --- MSS_DDR_CK0 Y3 Yes MSS_DDR_CK0/DDR_PLL0_OUT0 Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 48 --- MSS_DDR_CK0_N Y2 Yes MSS_DDR_CK_N0 Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 48 --- MSS_DDR_CKE0 V4 Yes MSS_DDR_CKE0 Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 34 --- MSS_DDR_CS0_N T4 Yes MSS_DDR_CS0 Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 34 --- MSS_DDR_DM[0] AC3 Yes MSS_DDR_DM0 Bank6 POD12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 48 --- MSS_DDR_DM[1] AC9 Yes MSS_DDR_DM1 Bank6 POD12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 48 --- MSS_DDR_DM[2] AE1 Yes MSS_DDR_DM2 Bank6 POD12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 48 --- MSS_DDR_DM[3] AH4 Yes MSS_DDR_DM3 Bank6 POD12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 48 --- MSS_DDR_DQ[0] AB5 Yes MSS_DDR_DQ0 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[1] AB4 Yes MSS_DDR_DQ1 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[2] AA4 Yes MSS_DDR_DQ2 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[3] AA3 Yes MSS_DDR_DQ3 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[4] AA2 Yes MSS_DDR_DQ4 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[5] AC4 Yes MSS_DDR_DQ5 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[6] AC1 Yes MSS_DDR_DQ6 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[7] AC2 Yes MSS_DDR_DQ7 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[8] AB7 Yes MSS_DDR_DQ8 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[9] AC6 Yes MSS_DDR_DQ9 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[10] AC7 Yes MSS_DDR_DQ10 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[11] AA5 Yes MSS_DDR_DQ11 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[12] AB6 Yes MSS_DDR_DQ12 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[13] AC8 Yes MSS_DDR_DQ13 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[14] AA9 Yes MSS_DDR_DQ14 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[15] AB9 Yes MSS_DDR_DQ15 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[16] AD6 Yes MSS_DDR_DQ16 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[17] AE5 Yes MSS_DDR_DQ17 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[18] AD5 Yes MSS_DDR_DQ18 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[19] AD4 Yes MSS_DDR_DQ19 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[20] AF5 Yes MSS_DDR_DQ20 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[21] AE6 Yes MSS_DDR_DQ21 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[22] AE2 Yes MSS_DDR_DQ22 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[23] AD1 Yes MSS_DDR_DQ23 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[24] AF4 Yes MSS_DDR_DQ24 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[25] AF3 Yes MSS_DDR_DQ25 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[26] AF1 Yes MSS_DDR_DQ26 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[27] AG1 Yes MSS_DDR_DQ27 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[28] AH2 Yes MSS_DDR_DQ28 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[29] AH3 Yes MSS_DDR_DQ29 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[30] AG5 Yes MSS_DDR_DQ30 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQ[31] AG4 Yes MSS_DDR_DQ31 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQS[0] AB2 Yes MSS_DDR_DQS_P0 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQS[1] AA7 Yes MSS_DDR_DQS_P1 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQS[2] AD3 Yes MSS_DDR_DQS_P2 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQS[3] AF2 Yes MSS_DDR_DQS_P3 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQS_N[0] AB1 Yes MSS_DDR_DQS_N0 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQS_N[1] AA8 Yes MSS_DDR_DQS_N1 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQS_N[2] AE3 Yes MSS_DDR_DQS_N2 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_DQS_N[3] AG2 Yes MSS_DDR_DQS_N3 Bank6 POD12I Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 120 --- --- --- --- --- 48 --- MSS_DDR_ODT0 V3 Yes MSS_DDR_ODT0 Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 34 --- MSS_DDR_PAR U6 Yes MSS_DDR_PARITY Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 34 --- MSS_DDR_RAS_N U10 Yes MSS_DDR_A16 Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 34 --- MSS_DDR_RESET_N U1 Yes MSS_DDR_RAM_RST_N/DDR_PLL0_OUT1 Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 34 --- MSS_DDR_WE_N T7 Yes MSS_DDR_A14 Bank6 HSTL12I Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF --- --- --- --- --- --- 34 --- PPX_N A20 Yes GPIO47NB9 Bank9 SSTL18I Input None No ON None No OFF MID ON 50 OFF --- --- --- --- --- --- PPX_P B20 Yes GPIO47PB9 Bank9 SSTL18I Input None No ON None No OFF MID ON 50 OFF --- --- --- --- --- --- REFCLK P11 Yes MSS_REFCLK_IN_P Bank5 LVDS25 Input --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 100 --- --- --- --- --- --- --- REFCLK_N R11 Yes MSS_REFCLK_IN_N Bank5 LVDS25 Input --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- OFF 100 --- --- --- --- --- --- --- SENSOR_SCL B21 Yes GPIO49PB9 Bank9 LVCMOS18 Inout None No ON Up No OFF --- OFF 120 OFF OFF 8 --- 5 --- OFF SENSOR_SDA B22 Yes GPIO52PB9 Bank9 LVCMOS18 Inout None No ON Up No OFF --- OFF 120 OFF OFF 8 --- 5 --- OFF SFP1_RXD_N T25 Fixed XCVR_0_RX1_N --- SFP1_RXD_P T26 Fixed XCVR_0_RX1_P --- SFP1_TXD_N U27 Fixed XCVR_0_TX1_N --- SFP1_TXD_P U28 Fixed XCVR_0_TX1_P --- SMUT_TRIGGER[0] D10 Yes GPIO0NB1 Bank1 LVCMOS33 Input None No ON Up No OFF --- --- --- OFF --- --- --- --- --- --- SMUT_TRIGGER[1] E10 Yes GPIO12NB1 Bank1 LVCMOS33 Input None No ON Up No OFF --- --- --- OFF --- --- --- --- --- --- SMUT_TRIGGER[2] F10 Yes GPIO183NB1 Bank1 LVCMOS33 Input None No ON Up No OFF --- --- --- OFF --- --- --- --- --- --- SMUT_TRIGGER[3] G10 Yes GPIO183PB1 Bank1 LVCMOS33 Input None No ON Up No OFF --- --- --- OFF --- --- --- --- --- --- SPI_ADC_CSB A27 Yes GPIO57PB9/CLKIN_S_12/CCC_SE_CLKIN_S_12/CCC_SE_PLL0_OUT0 Bank9 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF SPI_ADC_SCLK C27 Yes GPIO56PB9/DQS/CCC_SE_PLL0_OUT0 Bank9 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF SPI_ADC_SDIO C26 Yes GPIO56NB9/DQS Bank9 LVCMOS18 Inout None No ON Up No OFF --- OFF 120 OFF OFF 8 --- 5 --- OFF SPI_ENET_CLK E15 Yes GPIO18PB9 Bank9 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF SPI_ENET_DI E16 Yes GPIO21NB9 Bank9 LVCMOS18 Input None No ON Up No OFF --- OFF 120 OFF --- --- --- --- --- --- SPI_ENET_DO D16 Yes GPIO22PB9 Bank9 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF SPI_ENET_SS D15 Yes GPIO18NB9 Bank9 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF SPI_INTERPOSER_CLK M10 Yes MSSIO30B2 Bank2 LVCMOS33 Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Down OFF OFF OFF --- --- OFF --- OFF OFF 8 --- SPI_INTERPOSER_DI M9 Yes MSSIO33B2 Bank2 LVCMOS33 Input --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Up OFF OFF OFF --- --- OFF --- OFF --- --- --- SPI_INTERPOSER_DO L10 Yes MSSIO32B2 Bank2 LVCMOS33 Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Up OFF OFF OFF --- --- --- --- --- OFF 8 --- SPI_INTERPOSER_SS_A N9 Yes MSSIO31B2 Bank2 LVCMOS33 Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Up OFF OFF OFF --- --- OFF --- OFF OFF 8 --- SPI_INTERPOSER_SS_B G9 Yes GPIO180PB1 Bank1 LVCMOS33 Output None No ON None No --- --- --- --- --- OFF 8 --- 5 --- OFF TIMING_SCL A9 Yes GPIO3NB1 Bank1 LVCMOS33 Inout None No ON Up No OFF --- --- --- OFF OFF 8 --- 5 --- OFF TIMING_SDA A10 Yes GPIO5NB1 Bank1 LVCMOS33 Inout None No ON Up No OFF --- --- --- OFF OFF 8 --- 5 --- OFF USB_CLK N2 Yes MSSIO14B2 Bank2 LVCMOS33 Input --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Up OFF OFF OFF --- --- OFF --- OFF --- --- --- USB_DATA0 N1 Yes MSSIO18B2 Bank2 LVCMOS33 Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Up OFF OFF OFF --- --- OFF --- OFF OFF 8 --- USB_DATA1 M1 Yes MSSIO19B2 Bank2 LVCMOS33 Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Up OFF OFF OFF --- --- OFF --- OFF OFF 8 --- USB_DATA2 L3 Yes MSSIO20B2 Bank2 LVCMOS33 Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Up OFF OFF OFF --- --- OFF --- OFF OFF 8 --- USB_DATA3 L4 Yes MSSIO21B2 Bank2 LVCMOS33 Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Up OFF OFF OFF --- --- OFF --- OFF OFF 8 --- USB_DATA4 M2 Yes MSSIO22B2 Bank2 LVCMOS33 Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Up OFF OFF OFF --- --- OFF --- OFF OFF 8 --- USB_DATA5 L2 Yes MSSIO23B2 Bank2 LVCMOS33 Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Up OFF OFF OFF --- --- OFF --- OFF OFF 8 --- USB_DATA6 L5 Yes MSSIO24B2 Bank2 LVCMOS33 Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Up OFF OFF OFF --- --- OFF --- OFF OFF 8 --- USB_DATA7 M6 Yes MSSIO25B2 Bank2 LVCMOS33 Inout --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Up OFF OFF OFF --- --- OFF --- OFF OFF 8 --- USB_DIR N3 Yes MSSIO15B2 Bank2 LVCMOS33 Input --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Up OFF OFF OFF --- --- OFF --- OFF --- --- --- USB_NXT M4 Yes MSSIO16B2 Bank2 LVCMOS33 Input --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Up OFF OFF OFF --- --- OFF --- OFF --- --- --- USB_STP M5 Yes MSSIO17B2 Bank2 LVCMOS33 Output --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Up OFF OFF OFF --- --- --- --- --- OFF 8 ---