Date: Fri, 20 Oct 2023 20:51:34 +0000 From: Adam Maunder To: Dan Edmunds Cc: Nathan Whitehorn Subject: Re: mainboard-interposer interface Parts/Attachments: 1 OK ~330 lines Text 2 Shown ~473 lines Text ---------------------------------------- [ The following HTML text may contain deceptive links. Carefully ] [ note the destination URL before visiting any links. ] Hello, I've published a draft of the interface for you're review. I'm available anytime to discuss. https://p-one.atlassian.net/wiki/spaces/PONE/pages/460029953/Interface+Cont rol+Document+-+Mainboard+Interposer [urldefense.com] I did change the order of the pins, moving the SPI signals to one side interleaving with GND signals. as it appear to allow for an easier layout. One thing that might be important would be defining signal levels and the terminations on either side, which I didn't include. For the piezo signal I believe it will definitely be a differential signal now. The UART looks like it is expected to be 57600 baud. For the fidelity of the Flash_Seen signal, there are several propagation delays/uncertainty in the signal (it is coming from the SiPM signal), so I'm not sure what sort of uncertainty can be expected from the raw signal compared to the uncertainty with the fidelity. Adam From Adam's drawing from 20-Oct-2023: 87833-4020 1 1V8 2 1V8 3 3V3 4 3V3 5 Gnd 6 Gnd 7 FLASH_Pulse_p 8 FLASH_Pulse_n 9 Gnd 10 Gnd 11 PIEZO_p 12 PIEZO_n 13 Gnd 14 Gnd 15 FLASH_TDC 16 Gnd 17 Gnd 18 SPI_CLK 19 CTRL_RST 20 SPI_MISO 21 Gnd 22 SPI_MOSI 23 A0 24 SPI_CS 25 Gnd 26 Gnd 27 A2 28 A1 29 Gnd 30 Gnd 31 UART_Tx 32 UART-Rx 33 SMUT_S1 34 Gnd 35 SMUT_S2 36 SMUT_S3 37 SMUT_S4 38 Gnd 39 5V0 40 5V0