Special Layer Usage on Disco-Kraken -------------------------------------- Original Rev. - -2023 Current Rev. 9-Oct-2024 This file holds the details about the "special" use of some logical layers in the design of the DK circuit board. There are other text files with details about other aspects of the DK pcb design - trace widths and such. Special Uses of Mentor Logical Layers: -------------------------------------- In the Disco-Kraken design I have made special use of a number of Mentor Logical Layers. Review the special use of layers in the DK design: Ground Plane Cuts in Top layers PrePreg_1 Ground Plane Cuts in Bot layres PrePreg_2 Ground Plane Cuts in All layers PrePreg_3 Vias Plugged from the Top PrePreg_5 Vias Plugged from the Bottom PrePreg_6 Backside metal on Bot side L12 e.g. QFN center pad Sheet_Dielectric_1 Backside metal on Top side L1 e.g. QFN center pad Sheet_Dielectric_2 Special Drawing that is used as a guide, e.g. Sheet_Dielectric_9 340 mm outer circle limit, USB and optical cables and plugs, bank boarders in FPGA and memory chips, ... Power Fill Shapes - in addition to the Shape_Edit layer: Fills on L4 Signal_3 are shown on DIELECTRIC_3 Fills on L6 Signal_11 are shown on DIELECTRIC_1 Fills on L7 Signal_12 are shown on DIELECTRIC_2 Fills on L1 Signal_1 are shown on DIELECTRIC_4 Fills on L12 Signal_10 are shown on DIELECTRIC_5 Recall that Sheet_Dielectric_1 is being used for the backside metal of components that are placed on the Top side of the card. This is metal on side 2. Sheet_Dielectric_2 is being used for the backside metal of components that are placed on the Bottom side of the card. This is metal on side 1. PrePreg_5 marks the vias that are plugged from the Top PrePreg_6 marks the vias that are plugged from the Bottom. The Geometries that have backside metal or plugs include: the QFN packages, the BGA packages (dog-bone vias), The Ground Plane cutouts are implemented as patterns on there of the PREPREG layers and two other special use layers: - PREPREG_1 cuts out the Ground Plane near the top side of the PCB but allows it to close on the bottom side. Thus for example PREPREG_1 is used in DC Blocking caps that are placed on the top side of the PCB. - PREPREG_2 cuts out the Ground Plane near the bottom side of the PCB but allows it to close on the top side. Thus for example PREPREG_2 is be used in DC Blocking caps that are placed on the bottom side of the PCB. - PREPREG_3 cuts out the Ground Plane on all PCB Ground Plane layers. Thus for example PREPREG_3 is used for ground relief around a high speed differential pair that goes the whole way through the PCB. Via Plugs are implemented in two of the PREPREG Layers: - PREPREG_5 marks the vias that are to be Plugged from the Top side of the card. - PREPREG_6 marks the vias that are to be Plugged from the Bottom side of the card. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Backside Metal for the: QFN, Switch, and PVA Components: --------------------------------------------------------- In the Hub design I want metal on the backside of such things as the center thermal/ground pad of the QFN and Switch components and for the Power Via Arrays. Note that "backside" typically means "side 2" aka the "solder" side - but note that the QFN-16 for the OnSemi Fanout chips is placed on both sides of the card. Using Breaout_1 for the front-side copper works well. But the Breakout layers follow the Top/Bottom Layer Mapping Rules so they can not be used for copper on the opposite side from where the component is placed. This all makes good rational sense but I do not know the official way that Mentor wants me to place backside metal. For a side 1 component I can not just use Signal_10 in its geometry for backside metal as this will cause a placement clearance error where for example I overlap the backside PVA metal with the associated component pin. So I have given up trying to figure out how to officially do this and I'm just going to do something unofficial but easy to understand and rational. In the Geometries for the: QFNs, Switch, and PVAs I'm placing the backside metal by: - Components instanced on Side 1 have their backside metal on Side 2 and in their geometry this metal is described on layer Sheet-Dielectric_1. - Components instanced on Side 2 have their backside metal on Side 1 and in their geometry this metal is described on layer Sheet-Dielectric_2. Note that this does not violate the Mentor Top/Bottom Layer Mapping Rules. The specific Sheet_Dielectric layer used matches the side on which the component is instanced. In generating the Gerber Plots the ArtWork Order file needs to: - Include Sheet-Dielectric_2 in the Top side (side 1) plot. - Include Sheet-Dielectric_1 in the Bottom side (side 2) plot. Note that this is strange, i.e. I'm using a specific layer 2 during the generation of a side 1 plot. But this does not violate any rules. Note that this only works because the generic and specific Sheet_Dielectric layeres are not being used for anything else in the Hub design so that they are empty except for my use of them for the backside metal in the QFN, Switch, and PVA components. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=