Drawing Number Indices for the DK Board ------------------------------------------ Original Rev. 9-Jan-2024 Current Rev. 28-Jan-2024 Drawings that are NOT part of the Current DK Board design: -------------------===--------------=======----------------- 8 Reset Circuits page 1 - replaced by 55 11 DK Board Test Power Supply - this is a different project 15 FPGA Clks to External Consumers - replaced by 54 19 TOMCat Power Feed - is this still part of DK ??? 20 Copper ENet dual PHYs - no longer part of DK 21 Copper ENet dual PHYs - no longer part of DK 24 Timing Singnal In/Out - replaced by 50 27 TDC TDC7200 - no longer part of DK 28 SPI Buses - replaced by 48 29 SPI Buses - replaced by 49 30 Cable Timing Switch Yard - no longer part of DK 31 Reset Circuits page 2 - replaced by 56 32 Copper Cable Terminations - no longer part of DK 33 SPI connections to Interposers - replaced by 51 34 Other connections to Interposers - replaced by 52 35 Switch Yard I2C Expander - no longer part of DK 40 Block Diagram - replaced by 46 41 Connections to the TOMCat - is this still part of DK ??? 57 Optical Clock Distribution Board - this is a different project 58 Optical Timing Fanout Basics - this is a different project DK Drawings that are Officially part of the Current DK Design: ---------------------==========-------------=======-==----- 1 DK Board Power Supplies 2 Input Power to 5V Converter 3 DC/DC Converters 4 Startup Supervisor 5 All Power OK Supervisor 6 DDR4 Reference Terminator Supply 7 Always ON CNST 3V3 supply 8 - 9 Power Bus Turn On Ramp Up 10 PMT to ADC Analog Input Circuits 11 - 12 Boot Memory FPGA Bank #3 13 JTAG to FPGA/CPU 14 Quarts Oscillators on DK Board 15 - 16 PMT ADC - Clocks, Control, & Outut Links 17 FPGA/CPU Bank #2 to USB Phy 18 USB Phy to USB Connector 19 - 20 - 21 - 22 PMY ADC Power and Grounds 23 Timing Generator - Control, Power, and Grounds 24 - 25 FPGA/CPU Pin Diagram - overall 26 DK Board Size and Connector Locations 27 - 28 - 29 - 30 - 31 - 32 - 33 - 34 - 35 - 36 Environmental Sensors 37 BB Audio ADC 38 FPGA DDR4 Memory 39 CPU DDR4 Memory 40 - 41 - 42 SFP Timing Module Connections 43 Barnacle Connections 44 Emergency Rescue RS-485 page 1 45 FPGA/CPU Power Bus Connections 46 Block Diagram of the DK Board 47 Emergency Rescue RS-485 page 3 48 SPI Buses on the DK 49 I2C Buses on the DK 50 Timing Generator In/Out Signals 51 SPI Connections to the Interposers 52 Other Connections to the Interposers 53 High-Speed Serial Transceiver Connections 54 FPGA Clocks to External Consumers 55 Startup & Reset Circuits page 1 56 Startup & Reset Circuits page 2 57 - 58 - 59 CPU Boot Memory - CPU QSPI Port 60 UARTs DK FPGA/CPU and DK Emergency Rescue 61 FPGA/CPU Pin Diagram - divided into Banks 62 Photo-Diode Analog Input to PMT ADC 63 DK Board - Floor Plan 64 Clocks on the DK Board 65 DK Board Mounting Holes 66 SFP Ethernet Module Connections 67 Emergency Rescue RS-485 Simplifier 68 Emergency Rescue RS-485 page 2 69 Interposer Connectors Pin Numbering and Function 70 Timing Generator In/Out Signals Simplified aka 50-Simplified 71 Main Cable J1 and Access Connectors J6 & J12