Net List Files  that Include a Connection to the FPGA/CPU
    -----------------------------------------------------------



                                              Initial Rev.   4-Dec-2023
                                              Current Rev.  26-Dec-2023


For the purpose of the DK design there are 2 kinds of pin
connections to the FPGA/CPU:

  - Connections to dedicated fixed location pins,  e.g.
    power pins,  DDR4 memory pins,  High-Speed Serial
    Link pins,  Clock pins,  Bank #3 pins, ...

  - Connections to "Floating" pins,  i.e. general purpose
    Bank I/O type signals that are only assigned to a
    specific pin by our FPGA design.


Most of the Floating pin connections involve connections
to the CPU's Peripheral devices  or  connections to
normal FPGA Bank I/O signals.


This document contains two list of Net List file names:

  - Names of the Net List files that include FPGA nets
    that connect to a dedicated fixed pin on the FPGA/CPU.

  - Names of the Net List files that include FPGA nets
    that connect to a "Floating" I/O Bank pin and need
    to be assigned to a specific pin in our FPGA design.


The FPGA/CPU  Floating  pin assignments are handled in
two steps:

  - The Net List file for a DK board function that
    included a connection to a Floating pin specifically
    mentions that connection to the FPGA/CPU  but  does
    not actually make the connection - rather

  - All Floating pin connections to the FPGA/CPU are
    made in the file:  fpga_cpu_floating_connection_nets.txt


That is, the file   fpga_cpu_floating_connection_nets.txt
is "one stop shopping" for all of the FPGA/CPU pin assignments
that must be coordinated between the DK's PCB design  and the
DK's FPGA/CPU design.


Net List File Names with connections
to  Dedicated Fixed  FPGA/CPU Pins:
---=================----------------

  boot_memory__cpu_nets.txt
  boot_memory_fpga_nets.txt
  crystal_oscillator_nets.txt
  ddr4_cpu_bank_6_address_and_command_nets.txt
  ddr4_cpu_bank_6_data_path_nets.txt
  ddr4_cpu_bank_6_no_connection_nets.txt
  ddr4_fpga_bank_0_address_and_command_nets.txt
  ddr4_fpga_bank_0_data_path_nets.txt
  ddr4_fpga_bank_0_no_connection_nets.txt
  fpga_power_and_ground_pins.txt
  jtag_for_fpga_cpu_nets.txt
  pmt_adc_serial_link_to_fpga_nets.txt
  sfp_cage_conn_pin_nets.txt
  timing_generator_nets.txt
  usb_phy_nets.txt



Net List File Names with references to
connections to  Floating  FPGA/CPU Pins:
---------------==========---------------

  access_conn_and_misc_uarts_nets.txt
  barnacle_interface_nets.txt
  bb_audio_adc_nets.txt
  environment_sensor_nets.txt
  interposer_all_other_nets.txt
  interposer_all_spi_nets.txt
  pmt_adc_sundry_nets.txt
  sfp_cage_conn_pin_nets.txt
  startup_and_reset_nets.txt
  usb_phy_nets.txt


Recall that all actual connections to  "Floating"
pins on the FPGA/CPU are made in the net list file:

  fpga_cpu_floating_connection_nets.txt