Krakow DK Talk on 9-May-2023
     -----------------------------


Overview of the Main Board aka the Disco Kraken Design:
-------------------------------------------------------

1. Show the drawing of the card:

     Physical size constraints
     As being designed the card is 235 mm square ... bla bla
     Location of connectors
     Required holes in mounting plate for cables
     Plugging in of connectors during final assembly


2. Goals and Concerns about the Design

     Would like Rev A to be as close to the final design
     as possible:

        Minimize any changes  (i.e. minimize risk)  when
        going from prototype build  to production build

        Minimize any differences in Physics performance or
        analysis between prototype and production cards

     Cost control:  We need 1400 of these cards so don't
     use unnecessary fancy expensive technology just for
     fun, control the pcb layer count, avoid unnecessary
     manufacturing steps were possible, e.g. back drilling

     Manufacturing yield:  Use conservative design rules
     where ever possible, follow IPC guidelines, visit
     assembly house to understand their concerns

     Reliability and Lifetime:  Study and follow the guidelines
     for reliable long life electronics and use common sense
     about component selection, e.g. no aluminum electrolytic caps

     Low Power:  This has not been a common concern for our
     previous designs - must pay attention to this

     Module Final Assembly and Testing:  The DK board must
     facilitate final assembly and testing

     Noise in the PMT signals or in their ADC:  We need the
     full 12 bit and 5 nsec resolution to do the Physics,
     focus on controlling noise in this important analog channel

     Too Many Sole Source Parts:  This situation is
     exacerbated by the manufacturing schedule being spread
     over years, an issue for management attention 



List of Hardware Functions on the DK:
(nothing about the DK's SW or FW functions)
-------------------------------------------

1. Power Supply Section - 100 V DC Input Power to:

      5V0, 3V3, 2V5, 1V8, 1V2, 1V05, 1V0_CORE, 1V0_ADC, 0V6

      5V0, 3V3, 1V8 are supplied to external loads:
      Interposer and TOMCat

      Power supply startup includes controlled ramp rate
      to meet the requirements of FPGA/CPU and all other ICs

      Power supply startup includes control of the Reset
      signals to:
      FPGA/CPU, PMT ADC, Clock Generator, Ethernet, Bluetooth

      The power supply section provides control of the
      Power Feed to:
      TOMCat, Bluetooth, Ethernet, Inductive Power Coupling,
      and some sections of the Clock Generator


2. FPGA/CPU  with

     4 GBytes of memory for the FPGA Fabric:  used for the
       circular buffer for PMT ADC data

     4 GBytes of memory for the CPU:  used for programs and data

     Power up Boot Configuration non-volatile memories:
     for the FPGA and for the CPU Linux


3. PMT ADC for the 16 PMT signals that provides  12 bit
   resolution and a conversion once every 5 nsec

4. Support for TOMCat which provides the 125 MHz and 1 Hz
   Time Base and Ethernet Communication to the DK board

5. Clock Generation:  clocks for the PMT ADC and for the
   Flash Now based are on TOMCat reference,  and other clocks
   for the: FPGA, CPU, USB, Bluetooth, TDC, Ethernet, Audio ADC

6. Ethernet communication from CPU via TOMCat to shore

7. Ethernet communication from CPU up/down main cable
   to adjacent modules

8. Timing Signals up/down main cable to adjacent modules

9. Interposer Connections and Device Support:

     Power for the Interposer
     SPI and UART Communication with 3 Address Lines
     Hydrophone signal from Interposer to Audio ADC
     4x Muon signals from Interposer to FPGA I/O
     Flash Now timing signal to the Interposer
     Light or Current Seen signal from Interposer to TDC


10. Module Accelerometer and Magnetometer

11. USB connection for a camera

12. Bluetooth and Inductive Power Coupling for External Sensors

13. Support for the Emergency Rescue RS-485 connection

14. Access Connectors:  For Initial Testing and then
    used during Production Testing

      Connector for JTAG for FPGA/CPU
      Connector for Power Supply Voltage and Current tests
      Connector for Access Signals: clocks, FPGA I/O


Milestones and Schedule:
------------------------

   no idea what to say

   Just give a list of proposed milestones and say
   that we are working on making a schedule for them ?