The 0402 & 0603 1% +-100 ppm/deg C are Panisonic ERJ-2RKF____X for 0402 size ERJ-3EKF____V for 0603 size The 0603 & 0805 0.1% +-25 ppm/deg C are Panisonic ERA-3AEB____V for 0603 size ERA-6AEB____V for 0805 size The 0805 0.1% +-25 ppm/deg C resistors are: 976 2.15k 4.32k 11.0k 15.4k 18.2k The 0603 0.1% +-25 ppm/deg C resistors are: 4.99k 8.06k 10.0k 12.0k 37.4k 45.3k 62.8k 100.0k $view_area([[-11, -32, "E$artwork_2_top_side.sim"], [14.1, -66.9, "E$artwork_2_top_side.sim"]]); $view_area([[-4.7, -34, "E$artwork_2_top_side.sim"], [2, -43.8, "E$artwork_2_top_side.sim"]]); $$close_window(void); $set_active_window("BO$disco_0_pcb"); $create_artwork_data("Gerber_274X", @ascii, [], @all, @noteardrops, @nopins, @novias, @notjunctions, 1.1, 1.1, @none, @board, @nopins_remove, @novias_remove, "", @flash_unplated, @noremove_partial_hatch, @noresize, 0, @noscale, 1, @triangle, 0, void); // Warning: Pin Padstack (SFP_1MM20) is Not defined on (BOARD_OUTLINE) (from: Idea/Util/Get Term Size 06) // Warning: Pin Padstack (SFP_1MM10) is Not defined on (BOARD_OUTLINE) (from: Idea/Util/Get Term Size 06) // ============================ Save Design All without changing anything except what layers are being displayed and their color attributes. Note: Writing design object... : layers (from: Idea/Librarian/Files 14) Note: Writing environment file... : /home2/designs/boards/Disco/Disco_pcb/startup/layout.env Note: Writing environment file... : /home2/designs/boards/Disco/Disco_pcb/startup/fablink_layout.env Note: Writing environment file... : /home2/edmunds/mgc/startup/layout.env Note: Writing design object... : tech (from: Idea/Librarian/Files 14) Note: Writing design object... : testpoints (from: Idea/Librarian/Files 14) So those are the 3 .env files that get touched and two are for layout why. ======================= 5-Nov-2024 in Lyaout: $$view_centered([148.1, 50.4, "BO$disco_0_pcb"]); $view_area([[140.5, 52.1, "BO$disco_0_pcb"], [150.1, 45.4, "BO$disco_0_pcb"]]); $unselect_all(@fills_absent, @geom_attributes_absent, @components_absent, @gates_absent, @guides_absent, @nets_absent, @pins_absent, @pinsets_absent, @references_absent, @text_absent, @traces_absent, @vertices_absent, @vias_absent, @probes_absent, @tea\ rdrops_absent, @arcs_absent, @circles_absent, @lines_absent, @polygons_absent); // Note: Objects unselected = 0. (from: Idea/Librarian/Select 0D) $zoom_out(2); $view_area([[141.4, 50.3, "BO$disco_0_pcb"], [148, 43.9, "BO$disco_0_pcb"]]); // Note: Use space bar to toggle route mode. (from: Uims/base_toolkit/ui_session_tk 81) $route_interactive([144, 48.1, "BO$disco_0_pcb"],@guide_or_trace,@norepeat); $route_from_other_end(); $route_interactive([146.5, 48.1, "BO$disco_0_pcb"],@guide_or_trace,@norepeat); $route_interactive([145.6, 47.3, "BO$disco_0_pcb"],@guide_or_trace,@norepeat); $route_interactive([145.8, 45.5, "BO$disco_0_pcb"],@guide_or_trace,@norepeat); $route_interactive([145.8, 47.3, "BO$disco_0_pcb"],@guide_or_trace,@norepeat); $route_interactive([0, 0, "undo"],@guide_or_trace,@norepeat); $route_interactive([0, 0, "undo"],@guide_or_trace,@norepeat); // ERROR -- Unhandled exception caught: caught signal 11 - SIGSEGV: segmentation violation 23279: /home4/MentorGraphics/2007.5BSXE/MGC_HOME.ss5/pkgs/layout/_lib/layout. fdb20640 waitid (0, 5c53, ffbfbbf0, 3) fdad8ff0 wait4 (5c53, 0, 0, 0, 109654, 8) + a0 fe4c8100 __cbt_bt (0, fdc37c3c, fdd01524, fdcfddc4, 109654, 0) + 30 00e2b77c __1cVpcb_exception_handler6FpnLCore_status_pnPCore_xcpt_hndlr__n0BWCore_xcpt_fixup_action__ (3020808, ffbfea50, 14cd800, 14cd800, 14cd800, 14cd800) + 48 fe4bebe0 __1cPCore_xcpt_hndlrFraise6FpnLCore_status_n0AbGCore_xcpt_hndlr_raise_permission__v_ (3020808, 1, fe533854, fe530424, 700, 400) + 4c fe4ad920 __1cLsig_handler6Fi_v_ (141d7c8, 73c, 400, 12, 1, 3020e68) + 11c fe5756c8 __sighndlr (b, 0, ffbfbfe0, fe4ad804, 0, 0) + c fe56f320 call_user_handler (b, 0, ffbfbfe0, 0, 0, 0) + 234 fe56f4d0 sigacthandler (b, 0, ffbfbfe0, ffbfc240, 2715278, 271528c) + 64 --- called from signal handler with signal 11 (SIGSEGV) --- 00870a10 __1cUPcb_areafill_managerPamend_heal_list6MpnHsegrecr__i_ (1612198, 0, 904d08, 116aba4, 149d400, 0) + 2c 00af6260 __1cLundo_vertex6FrpnHsegrecr_2i_v_ (149ca8c, 149ca90, 212e080, 2, 0, 1) + 2fc 008a0fc4 __1cKpcb_vertex6FiipchCCCC_C_ (1fa8f60, 20001348, 149c800, 1fa76c0, 0, 212b510) + 56c 00df9a44 __1cSPcb_edwire_dynamicKadd_vertex6MrknKCore_point_b_v_ (1, ffbfe498, 3086f10, 30a2010, 1612198, 1) + 49c 00dfa154 __1cSPcb_edwire_dynamicLremove_poly6Mb_v_ (30a2010, 0, 0, 10e4800, 0, 30a2010) + 54 fe23d218 __1cHDynamicNother_key_act6MpnRUi_physical_event__v_ (30a2010, fe418890, 3a4, ffbfe504, fe406978, fe17a1f0) + e4 fe1e1318 __1cSUi_prompt_bar_areaDact6MpnRUi_physical_event__v_ (3065450, fe418890, 11ed4f8, 0, 30a2010, 2fb2710) + 5dc fe19a6b4 __1cMUi_event_mgrPdispatch_events6Mb_v_ (165a010, fe418890, 0, 400, fe406978, ffbfe668) + 4d8 fe20eaa0 __1cPui__take_events6F_v_ (1cc00, 0, c24, 14e8b00, fe406978, c58) + 358 00e156f4 __1cNpcb___uims_go6F_v_ (109e000, 14e8800, 11efc00, ff, 11efc00, 182f010) + 78 0080913c __1cNlay__go__main6F_v_ (10e2400, 141d400, 10e1400, 2, 1560df0, 104e647) + 1ec 00809470 main (2, ffbfeb0c, 104e800, 10d2400, 0, 0) + 300 00278fb0 _start (0, 0, 0, 0, 0, 0) + 108 > > ##################### // // Net Rules from the TECH File not same as GUI or Call Augement List // $$define_net_rules( "POWER_HV", 1.0, 1.0, 0.5, 0.5, 0.32, 0.5, 0.5, "via_2mm2_hv", "PHYSICAL_1, PHYSICAL_2, PHYSICAL_3, PHYSICAL_11, PHYSICAL_12, PHYSICAL_13", " ", , , 0.8, 1.0, 1.0, 1.0); $$define_net_rules( "DIFF_PAIR_HS", 1.0, 0.5, 0.38, 0.12, 1.0, 0.26, 0.21, "via_0mm65, via_0mm60", "PHYSICAL_1, PHYSICAL_2, PHYSICAL_3, PHYSICAL_11, PHYSICAL_12, PHYSICAL_13", " ", , , 0.5, 0.35, 0.5, 0.35); $$define_net_rules( "DIFF_ANALOG", 1.0, 1.0, 0.2, 0.11, 0.28, 0.3, 0.21, "via_0mm79, via_0mm65, via_0mm60", "PHYSICAL_1, PHYSICAL_2, PHYSICAL_3, PHYSICAL_11, PHYSICAL_12, PHYSICAL_13", " ", , , 0.4, 0.2, 0.3, 0.14); $$define_net_rules( "DEFAULT_NET_TYPE", 1.0, 1.0, 0.19, 0.11, 0.32, 0.2, 0.185, "via_2mm2, via_1mm1, via_0mm79, via_0mm65, via_0mm60", "PHYSICAL_1, PHYSICAL_2, PHYSICAL_3, PHYSICAL_11, PHYSICAL_12, PHYSICAL_13", " ", , , 0.5, 0.35, 0.5, 0.35); ##################### $set_shape_edit_mode(); $select_area([[121.3, 172.9, "BO$disco_0_pcb"], [121.3, 172.9, "BO$disco_0_pcb"]], @nofills, @nogeom_attributes, @nocomponents, @nogates, @noguides, @nonets, @nopins, @nopinsets, @noreferences, @notext, @notraces, @vertices, @novias, @noprobes, @notear\drops, @noarcs, @nocircles, @nolines, @nopolygons); // Note: Additional objects selected = 2. (from: Idea/Librarian/Select 0C) $setup_thermal_tie(@smd_tie, 0.111, 4, 1, 360, @pin_tie, 0.222, 4, 4, 405, @via_tie, 0.333, 2, 1, 450); $change_shape_to_fill(@area_fill, "ACCESS_SIGNAL_1", "SIGNAL_11", @solid, @polygon, 0.01, 0.123, 0, 0, [-1, -1, "BO$disco_0_pcb"], @nodeleteshape, @keep_partial_hatch); // Note: Cutout radius is set to: 0.123. (from: Idea/Util/Lay Template 5A) // Note: Number of sides for a circular cutout set to polygon with specified tolerance. (from: Idea/Util/Lay Template C1) // Warning: Cannot change layer of selected Fill_Area(s). Net layer rule violation. (from: Idea/Util/Fill 74) $setup_thermal_tie(@smd_tie, 0.012, 4, 4, 405, @pin_tie, 0.012, 4, 4, 405, @via_tie, 0.012, 4, 4, 405); ##################### $setup_thermal_tie(@smd_tie, 0.111, 4, 1, 360, @pin_tie, 0.222, 4, 2, 405, @via_tie, 0.333, 4, 4, 0); $change_shape_to_fill(@area_fill, "ACCESS_SIGNAL_1", "SIGNAL_2", @solid, @polygon, 0.444, 0.555, 0, 0, [-1, -1, "BO$disco_0_pcb"], @nodeleteshape, @keep_partial_hatch); // Note: Cutout radius is set to: 0.555. (from: Idea/Util/Lay Template 5A) // Note: Number of sides for a circular cutout set to polygon with specified tolerance. (from: Idea/Util/Lay Template C1) // Note: Aperture size for Fill_Areas is changed to : 0.444. (from: Idea/Util/Lay Template 63) ##################### // Note: Objects unselected = 0. (from: Idea/Librarian/Select 0D) // Note: To include an arc in the polygon boundary, use Select mouse button to set initial (from: Uims/base_toolkit/ui_session_tk 81) // Note: point - Spacebar to enter second point - Select mouse button to complete arc. (from: Uims/base_toolkit/ui_session_tk 81) $cutout_area_fill(void, "SIGNAL_1", [181.8, 163.8, 181.8, 172.9, 185.8, 172.9, 185.8, 163.8, 181.8, 163.8], @NoRepeat); // Note: No messages generated for "Cutout_Area_Fill" (from: Idea/Util/Pcb_Ui 02) $$view_centered([183.8, 168.5, "BO$disco_0_pcb"]); > > tail traces.traces_529 SEG 9890000 9140000 1 0 # NET 'ZQ_REFERENCE_U402' WIR 6 9880000 10180000 9890000 10440000 SEG 9880000 10180000 1 30000 SEG 9880000 10230000 1 30000 SEG 9900000 10250000 1 30000 SEG 9900000 10400000 1 30000 SEG 9890000 10410000 1 30000 SEG 9890000 10440000 1 0 ST 0 4161 169 534 0 0 0 0 > > > > tail traces.traces_530 SEG 9900000 10250000 1 30000 SEG 9900000 10400000 1 30000 SEG 9890000 10410000 1 30000 SEG 9890000 10440000 1 0 FIL '$NONE' 'SIGNAL_1' CUTOUT 4 0 0 0 0 0 0 0 0 T 22 22 22 VER 18180000 16380000 VER 18580000 16380000 VER 18580000 17290000 VER 18180000 17290000 ST 0 4161 169 534 0 0 0 1 > > ##################### Setup ---> Shape Edit Mode ON Right panel memue ---> Shape to Fill Select Shape Select: Area Fill, Layer: Signal_1, Net: SHIELD, Polygon, Manufacture Aperture Size: 0.1 mm Mininum Pad Slot Threshold: 0 Solid, Thermal Ties: SMD FLOOD, Pin FLOOD, Via FLOOD Delete Original Shape: NO I did NOT set: Design Rule Relieves or segments per 2 pi This generally looks OK but it does slot down between the 0603 resistors in the termination networks. Try again but with a big Minimum Pad Slot Threshold, e.g. 5 mm which may be 500000 in precision units. This looks the same - still a slot between resistors in a network. Setting Pin Via & Trace reelief to Fill to 0.4 mm for the Default Net Type makes things look pretty nice. neet to try 0.35 mm for all three. ##################### ##################### #####################