The following notes are mostly extracted from emails that
I received from Nathan.  Some points were gleaned from
various proto-type and test board schematics.

                                         Initial Rev.  24-Oct-2022
                                         Current Rev.   2-Jan-2023


The PMT ADC Sampling Rate is:  208.3  Msps
Is that the exact value ?

The PMT ADC Serial Output Line Rate is:  12.5 Gbps
Is that the exact value ?

Nathan says the one-bit sampler in the PMT ADC runs
at  1.6 Gsps  is that the exact value ?

What is the clock frequency to the PMT ADC ?

What are the  M / N  integer multipliers to get from the
ADC's input clock frequency to each of the 3 items listed
above:  ADC Sample Rate,  Serial Output Line Rate,  and
one-bit sampler rate ?


Here's a rough written description of the board features
from Nathan on 16-June-2022:

  Total power consumption: < 8 W

  Input voltage: 96VDC

  Max. global timing uncertainty: ~ 0.8 ns

  Output data rate: ~ 1 Mbps

  Data lines in and out:

   - 16x PMT signals

   - Two single-mode dedicated optical fibers

   - 1 pair dedicated power

   - Up to 4 pairs digital copper IO.  We had planned to
     use these for 2x LVDS timing signals (bidirectional),
     1x data (10BASE-T1L single-pair ethernet), and
     1x RS-485 for backup programming access

   - An external digital interface to the HV supplies on
     the PMT bases, likely either I2C or a whole lot of UARTs


  Key components:

   - Power supply to step 96V down to something reasonable

   - AD9083 ADC, connected by 4x JESD204b links at the
     most 12.7 Gbps to:

   - MPS250T FPGA (784-pin package)

   - DDR4 or DDR3L RAM attached to FPGA, in an amount we
     are deciding on, but at the few-GB level. This will
     store a ring buffer of waveforms from the ADC.

   - Central high-precision timing sync and on-board
     distribution (ADC clock, mostly), for which we had
     penciled in a PLL and synchronizer chip, the AD9546

      - Copper timing connected to that by an M-LVDS
        transceiver.  We had penciled in the ADN4680E,
        which is on the prototype board we were looking
        at today.

      - Optical timing in on a pair of differential
        lines, one for a frequency reference and one for
        a synchronization pulse.

      - ADC clock out

      - ADC timing reference pulse (JESD204B SYSREF) out


   - Optical timing and data TBD, currently being designed
     by Germans.

   - A 10BASE-T1L PHY attached to the FPGA for copper
     ethernet communications

   - 2x SPI flash for the FPGA firmware

   - Some microcontroller or other to attach to the RS-485
     line to allow the FPGA to be reprogrammed or other
     recovery to be done in case we make a mistake and
     flash bad firmware

   - As-yet-unspecified calibration devices

   - PMT signal coupling, likely just need single-ended to
     differential conversion and something so we don't waste
     half our dynamic range, e.g. just offseting the DC level
     of the signal.


List of some of the Inegrated Circuits:

  FPGA  -  Its specific part number:   MPFS250T-1FCVG784E

     And schematics and layout files for its evaluation board:
     https://www.microsemi.com/existing-parts/parts/152514#resources

     The eval. board is the 484-pin version, and we have
     the 784-pin version.

  Ethernet  -  ADIN2111

  M-LVDS Transmitter  -  DS91M125

  M-LVDS Receiver/Repeater  -  ADN4680E

  Clock Generator  -  AD9546

  ADC  -  AD9083