Nathan Meeting Topics 11-Nov-2022 -------------------------------------- 1. I need a drop-dead decision on the name of this board. 2. Power Supplies: Required Power Buses and anticipated Loads Is there a list of this information or should I start making such a list ? What is the input power - does it need special conditioning before use. We will need to fully understand the required startup sequence for the various supplies and need to include a startup sequencer (for both order of start up and ramp rate). Are there any individual loads that you want to be able to turn Off, i.e. that need their own independent power supply ? Are there any loads that draw high current during their start up (e.g. FPGA) and then once running drop down to their normal load ? I assume the basic layout will be something like: a single step down converter that takes the input power and drops it down to 12 Volts and then multiple non-isolating buck converters to make the various supply rails. Should the single step down converter from the input power be an isolated converter. Concern - I've not done any low power work in a while and I like to well over design the power supplies and their filtering. 3. Questions about Block Diagram Blue Tooth - really ? Do you really want RF running around in this system ? 4. Note to colleagues - my concerns I've done lots of complicated FPGA boards but only ever worked with Xilinx. What am I going to screw up because I'm so Xilinx-centric in my thinking ? I've never done a pcb design where I have not been deeply involved in the System design and Circuit Design. What am I likely to screw up because I'm only weakly connected to the System (and Circuit) design of this card. I like to get things 100% right at Rev. A. --> I will have lots of annoying questions and lots of "cool-down" and checking before release for build. 5. Is there an overall sch or do I make one, is my work on this project just the pcb layout or am I also doing the overall circuit design ? 6. Is the "Data Link" optical - if so then why not carry both Data and Timing on the same link ? 7. I'm working on the foot-prints, in Metor Graphics speak "geometries", for the following parts: MPFS250T-1FCVG784E FPGA AD9083BBCZ ADC AD9546BCPZ Clock Generator ADIN2111BCPZ (or CCPZ) Ethernet ADN4680EBCPZ M-LVDS Receiver/Repeater DS91M125 M-LVDS Fanout Others at this time ? 8. We need to start understanding the PCB stackup. I assume that the layer count will be driven by the FPGA, and the power distribution requirements under the FPGA. That second point may be driven by what IO Banks need which supply rails. That is we need to start understanding the IO Bank connections. 9. Is the 784 pin count package needed ? are there enough IOs on the 484 pin part ? Escaping the 784 connections on this FPGA/CPU is very likely going to drive the PCB layer count and its cost. 10. When, Who, How to allocate the pins on the FPGA - both FPGA pins and its CPU pins ? Do you have (or do I need to start) a list of how many pins of each type each box that connects to the FPGA & CPU needs. I.E. each line on your block diagram that leads to the FPGA & CPU needs to include pin count and pin type information How much control to move things around do I get during layout ? You need to get ready to request that people "now and forever more" sign-off on FPGA & CPU pin assignments. 11. Do you have people working in parallel with the PCB layout to prove that the assignments of FPGA/CPU pins meets the restrictions imposed by the FPGA/CPU or by the FW/SW development tools ? You need to prove that FPGA FW and CPU SW can instance the signals at the pins they are being connected to on the PCB. This is not "throw away" work. All versions of all FPGA FW and CPU SW should include the code that sets up all IO connections in the final system. This is required both for good CMOS etiquette and to prove that your IO assignments can be meet. This needs to be done in a way that is not optimized out by your design tools. 12. I will need a decision about how much, how fast, and what kind of DDR memory you want for both the FPGA and for the CPUs. Note that the range of choices is driven by what the DDR Controllers in the MPFS250T can work with and that is a many page document in itself. 13. I want print sets for all of the orange boxes aka separate boards. 14. Need to have (or start draft version of) the pinout and definition for all connectors on this board, i.e. all orange boxes on this board plus all other connectors, e.g. power input, cable signals, bench test "Access" connector, ... I need this before starting any serious layout work. 15. Define all connectors on the your board: part number, pinout, high quality reliable connectors are important, Through Hole board mount connectors may be important if your cards will experience a lot of handling by careless people. This is an interface definition. 16. What is the mechanical foot-print of any mezzanine cards ? What mechanical mount points must your card provide for any mezzanines ? 17. Is there a formal list of all the other boards (orange boxes) that will plug into your board and who the official contact is for each of these boards ? 18. Yes, move the transformers to the PMT boards, make the "long" analog runs differential. 19. Number of cards to make in the initial build: - boards for the initial deployed string of modules - a board for each institution that needs to test some component of the overall system - spare boards - manufacturing or final assembly failure boards 20. Component procurement for the initial build: - driven by how many boards you need to make in the initial build - strongly driven by sole source parts - who handles the component purchases ? - where to store the components ? - how many spare components do you need to support manufacturing and to support any required repair work ? You have selected a lot of sole source parts and thus need to be very careful - ask Wade. 21. Clocks going to the FPGA & CPU how many are they ? where do they need to land for optimum clock distribution within these components ? does the system keep running on a "local clock" ? can you run (do you want to be able to run) "stand alone" without the full chain or head end equipment ? What all other boxes, e.g. Enet Phy need clocks. Will the RC clocks in the FPGA / CPU run at 0 deg C ? Who signs off on the Clocks ? 22. Confused about the number of optical I/O connections How many are there ? Are they all SFP or what ? I thought that there was too little power for optical ? 23. Overall shape, dimensions, and mounting points of your board ? My guess is that you will not know this in time for me to get started - so we need to agree on the shape dimensions and mounting points that I will use for now - known full well that this all will change. 24. Your board must support two kinds of testing: proof that the design functions as needed some what of a one time test on one board and Production Testing of all boards. What features are needed to support these two separate testing requirements ? Who is in charge of the Final Assembly and Production Testing ? 25. You should have a Power Supply Monitor connector, i.e. a connector where you can plug a cable to a "rotor switch" to a known good DVM to verify the operation of all power supplies and verify the operation of all on-board power supply monitor read-back functions. The points are to test all cards without probing around with hand held DVM probes. 26. You probably need an "Access Connector" to allow access to: JTAG strings, I2C strings, SPI strings, a few FPGA IIOs, a few CPU IOs, CPU terminal connection and ... This is needed for: Initial Cold Start of the board, for debugging any cards that fail production tests, special tests without soldering on White Wires, emergency "Life Boat". 27. List of all Clocks on your card, e.g. FPGA, CPU, High-Speed Serial Link, ... Where does each clock connect to the FPGA/CPU for optimum pcb layout and optimum distribution within the FPGA/CPU. Have you built in any chicken-egg problems, i.e. the clock does not automatically run at Cold Start and the FPGA/CPU can not "configure" the clock source without a running clock. 28. Are all types of Cold Start covered: initial test cold start, power failure and resumption during normal operation cold start, power failure while down loading new FW/SW and then cold start, ... e.g. chicken-egg no communications without the CPU configuring the Enet interface. 29. I believe that MPFS250T-1FCVG784E is a 0 deg C to 100 deg C "consumer" temperature range part in the higher speed "1" version. You are going to be cold starting this part from 0 deg C, i.e. right at it limit. Is that smart for a 20 year high reliability system ? 29 / 95 = 0.305 ML