Nathan Questions - Meeting Topics    December 2022 List
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      1. Need to review the analog input to the PMT ADCs.
            How to minimize noise pickup ?
            Do you need more anti-aliasing filters ?
            Do you want to pick up the other half of the dynamic range ?
            Was the idea of going single-ended to differential at the
               PMT Base taken too quickly ?
            If the single-ended to differential is actual on the
               PMT Interposer then it might be better on the DK brd ?
            Is there room on DK for serious analog input section to
               the PMT ADCs ?

      2. Review the current ideas for the Power Supply design.
            It may be very important to keep noise coming out of the
               power supply input off of the long main cable ?
            For example was your copper module to module timing
               distribution circuit tested with adjacent pair noise ?
            Are the proposed 100 V to 5 V converters stable with a
               soft input source under all conditions ?
            Problem of long life capacitors for the 100 V input filters ?
            One can not service this thing so how important is
               diagnostic read-back ?
            Basically any PS failure will mean no communication with
               the module so perhaps keeping it simple and clean is
               better than fancy with lots of diagnostic read-backs ?
            Stay focused on Physics - not on cleaver bells & whistles
               that add nothing to getting Physics done.
            We need to start bench testing of all power supply
               components under realistic input/output conditions.

      3. Do you want extra diagnostics in the first string ?

      4. Will the extra Up going pairs in the main cable be used
         for anything ?   e.g. for a module to module ground connection

      5. Can you run the whole Fabric DDR ADC Buffer Memory on the basis
         of a simultaneous time slice of all 16 ADCs ?   I assume that
         one sample from one ADC is 2 bytes.  If the Fabric's DDR Memory
         is 32 bits wide and the DDR naturally operates in bursts of
         8  then a single "frame" of data,  i.e. a simultaneous sample
         for all 16 ADCs,  just fits into a natural DDR burst for a
         32 bit wide memory.  Why not make all parts of the data path
         from: PMT ADCs,  Input FIFO,  main DDR Circular Buffer,  Output
         FIFO,  path to trigger,  path to Enet main data readout,
         that is everything,  work at the level of this quanta of data,
         i.e. addresses are at the  32 byte boundary.


         5 / 95  =  0.053 ML