Clock Input and Output Pins Accessible on the DK's FPGA FCG1152 -----------------------------------------------------------=======- Original Rev. 12-June-2024 Current Rev. 12-June-2024 Recall the use of the FPGA/CPU's I/O Banks on the DK board: Bank Voltage Function on the DK Board ---- ------- ------------------------------- 0 1V2 FPGA DDR4 Memory ---> 1 3V3 General I/O FPGA GPIO 2 3V3 USB UPLI Bus & QSPI 3 3V3 System Controller: JTAG, Controller SPI 4 - no power, not used, adjacent to bank 6 ---> 5 3V3 Used only for CPU Clock input 6 1V2 CPU DDR4 Memory ---> 7 3V3 General I/O FPGA GPIO 8 - no power, not used, between banks 0 and 6 ---> 9 1V8 General I/O FPGA GPIO The fixed location High Speed Transceiver Clock pins are not listed in this file. Recall that the inputs to the Clock Conditioner Circuit (CCC) can feed either the Reference signal or the Feedback signal to a PLL but that a given CCC input can only feed one of these two signal types to the PLL. See the "PolarFire SoC FPGA Clocking Resources" manual on page 15 section 2.4.2 about CCC Inputs. Whether a given CCC Input can provide a Reference signal or a Feedback signal is shown in a 2nd table at the end of this document. All signals are bonded out in the FCG1152 package for the MPFS250T FPGA/CPU so by some definition all of the Clock inputs and outputs are accessable in this package. Accessible Clock Pins in Banks: 1, 5, 7, 9 --------------------------------------------- Bank 1 FPGA GPIO: General 3V3 I/O on the DK board ------------------- L15 GPIO0PB1/ CLKIN_S_4 J14 GPIO1PB1/ CLKIN_S_5 J15 GPIO3PB1/ CLKIN_S_6 K16 GPIO5PB1/ CLKIN_S_7 J13 GPIO9PB1/ CLKIN_S_8/ CCC_SE_CLKIN_S_8 E11 GPIO11PB1/ CLKIN_S_9/ CCC_SE_CLKIN_S_9 B10 GPIO15PB1/ CCC_SE_CLKIN_S_10 C11 GPIO17PB1/ CCC_SE_CLKIN_S_11 # Gap in the xlsx pin table for Bank 1 # E2 GPIO168PB1/ CCC_SW_CLKIN_S_0 C1 GPIO169PB1/ CCC_SW_CLKIN_S_1 C2 GPIO170PB1/DQS/ CCC_SW_PLL1_OUT0 E3 GPIO171PB1/ CLKIN_S_2/ CCC_SW_CLKIN_S_2/ CCC_SW_PLL1_OUT0 B2 GPIO172PB1/ CCC_SW_PLL1_OUT1 A3 GPIO173PB1/ CLKIN_S_3/ CCC_SW_CLKIN_S_3 F4 GPIO176PB1/DQS/ CCC_SW_PLL0_OUT0 B4 GPIO177PB1/ CCC_SW_PLL0_OUT0 E6 GPIO178PB1/ CCC_SW_PLL0_OUT1 Bank 5 Ethernet SGMII: Used only for CPU clock input and the SMGII ------------------------ to the TOMcat on the DK board W3 MSS_REFCLK_IN_N MSS_DDR_SGMII 5 I/O MSS_REFCLK V3 MSS_REFCLK_IN_P MSS_DDR_SGMII 5 I/O MSS_REFCLK Bank 7 FPGA GPIO: General 3V3 I/O on the DK board ------------------- U2 GPIO139PB7/ CLKIN_W_7 T4 GPIO140PB7/ CLKIN_W_6 R3 GPIO142PB7/ CLKIN_W_5 T3 GPIO143PB7/ CLKIN_W_4 L9 GPIO162PB7/ CLKIN_W_3/ CCC_SW_CLKIN_W_3 L10 GPIO163PB7/ CLKIN_W_2/ CCC_SW_CLKIN_W_2/ CCC_SW_PLL0_OUT0 N13 GPIO164PB7/ CLKIN_W_1/ CCC_SW_CLKIN_W_1 M11 GPIO165PB7/DQS/ CCC_SW_PLL0_OUT0 M14 GPIO167PB7/ CLKIN_W_0/ CCC_SW_CLKIN_W_0 Bank 9 FPGA GPIO: General 1V8 I/O on the DK board ------------------- A27 GPIO56PB9/DQS/ CCC_SE_PLL0_OUT0 A29 GPIO57PB9/ CLKIN_S_12/ CCC_SE_CLKIN_S_12/ CCC_SE_PLL0_OUT0 D26 GPIO58PB9/ CCC_SE_PLL0_OUT1 A30 GPIO59PB9/ CLKIN_S_13/ CCC_SE_CLKIN_S_13 F27 GPIO62PB9/DQS/ CCC_SE_PLL1_OUT0 G25 GPIO63PB9/ CCC_SE_CLKIN_S_14/ CCC_SE_PLL1_OUT0 J26 GPIO64PB9/ CCC_SE_PLL1_OUT1 J27 GPIO65PB9/ CCC_SE_CLKIN_S_15 CCC Inputs - Reference or Feedback Signal to the PLL: ----------------------------------------------------- Bank 1 FPGA GPIO: General 3V3 I/O on the DK board ------------------- J13 CCC_SE_CLKIN_S_8 PLL Reference E11 CCC_SE_CLKIN_S_9 PLL Reference B10 CCC_SE_CLKIN_S_10 PLL Feedback DLL Reference or Feedback C11 CCC_SE_CLKIN_S_11 PLL Feedback DLL Reference or Feedback # Gap in the xlsx pin table for Bank 1 # E2 CCC_SW_CLKIN_S_0 PLL Reference C1 CCC_SW_CLKIN_S_1 PLL Reference E3 CCC_SW_CLKIN_S_2 PLL Feedback DLL Reference or Feedback A3 CCC_SW_CLKIN_S_3 PLL Feedback DLL Reference or Feedback Bank 7 FPGA GPIO: General 3V3 I/O on the DK board ------------------- L9 CCC_SW_CLKIN_W_3 PLL Feedback DLL Reference or Feedback L10 CCC_SW_CLKIN_W_2 PLL Feedback DLL Reference or Feedback N13 CCC_SW_CLKIN_W_1 PLL Reference M14 CCC_SW_CLKIN_W_0 PLL Reference Bank 9 FPGA GPIO: General 1V8 I/O on the DK board ------------------- A29 CCC_SE_CLKIN_S_12 PLL Reference A30 CCC_SE_CLKIN_S_13 PLL Reference G25 CCC_SE_CLKIN_S_14 PLL Feedback DLL Reference or Feedback J27 CCC_SE_CLKIN_S_15 PLL Feedback DLL Reference or Feedback For Reference the following shows the Clock type connections in Bank #8. Bank #8 an HSIO type bank that is not powered in the DK design. ------------------------------------------------------------------------- AH9 HSIO127PB8/ CCC_NW_PLL0_OUT1 AJ8 HSIO128PB8/ CCC_NW_PLL0_OUT0 AJ10 HSIO129PB8/DQS/ CCC_NW_PLL0_OUT0 AN6 HSIO132PB8/ CCC_NW_CLKIN_N_15 AP5 HSIO133PB8/ CCC_NW_PLL1_OUT1 AL7 HSIO134PB8/ CCC_NW_CLKIN_N_14/ CCC_NW_PLL1_OUT0 AN4 HSIO135PB8/DQS/ CCC_NW_PLL1_OUT0 AN3 HSIO136PB8/ CLKIN_N_13/ CCC_NW_CLKIN_N_13 AM5 HSIO137PB8/ CLKIN_N_12/ CCC_NW_CLKIN_N_12