Clock Input and Output Pins Accessible on the DK's FPGA/CPU -------------------------------------------------------------- Original Rev. 4-Mar-2024 Current Rev. 15-Mar-2024 Recall the use of the FPGA/CPU's I/O Banks on the DK board: Bank Voltage Function on the DK Board ---- ------- ------------------------------- 0 1V2 FPGA DDR4 Memory ---> 1 3V3 General I/O FPGA GPIO 2 3V3 USB UPLI Bus & QSPI 3 3V3 System Controller: JTAG, Controller SPI 4 - no power, not used, adjacent to bank 6 ---> 5 3V3 Used only for CPU Clock input 6 1V2 CPU DDR4 Memory ---> 7 3V3 General I/O FPGA GPIO 8 - no power, not used, between banks 0 and 6 ---> 9 1V8 General I/O FPGA GPIO The fixed location High Speed Transceiver Clock pins are not listed in this file. Recall that the inputs to the Clock Conditioner Circuit (CCC) can feed either the Reference signal or the Feedback signal to a PLL but that a given CCC input can only feed one of these two signal types to the PLL. See the "PolarFire SoC FPGA Clocking Resources" manual on page 15 section 2.4.2 about CCC Inputs. Whether a given CCC Input can provide a Reference signal or a Feedback signal is shown in a 2nd table at the end of this document. Accessible Clock Pins in Banks: 1, 5, 7, 9 --------------------------------------------- Bank 1 FPGA GPIO: General 3V3 I/O on the DK board ------------------- D9 GPIO0PB1/ CLKIN_S_4 B7 GPIO1PB1/ CLKIN_S_5 A8 GPIO3PB1/ CLKIN_S_6 B10 GPIO5PB1/ CLKIN_S_7 G12 GPIO9PB1/ CLKIN_S_8/ CCC_SE_CLKIN_S_8 J14 GPIO11PB1/ CLKIN_S_9/ CCC_SE_CLKIN_S_9 C14 GPIO15PB1/ CCC_SE_CLKIN_S_10 A12 GPIO17PB1/ CCC_SE_CLKIN_S_11 # Gap in the xlsx pin table for Bank 1 # C2 GPIO168PB1/ CCC_SW_CLKIN_S_0 E3 GPIO169PB1/ CCC_SW_CLKIN_S_1 E1 GPIO170PB1/DQS/ CCC_SW_PLL1_OUT0 D3 GPIO171PB1/ CLKIN_S_2/ CCC_SW_CLKIN_S_2/ CCC_SW_PLL1_OUT0 C1 GPIO172PB1/ CCC_SW_PLL1_OUT1 A2 GPIO173PB1/ CLKIN_S_3/ CCC_SW_CLKIN_S_3 D4 GPIO176PB1/DQS/ CCC_SW_PLL0_OUT0 B4 GPIO177PB1/ CCC_SW_PLL0_OUT0 D6 GPIO178PB1/ CCC_SW_PLL0_OUT1 Bank 5 Ethernet SGMII: Used only for CPU clock input ------------------------ on the DK board R11 MSS_REFCLK_IN_N P11 MSS_REFCLK_IN_P Bank 7 FPGA GPIO: General 3V3 I/O on the DK board ------------------- J3 GPIO139PB7/ CLKIN_W_7 J5 GPIO140PB7/ CLKIN_W_6 K7 GPIO142PB7/ CLKIN_W_5 H7 GPIO143PB7/ CLKIN_W_4 K1 GPIO162PB7/ CLKIN_W_3/ CCC_SW_CLKIN_W_3 H1 GPIO163PB7/ CLKIN_W_2/ CCC_SW_CLKIN_W_2/ CCC_SW_PLL0_OUT0 F4 GPIO164PB7/ CLKIN_W_1/ CCC_SW_CLKIN_W_1 G2 GPIO165PB7/DQS/ CCC_SW_PLL0_OUT0 G5 GPIO167PB7/ CLKIN_W_0/ CCC_SW_CLKIN_W_0 Bank 9 FPGA GPIO: General 1V8 I/O on the DK board ------------------- C27 GPIO56PB9/DQS/ CCC_SE_PLL0_OUT0 A27 GPIO57PB9/ CLKIN_S_12/ CCC_SE_CLKIN_S_12/ CCC_SE_PLL0_OUT0 D25 GPIO58PB9/ CCC_SE_PLL0_OUT1 B28 GPIO59PB9/ CLKIN_S_13/ CCC_SE_CLKIN_S_13 F22 GPIO62PB9/DQS/ CCC_SE_PLL1_OUT0 E21 GPIO63PB9/ CCC_SE_CLKIN_S_14/ CCC_SE_PLL1_OUT0 H22 GPIO64PB9/ CCC_SE_PLL1_OUT1 F23 GPIO65PB9/ CCC_SE_CLKIN_S_15 CCC Inputs - Reference or Feedback Signal to the PLL: ----------------------------------------------------- Bank 1 FPGA GPIO: General 3V3 I/O on the DK board ------------------- G12 CCC_SE_CLKIN_S_8 PLL Reference J14 CCC_SE_CLKIN_S_9 PLL Reference C14 CCC_SE_CLKIN_S_10 PLL Feedback DLL Reference or Feedback A12 CCC_SE_CLKIN_S_11 PLL Feedback DLL Reference or Feedback # Gap in the xlsx pin table for Bank 1 # C2 CCC_SW_CLKIN_S_0 PLL Reference E3 CCC_SW_CLKIN_S_1 PLL Reference D3 CCC_SW_CLKIN_S_2 PLL Feedback DLL Reference or Feedback A2 CCC_SW_CLKIN_S_3 PLL Feedback DLL Reference or Feedback Bank 7 FPGA GPIO: General 3V3 I/O on the DK board ------------------- K1 CCC_SW_CLKIN_W_3 PLL Feedback DLL Reference or Feedback H1 CCC_SW_CLKIN_W_2 PLL Feedback DLL Reference or Feedback F4 CCC_SW_CLKIN_W_1 PLL Reference G5 CCC_SW_CLKIN_W_0 PLL Reference Bank 9 FPGA GPIO: General 1V8 I/O on the DK board ------------------- A27 CCC_SE_CLKIN_S_12 PLL Reference B28 CCC_SE_CLKIN_S_13 PLL Reference E21 CCC_SE_CLKIN_S_14 PLL Feedback DLL Reference or Feedback F23 CCC_SE_CLKIN_S_15 PLL Feedback DLL Reference or Feedback