MPFS250T-FCVG784 Bank 6 All Pins ------------------------------------ Original Rev. 8-Mar-2023 Current Rev. 7-Sept-2023 This file is all of the Bank 6 pins from the MPFS250T-FCVG784 Tab of the Pin Table .xlsx file from Microchip obtained on 6-Mar-2023. Bank 6 is the MSS (aka CPU) DDR Memory Controller. There are 88 pins in Bank 6. It currently appears that 15 pins in the Bank 6 DDR Controller are not used by the DDR4 memory system on the Disco-Kraken board. MSS MPFS250T Used by Pin FCVG784 the DK's Nmb Pin Names DDR Lane Bank CPU DDR4 --- -------------- ------------- ----- -------- AH4 MSS_DDR_DM3 MSS_DDR_DATA3 6 Y AG4 MSS_DDR_DQ31 MSS_DDR_DATA3 6 Y AG5 MSS_DDR_DQ30 MSS_DDR_DATA3 6 Y AH3 MSS_DDR_DQ29 MSS_DDR_DATA3 6 Y AH2 MSS_DDR_DQ28 MSS_DDR_DATA3 6 Y AG2 MSS_DDR_DQS_N3 MSS_DDR_DATA3 6 Y AF2 MSS_DDR_DQS_P3 MSS_DDR_DATA3 6 Y AG1 MSS_DDR_DQ27 MSS_DDR_DATA3 6 Y AF1 MSS_DDR_DQ26 MSS_DDR_DATA3 6 Y AF3 MSS_DDR_DQ25 MSS_DDR_DATA3 6 Y AF4 MSS_DDR_DQ24 MSS_DDR_DATA3 6 Y AE1 MSS_DDR_DM2 MSS_DDR_DATA2 6 Y AD1 MSS_DDR_DQ23 MSS_DDR_DATA2 6 Y AE2 MSS_DDR_DQ22 MSS_DDR_DATA2 6 Y AE6 MSS_DDR_DQ21 MSS_DDR_DATA2 6 Y AF5 MSS_DDR_DQ20 MSS_DDR_DATA2 6 Y AE3 MSS_DDR_DQS_N2 MSS_DDR_DATA2 6 Y AD3 MSS_DDR_DQS_P2 MSS_DDR_DATA2 6 Y AD4 MSS_DDR_DQ19 MSS_DDR_DATA2 6 Y AD5 MSS_DDR_DQ18 MSS_DDR_DATA2 6 Y AE5 MSS_DDR_DQ17 MSS_DDR_DATA2 6 Y AD6 MSS_DDR_DQ16 MSS_DDR_DATA2 6 Y AC9 MSS_DDR_DM1 MSS_DDR_DATA1 6 Y AB9 MSS_DDR_DQ15 MSS_DDR_DATA1 6 Y AA9 MSS_DDR_DQ14 MSS_DDR_DATA1 6 Y AC8 MSS_DDR_DQ13 MSS_DDR_DATA1 6 Y AB6 MSS_DDR_DQ12 MSS_DDR_DATA1 6 Y AA8 MSS_DDR_DQS_N1 MSS_DDR_DATA1 6 Y AA7 MSS_DDR_DQS_P1 MSS_DDR_DATA1 6 Y AA5 MSS_DDR_DQ11 MSS_DDR_DATA1 6 Y AC7 MSS_DDR_DQ10 MSS_DDR_DATA1 6 Y AC6 MSS_DDR_DQ9 MSS_DDR_DATA1 6 Y AB7 MSS_DDR_DQ8 MSS_DDR_DATA1 6 Y AC3 MSS_DDR_DM0 MSS_DDR_DATA0 6 Y AC2 MSS_DDR_DQ7 MSS_DDR_DATA0 6 Y AC1 MSS_DDR_DQ6 MSS_DDR_DATA0 6 Y AC4 MSS_DDR_DQ5 MSS_DDR_DATA0 6 Y AA2 MSS_DDR_DQ4 MSS_DDR_DATA0 6 Y AB1 MSS_DDR_DQS_N0 MSS_DDR_DATA0 6 Y AB2 MSS_DDR_DQS_P0 MSS_DDR_DATA0 6 Y AA3 MSS_DDR_DQ3 MSS_DDR_DATA0 6 Y AA4 MSS_DDR_DQ2 MSS_DDR_DATA0 6 Y AB4 MSS_DDR_DQ1 MSS_DDR_DATA0 6 Y AB5 MSS_DDR_DQ0 MSS_DDR_DATA0 6 Y Y10 MSS_DDR_VREF_IN N/A 6 N W11 MSS_DDR_DM4 MSS_DDR_ECC 6 N Y8 MSS_DDR_DQS_N4 MSS_DDR_ECC 6 N Y7 MSS_DDR_DQS_P4 MSS_DDR_ECC 6 N Y11 MSS_DDR_DQ35 MSS_DDR_ECC 6 N AA10 MSS_DDR_DQ34 MSS_DDR_ECC 6 N AB11 MSS_DDR_DQ33 MSS_DDR_ECC 6 N AB10 MSS_DDR_DQ32 MSS_DDR_ECC 6 N Y5 MSS_DDR_A9 MSS_DDR_ADDCMD0 6 Y W6 MSS_DDR_A8 MSS_DDR_ADDCMD0 6 Y Y6 MSS_DDR_A7 MSS_DDR_ADDCMD0 6 Y W5 MSS_DDR_A6 MSS_DDR_ADDCMD0 6 Y W4 MSS_DDR_A5 MSS_DDR_ADDCMD0 6 Y W3 MSS_DDR_A4 MSS_DDR_ADDCMD0 6 Y W1 MSS_DDR_A3 MSS_DDR_ADDCMD0 6 Y Y1 MSS_DDR_A2 MSS_DDR_ADDCMD0 6 Y V2 MSS_DDR_A1 MSS_DDR_ADDCMD0 6 Y V1 MSS_DDR_A0 MSS_DDR_ADDCMD0 6 Y Y2 MSS_DDR_CK_N0 MSS_DDR_ADDCMD0 6 Y Y3 MSS_DDR_CK0/ MSS_DDR_ADDCMD0 6 Y DDR_PLL0_OUT0 W10 MSS_DDR_BA1 MSS_DDR_ADDCMD1 6 Y U11 MSS_DDR_BA0 MSS_DDR_ADDCMD1 6 Y V11 MSS_DDR3_WE_N MSS_DDR_ADDCMD1 6 N U10 MSS_DDR_A16 MSS_DDR_ADDCMD1 6 Y U7 MSS_DDR_A15 MSS_DDR_ADDCMD1 6 Y T7 MSS_DDR_A14 MSS_DDR_ADDCMD1 6 Y V8 MSS_DDR_A13 MSS_DDR_ADDCMD1 6 Y V7 MSS_DDR_A12 MSS_DDR_ADDCMD1 6 Y U9 MSS_DDR_A11 MSS_DDR_ADDCMD1 6 Y V9 MSS_DDR_A10 MSS_DDR_ADDCMD1 6 Y W9 MSS_DDR_CK_N1 MSS_DDR_ADDCMD1 6 N W8 MSS_DDR_CK1/ MSS_DDR_ADDCMD1 6 N DDR_PLL0_OUT0 V6 MSS_DDR_ALERT_N MSS_DDR_ADDCMD2 6 Y U6 MSS_DDR_PARITY MSS_DDR_ADDCMD2 6 Y U5 MSS_DDR_ACT_N MSS_DDR_ADDCMD2 6 Y T5 MSS_DDR_ODT1 MSS_DDR_ADDCMD2 6 N T2 MSS_DDR_CKE1 MSS_DDR_ADDCMD2 6 N T3 MSS_DDR_CS1 MSS_DDR_ADDCMD2 6 N V3 MSS_DDR_ODT0 MSS_DDR_ADDCMD2 6 Y V4 MSS_DDR_CKE0 MSS_DDR_ADDCMD2 6 Y T4 MSS_DDR_CS0 MSS_DDR_ADDCMD2 6 Y U4 MSS_DDR_BG1 MSS_DDR_ADDCMD2 6 N U2 MSS_DDR_BG0 MSS_DDR_ADDCMD2 6 Y U1 MSS_DDR_RAM_RST_N/ MSS_DDR_ADDCMD2 6 Y DDR_PLL0_OUT1 Now Show the exact same information but listed in pin number order: ----------------------------------- MSS MPFS250T Used by Pin FCVG784 the DK's Nmb Pin Names DDR Lane Bank CPU DDR4 --- -------------- ------------- ----- -------- T2 MSS_DDR_CKE1 MSS_DDR_ADDCMD2 6 N T3 MSS_DDR_CS1 MSS_DDR_ADDCMD2 6 N T4 MSS_DDR_CS0 MSS_DDR_ADDCMD2 6 Y T5 MSS_DDR_ODT1 MSS_DDR_ADDCMD2 6 N T7 MSS_DDR_A14 MSS_DDR_ADDCMD1 6 Y U1 MSS_DDR_RAM_RST_N/ MSS_DDR_ADDCMD2 6 Y DDR_PLL0_OUT1 U2 MSS_DDR_BG0 MSS_DDR_ADDCMD2 6 Y U4 MSS_DDR_BG1 MSS_DDR_ADDCMD2 6 N U5 MSS_DDR_ACT_N MSS_DDR_ADDCMD2 6 Y U6 MSS_DDR_PARITY MSS_DDR_ADDCMD2 6 Y U7 MSS_DDR_A15 MSS_DDR_ADDCMD1 6 Y U9 MSS_DDR_A11 MSS_DDR_ADDCMD1 6 Y U10 MSS_DDR_A16 MSS_DDR_ADDCMD1 6 Y U11 MSS_DDR_BA0 MSS_DDR_ADDCMD1 6 Y V1 MSS_DDR_A0 MSS_DDR_ADDCMD0 6 Y V2 MSS_DDR_A1 MSS_DDR_ADDCMD0 6 Y V3 MSS_DDR_ODT0 MSS_DDR_ADDCMD2 6 Y V4 MSS_DDR_CKE0 MSS_DDR_ADDCMD2 6 Y V6 MSS_DDR_ALERT_N MSS_DDR_ADDCMD2 6 Y V7 MSS_DDR_A12 MSS_DDR_ADDCMD1 6 Y V8 MSS_DDR_A13 MSS_DDR_ADDCMD1 6 Y V9 MSS_DDR_A10 MSS_DDR_ADDCMD1 6 Y V11 MSS_DDR3_WE_N MSS_DDR_ADDCMD1 6 N W1 MSS_DDR_A3 MSS_DDR_ADDCMD0 6 Y W3 MSS_DDR_A4 MSS_DDR_ADDCMD0 6 Y W4 MSS_DDR_A5 MSS_DDR_ADDCMD0 6 Y W5 MSS_DDR_A6 MSS_DDR_ADDCMD0 6 Y W6 MSS_DDR_A8 MSS_DDR_ADDCMD0 6 Y W8 MSS_DDR_CK1/ MSS_DDR_ADDCMD1 6 N DDR_PLL0_OUT0 W9 MSS_DDR_CK_N1 MSS_DDR_ADDCMD1 6 N W10 MSS_DDR_BA1 MSS_DDR_ADDCMD1 6 Y W11 MSS_DDR_DM4 MSS_DDR_ECC 6 N Y1 MSS_DDR_A2 MSS_DDR_ADDCMD0 6 Y Y2 MSS_DDR_CK_N0 MSS_DDR_ADDCMD0 6 Y Y3 MSS_DDR_CK0/ MSS_DDR_ADDCMD0 6 Y DDR_PLL0_OUT0 Y5 MSS_DDR_A9 MSS_DDR_ADDCMD0 6 Y Y6 MSS_DDR_A7 MSS_DDR_ADDCMD0 6 Y Y7 MSS_DDR_DQS_P4 MSS_DDR_ECC 6 N Y8 MSS_DDR_DQS_N4 MSS_DDR_ECC 6 N Y10 MSS_DDR_VREF_IN N/A 6 N Y11 MSS_DDR_DQ35 MSS_DDR_ECC 6 N AA2 MSS_DDR_DQ4 MSS_DDR_DATA0 6 Y AA3 MSS_DDR_DQ3 MSS_DDR_DATA0 6 Y AA4 MSS_DDR_DQ2 MSS_DDR_DATA0 6 Y AA5 MSS_DDR_DQ11 MSS_DDR_DATA1 6 Y AA7 MSS_DDR_DQS_P1 MSS_DDR_DATA1 6 Y AA8 MSS_DDR_DQS_N1 MSS_DDR_DATA1 6 Y AA9 MSS_DDR_DQ14 MSS_DDR_DATA1 6 Y AA10 MSS_DDR_DQ34 MSS_DDR_ECC 6 N AB1 MSS_DDR_DQS_N0 MSS_DDR_DATA0 6 Y AB2 MSS_DDR_DQS_P0 MSS_DDR_DATA0 6 Y AB4 MSS_DDR_DQ1 MSS_DDR_DATA0 6 Y AB5 MSS_DDR_DQ0 MSS_DDR_DATA0 6 Y AB6 MSS_DDR_DQ12 MSS_DDR_DATA1 6 Y AB7 MSS_DDR_DQ8 MSS_DDR_DATA1 6 Y AB9 MSS_DDR_DQ15 MSS_DDR_DATA1 6 Y AB10 MSS_DDR_DQ32 MSS_DDR_ECC 6 N AB11 MSS_DDR_DQ33 MSS_DDR_ECC 6 N AC1 MSS_DDR_DQ6 MSS_DDR_DATA0 6 Y AC2 MSS_DDR_DQ7 MSS_DDR_DATA0 6 Y AC3 MSS_DDR_DM0 MSS_DDR_DATA0 6 Y AC4 MSS_DDR_DQ5 MSS_DDR_DATA0 6 Y AC6 MSS_DDR_DQ9 MSS_DDR_DATA1 6 Y AC7 MSS_DDR_DQ10 MSS_DDR_DATA1 6 Y AC8 MSS_DDR_DQ13 MSS_DDR_DATA1 6 Y AC9 MSS_DDR_DM1 MSS_DDR_DATA1 6 Y AD1 MSS_DDR_DQ23 MSS_DDR_DATA2 6 Y AD3 MSS_DDR_DQS_P2 MSS_DDR_DATA2 6 Y AD4 MSS_DDR_DQ19 MSS_DDR_DATA2 6 Y AD5 MSS_DDR_DQ18 MSS_DDR_DATA2 6 Y AD6 MSS_DDR_DQ16 MSS_DDR_DATA2 6 Y AE1 MSS_DDR_DM2 MSS_DDR_DATA2 6 Y AE2 MSS_DDR_DQ22 MSS_DDR_DATA2 6 Y AE3 MSS_DDR_DQS_N2 MSS_DDR_DATA2 6 Y AE5 MSS_DDR_DQ17 MSS_DDR_DATA2 6 Y AE6 MSS_DDR_DQ21 MSS_DDR_DATA2 6 Y AF1 MSS_DDR_DQ26 MSS_DDR_DATA3 6 Y AF2 MSS_DDR_DQS_P3 MSS_DDR_DATA3 6 Y AF3 MSS_DDR_DQ25 MSS_DDR_DATA3 6 Y AF4 MSS_DDR_DQ24 MSS_DDR_DATA3 6 Y AF5 MSS_DDR_DQ20 MSS_DDR_DATA2 6 Y AG1 MSS_DDR_DQ27 MSS_DDR_DATA3 6 Y AG2 MSS_DDR_DQS_N3 MSS_DDR_DATA3 6 Y AG4 MSS_DDR_DQ31 MSS_DDR_DATA3 6 Y AG5 MSS_DDR_DQ30 MSS_DDR_DATA3 6 Y AH2 MSS_DDR_DQ28 MSS_DDR_DATA3 6 Y AH3 MSS_DDR_DQ29 MSS_DDR_DATA3 6 Y AH4 MSS_DDR_DM3 MSS_DDR_DATA3 6 Y