DDR4 and CPU DDR4 Controller Pinout --------------------------------------- Initial Rev. 29-Dec-2022 Current Rev. 8-Mar-2023 CPU DDR4 Controller Pinout for the MPFS250T-FCVG784: ---------------------------------------------------- Microchip calls the CPU function in their FPGA/CPU the MSS, i.e. the Microprocessor SubSystem. The CPU's DDR Controller uses CPU HSIO pins in Bank 6. CPU aka MSS INTERFACE Bank 6 Pin Name Pin Number ------------- ----------- ADDR0 V1 ADDR1 V2 ADDR2 Y1 ADDR3 W1 ADDR4 W3 ADDR5 W4 ADDR6 W5 ADDR7 Y6 ADDR8 W6 ADDR9 Y5 ADDR10/AP V9 ADDR11 U9 ADDR12/BC_n V7 ADDR13 V8 ADDR14/WE_n T7 ADDR15/CAS_n U7 ADDR16/RAS_n U10 BA0 U11 BA1 W10 BG0 U2 BG1 U4 ODT0 V3 ODT1 T5 CLK0_P Y3 CLK0_N Y2 CKE0 V4 CLK1_P W8 CLK1_N W9 CKE1 T2 CS0_n T4 CS1_n T3 ALERT_N V6 * PARITY U6 * ACT_N U5 RESET# U1 TEN --- ** DQ0 AB5 DQ1 AB4 DQ2 AA4 DQ3 AA3 DQ4 AA2 DQ5 AC4 DQ6 AC1 DQ7 AC2 DQS0_P AB2 DQS0_N AB1 DQM0/DBI0 AC3 DQ0_ECC AB10 DQ8 AB7 DQ9 AC6 DQ10 AC7 DQ11 AA5 DQ12 AB6 DQ13 AC8 DQ14 AA9 DQ15 AB9 DQS1_P AA7 DQS1_N AA8 DQM1/DBI1 AC9 DQ1_ECC AB11 DQ16 AD6 DQ17 AE5 DQ18 AD5 DQ19 AD4 DQ20 AF5 DQ21 AE6 DQ22 AE2 DQ23 AD1 DQS2_P AD3 DQS2_N AE3 DQM2/DBI2 AE1 DQ2_ECC AA10 DQ24 AF4 DQ25 AF3 DQ26 AF1 DQ27 AG1 DQ28 AH2 DQ29 AH3 DQ30 AG5 DQ31 AG4 DQS3_P AF2 DQS3_N AG2 DQM3/DBI3 AH4 DQ3_ECC Y11 DQM_ECC/DBI_ECC W11 DQSP_ECC Y7 DQSN_ECC Y8 Notes about the CPU DDR4 Controller pinout on the MPFS250T FCVG784: - * The ALERT_N and PARITY signals are not listed in the MSS DDR4 tab of the pin table for the MPFS250T-FCVG784. These 2 signals are listed under the tab for the overall pins list MPFS250T-FCVG784. - ** So far I have not found a pin for TEN or TEN/EVENT_N in the MSS Bank 6 DDR interface. When the TEN pin on the memory chip is HI (>80% of the 1V2 VDD) it Enables the Test Mode. - What is: DQ0_ECC, DQ1_ECC, DQ2_ECC, DQ3_ECC DQM_ECC/DBI_ECC DQSP_ECC, DQSN_ECC The CPU's DDR Controller supports ECC and thus all of the ECC pins of unknown function listed just above. See section 4.11 of the "PolarFire SoC FPGA MSS Technical Reference Manual" for information about the CPU's DDR Controller. There are clearly some mistakes in what they have written in this section. There are clearly some un-answered questions on our part about how to use the MSS DDR4 Controller and what it can actually do. Micron MT40A1G16: ------------------ Pins in Physical Pin Layout Order: ---------------------------------- Pin Function Number -------- ------ VDDQ A1 VSSQ A2 DQ8 A3 UDQS_c A7 VSSQ A8 VDDQ A9 VPP B1 VSS B2 VDD B3 UDQS_t B7 DQ9 B8 VDD B9 VDDQ C1 DQ12 C2 DQ10 C3 DQ11 C7 DQ13 C8 VSSQ C9 VDD D1 VSSQ D2 DQ14 D3 DQ15 D7 VSSQ D8 VDDQ D9 VSS E1 NF/UDM_n/UDBI_n E2 VSSQ E3 NF/LDM_n/LDBI_n E7 VSSQ E8 VSS E9 VSSQ F1 VDDQ F2 LDQS_c F3 DQ1 F7 VDDQ F8 ZQ F9 VDDQ G1 DQ0 G2 LDQS_t G3 VDD G7 VSS G8 VDDQ G9 VSSQ H1 DQ4 H2 DQ2 H3 DQ3 H7 DQ5 H8 VSSQ H9 VDD J1 VDDQ J2 DQ6 J3 DQ7 J7 VDDQ J8 VDD J9 VSS K1 CKE K2 ODT K3 CK_t K7 CK_c K8 VSS K9 VDD L1 WE_n/A14 L2 ACT_n L3 CS_n L7 RAS_n/A16 L8 VDD L9 VREFCA M1 BG0 M2 A10/AP M3 A12/BC_n M7 CAS_n/A15 M8 VSS M9 VSS N1 BA0 N2 A4 N3 A3 N7 BA1 N8 TEN N9 RESET_n P1 A6 P2 A0 P3 A1 P7 A5 P8 ALERT_n P9 VDD R1 A8 R2 A2 R3 A9 R7 A7 R8 VPP R9 VSS T1 A11 T2 PAR T3 NF/NC T7 A13 T8 VDD T9 Now the pins sorted into a Function order: ------------------------------------------ Pin Function Number -------- ------ A0 P3 A1 P7 A2 R3 A3 N7 A4 N3 A5 P8 A6 P2 A7 R8 A8 R2 A9 R7 A10/AP M3 A11 T2 A12/BC_n M7 A13 T8 WE_n/A14 L2 CAS_n/A15 M8 RAS_n/A16 L8 BA0 N2 BA1 N8 BG0 M2 ODT K3 CK_t K7 CK_c K8 CKE K2 CS_n L7 ALERT_n P9 NF/LDM_n/LDBI_n E7 NF/UDM_n/UDBI_n E2 PAR T3 ACT_n L3 RESET_n P1 ZQ F9 TEN N9 DQ0 G2 DQ1 F7 DQ2 H3 DQ3 H7 DQ4 H2 DQ5 H8 DQ6 J3 DQ7 J7 LDQS_t G3 LDQS_c F3 DQ8 A3 DQ9 B8 DQ10 C3 DQ11 C7 DQ12 C2 DQ13 C8 DQ14 D3 DQ15 D7 UDQS_t B7 UDQS_c A7 VDD B3 VDD B9 VDD D1 VDD G7 VDD J1 VDD J9 VDD L1 VDD L9 VDD R1 VDD T9 VDDQ A1 VDDQ A9 VDDQ C1 VDDQ D9 VDDQ F2 VDDQ F8 VDDQ G1 VDDQ G9 VDDQ J2 VDDQ J8 VPP B1 VPP R9 VREFCA M1 VSS B2 VSS E1 VSS E9 VSS G8 VSS K1 VSS K9 VSS M9 VSS N1 VSS T1 VSSQ A2 VSSQ A8 VSSQ C9 VSSQ D2 VSSQ D8 VSSQ E3 VSSQ E8 VSSQ F1 VSSQ H1 VSSQ H9 NF/NC T7 Deffinition of the Pins from Micron: ------------------------------------ A[17:0] Input Address inputs: Provide the row address for ACTIVATE commands and the column address for READ/WRITE commands to select one location out of the memory array in the respective bank. (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, RAS_n/A16 have additional functions, see individual entries in this table.) The address inputs also provide the op-code during the MODE REGISTER SET command. A16 is used on some 8Gb and 16Gb parts. A17 connection is part-number specific; Contact vendor for more information. A10/AP Input Auto precharge: A10 is sampled during READ and WRITE commands to determine whether auto precharge should be performed to the accessed bank after a READ or WRITE operation. (HIGH = auto precharge; LOW = no auto precharge.) A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by the bank group and bank addresses. A12/BC_n Input Burst chop: A12/BC_n is sampled during READ and WRITE commands to determine if burst chop (on-the-fly) will be performed. (HIGH = no burst chop; LOW = burst chopped). See the Command Truth Table. ACT_n Input Command input: ACT_n indicates an ACTIVATE command. When ACT_n (along with CS_n) is LOW, the input pins RAS_n/A16, CAS_n/A15, and WE_n/A14 are treated as row address inputs for the ACTIVATE command. When ACT_n is HIGH (along with CS_n LOW), the input pins RAS_n/ A16, CAS_n/A15, and WE_n/A14 are treated as normal commands that use the RAS_n, CAS_n, and WE_n signals. See the Command Truth Table. BA[1:0] Input Bank address inputs: Define the bank (within a bank group) to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. Also determines which mode register is to be accessed during a MODE REGISTER SET command. BG[1:0] Input Bank group address inputs: Define the bank group to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. Also determines which mode register is to be accessed during a MODE REGISTER SET command. BG[1:0] are used in the x4 and x8 configurations. BG1 is not used in the x16 configuration. C0/CKE1, C1/CS1_n, C2/ODT1 Input Stack address inputs: These inputs are used only when devices are stacked; that is, they are used in 2H, 4H, and 8H stacks for x4 and x8 configurations (these pins are not used in the x16 configuration, and are N C on the x4/x8 SDP). DDR4 will support a traditional DDP package, which uses these three signals for control of the second die (CS1_n, CK E1, ODT1). DDR4 is not expected to support a traditional QDP package. For all other stack configurations, such as a 4H or 8H, it is assumed to be a single-load (master/slave) type of configuration where C0, C1, and C2 are used as chip ID selects in conjunction w ith a single CS_n, CK E, and ODT signal. CK_t, CK_c Input Clock: Differential clock inputs. All address, command, and control input signals are sampled on the crossing of the positive edge of CK_t and the negative edge of CK_c. CKE Input Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals, device input buffers, and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is asynchronous for self refresh exit, however, timing parameters such as t XS are still calculated from the first rising clock edge where CKE HIGH satisfies t IS. After V REFCA has become stable during the power-on and initialization sequence, it must be maintained during all operations (including SELF REFRESH). CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK_t, CK_c, ODT, RESET_n, and CKE) are disabled during power-down. Input buffers (excluding CKE and RESET_n) are disabled during self refresh. CS_n Input Chip select: All commands are masked when CS_n is registered HIGH. CS_n provides for external rank selection on systems with multiple ranks. CS_n is considered part of the command code. DM_n, UDM_n, LDM_n Input Input data mask: DM_n is an input mask signal for write data. Input data is masked when DM is sampled LOW coincident with that input data during a write access. DM is sampled on both edges of DQS. DM is not supported on x4 configurations. The UDM_n and LDM_n pins are used in the x16 configuration: UDM_n is associated with DQ[15:8]; LDM_n is associated with DQ[7:0]. The DM, DBI, and TDQS functions are enabled by mode register settings. See the Data Mask section. ODT Input On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR4 SDRAM. When enabled, ODT (Rtt) is applied only to each DQ, DQS_t, DQS_c, DM_n/DBI_n/TDQS_t, and TDQS_c signal for the x4 and x8 configurations (when the TDQS function is enabled via mode register). For the x16 configuration, Rtt is applied to each DQ, UDQS_t, UDQS_c, LDQS_t, LDQS_c, UDM_n, and LDM_n signal. The ODT pin will be ignored if the mode registers are programmed to disable Rtt. PAR Input Parity for command and address: This function can be enabled or disabled via the mode register. When enabled, the parity signal covers all command and address inputs, including ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, A[17:0], A10/AP, A12/BC_n, BA[1:0], and BG[1:0] with C0, C1, and C2 on 3DS only devices. Control pins NOT covered by the parity signal are CS_n, CK E, and ODT. Unused address pins that are density and configuration specific should be treated internally as 0s by the DRAM parity logic. Command and address inputs will have parity check performed when commands are latched via the rising edge of CK_t and when CS_n is LOW. RAS_n/A16, CAS_n/A15, WE_n/A14 Input Command inputs: RAS_n/A16, CAS_n/A15, and WE_n/A14 (along with CS_n and ACT_n) define the command and/or address being entered. See the ACT_n description in this table. RESET_n Input Active LOW asynchronous reset: Reset is active when RESET_n is LOW, and inactive when RESET_n is HIGH. RESET_n must be HIGH during normal operation. RESET_n is a CMOS rail-to-rail signal with DC HIGH and LOW at 80% and 20% of V DD (960 mV for DC HIGH and 240 mV for DC LOW). TEN Input Connectivity test mode: TEN is active when HIGH and inactive when LOW. TEN must be LOW during normal operation. TEN is a CMOS rail-to-rail signal with DC HIGH and LOW at 80% and 20% of V DD (960mV for DC HIGH and 240mV for DC LOW). On Micron 3DS devices, connectivity test mode is not supported and the TEN pin should be considered NF maintained LOW at all times. DQ I/O Data input/output: Bidirectional data bus. DQ represents DQ[3:0], DQ[7:0], and DQ[15:0] for the x4, x8, and x16 configurations, respectively. If write CRC is enabled via mode register, the write CRC code is added at the end of data burst. Any one or all of DQ0, DQ1, DQ2, and DQ3 may be used to monitor the internal Vref level during test via mode register setting MR[4] A[4] = HIGH, training times change when enabled. During this mode, the Rtt value should be set to High-Z. This measurement is for verification purposes and is NOT an external voltage supply pin. DBI_n, UDBI_n, LDBI_n I/O DBI input/output: Data bus inversion. DBI_n is an input/output signal used for data bus inversion in the x8 configuration. UDBI_n and LDBI_n are used in the x16 configuration; UDBI_n is associated with DQ[15:8], and LDBI_n is associated with DQ[7:0]. The DBI feature is not supported on the x4 configuration. DBI is not supported for 3DS devices and should be disabled in MR5. DBI can be configured for both READ (output) and WRITE (input) operations depending on the mode register settings. The DM, DBI, and TDQS functions are enabled by mode register settings. See the Data Bus Inversion section. DQS_t, DQS_c, UDQS_t, UDQS_c, LDQS_t, LDQS_c I/O Data strobe: Output with READ data, input with WRITE data. Edge-aligned with READ data, centered-aligned with WRITE data. For the x16, LDQS corresponds to the data on DQ[7:0]; UDQS corresponds to the data on DQ[15:8]. For the x4 and x8 configurations, DQS corresponds to the data on DQ[3:0] and DQ[7:0], re spectively. DDR4 SDRAM supports a differential data strobe only and does not support a single-ended data strobe. ALERT_n Output Alert output: This signal allows the DRAM to indicate to the system's memory controller that a specific alert or event has occurred. Alerts will include the command/address parity error and the CRC data error when either of these functions is enabled in the mode register. TDQS_t, TDQS_c Output Termination data strobe: TDQS_t and TDQS_c are used by x8 DRAMs only. When enabled via the mode register, the DRAM will enable the same Rtt termination resistance on TDQS_t and TDQS_c that is applied to DQS_t and DQS_c. When the TDQS function is disabled via the mode register, the DM/TDQS_t pin will provide the DATA MASK (DM) function, and the TDQS_c pin is not used. The TDQS function must be disabled in the mode register for both the x4 and x16 configurations. The DM function is supported only in x8 and x16 configurations. VDD Supply Power supply: 1.200V +-0.060V VDDQ Supply DQ power supply: 1.200V +-0.060V VPP Supply DRAM activating power supply: 2.500V -0.125V +0.250V VREFCA Supply Reference voltage for: control, command, and address pins. VSS Supply Ground. VSSQ Supply DQ ground. ZQ Reference Reference ball for ZQ calibration: This ball is tied to an external 240 Ohm resistor (RZQ), which is tied to V SSQ. NC No Connect: No internal electrical connection is present. NF No Function: Internal connection is present but has no function.