DDR4 and FPGA Fabric DDR Controller Pinout -------------------------------------------- Initial Rev. 20-Dec-2022 Current Rev. 29-Dec-2022 FPGA Fabric DDR Controller Pinout for the MPFS250T-FCVG784: ----------------------------------------------------------- DDR4 Interface Package Ball INTERFACE_PIN NORTH_NE NORTH_NW ------------- -------- -------- A[0] AG28 AH6 A[1] Y22 AD8 A[2] AC26 AC11 A[3] Y23 AE7 A[4] AE26 AH7 A[5] AC27 AC12 A[6] AG27 AF8 A[7] AC22 AC13 A[8] Y21 AG11 A[9] AC28 AG6 A[10] AE25 AH8 A[11] W21 AB12 A[12] AA22 AG9 A[13] AB22 AD11 WE_N AF25 AG12 CAS_N AF28 AE10 RAS_N AF27 AA12 BA[0] AD24 AF10 BA[1] AD28 AD9 BG[0] AF24 AH9 BG[1] AD26 AF9 ODT AH26 AF12 CK AB25 Y13 CK_N AB24 AA13 CKE AG26 AE12 CS_N AH27 AG10 ALERT_N/A17 W22 Y12 PAR_IN AC24 AD10 ACT_N AD25 AH11 RESET_N AD21 AE11 TEN/EVENT_N AA23 AE8 DQ[0] AG24 Y14 DQ[1] AE23 AA14 DQ[2] AF23 Y15 DQ[3] AH23 AA15 DQ[4] AH22 AB15 DQ[5] AG21 AB16 DQ[6] AH21 W17 DQ[7] AF22 Y17 DQS[0] AE21 Y16 DQS_N[0] AE22 W15 DM_N[0] AG22 AA17 DQ[8] AG20 AD14 DQ[9] AD19 AD13 DQ[10] AC19 AD15 DQ[11] AG19 AE15 DQ[12] AF19 AE13 DQ[13] AH19 AF13 DQ[14] AH18 AH13 DQ[15] AF18 AH14 DQS[1] AE20 AF14 DQS_N[1] AD20 AG14 DM_N[1] AE18 AF15 DQ[16] AC21 AC16 DQ[17] AB21 AC17 DQ[18] Y20 AG16 DQ[19] W20 AH16 DQ[20] Y19 AG17 DQ[21] W19 AH17 DQ[22] AA19 AD18 DQ[23] AB19 AC18 DQS[2] AB20 AE17 DQS_N[2] AA20 AF17 DM_N[2] AA18 AD16 DQ[24] AE16 Y18 DQ[25] AD16 AA18 DQ[26] AC18 AB19 DQ[27] AD18 AA19 DQ[28] AH17 W19 DQ[29] AG17 Y19 DQ[30] AH16 W20 DQ[31] AG16 Y20 DQS[3] AE17 AB20 DQS_N[3] AF17 AA20 DM_N[3] AC17 AB21 DQ[32] AG15 AF18 DQ[33] AF15 AH18 DQ[34] AH14 AH19 DQ[35] AH13 AF19 DQ[36] AF13 AG19 DQ[37] AE13 AC19 DQ[38] AE15 AD19 DQ[39] AD15 AF20 DQS[4] AF14 AE20 DQS_N[4] AG14 AD20 DM_N[4] AD13 AG20 DQ[40] AB17 AG22 DQ[41] AA17 AF22 DQ[42] Y17 AH21 DQ[43] W17 AG21 DQ[44] AB16 AH23 DQ[45] AB15 AF23 DQ[46] AA15 AE23 DQ[47] Y15 AH24 DQS[5] Y16 AE21 DQS_N[5] W15 AE22 DM_N[5] AA14 AG24 DQ[48] AH12 AG25 DQ[49] AH11 AG26 DQ[50] AF12 AH26 DQ[51] AG12 AH27 DQ[52] AE12 AF25 DQ[53] AE11 AF27 DQ[54] AH9 AF28 DQ[55] AG9 AE26 DQS[6] AG10 AG27 DQS_N[6] AG11 AG28 DM_N[6] AF10 AE25 DQ[56] AA12 Y21 DQ[57] Y12 W21 DQ[58] AC13 AA22 DQ[59] AB12 AB22 DQ[60] AC14 AC23 DQ[61] AB14 W22 DQ[62] AD11 Y22 DQ[63] AD10 AA23 DQS[7] Y13 AD21 DQS_N[7] AA13 AC22 DM_N[7] AC11 Y23 DQ[64] AD8 AD24 DQ[65] AH8 AC24 DQ[66] AH7 AD26 DQ[67] AF9 AD25 DQ[68] AF8 AB24 DQ[69] AG7 AD28 DQ[70] AF7 AC28 DQ[71] AE7 AC27 DQS[8] AG6 AE27 DQS_N[8] AH6 AE28 DM_N[8] AE8 AC26 I have looked at all of these pins in detail and I think that all of the NORTH_NE pin layout, everything except the D32:D71 is in Bank 0. In the NORTH_NE lauout I believe that all of D32:D71 (and its associated strobes and masks) is in Bank 8. I have looked at all of these pins in detail and I think that all of the NORTH_NW pin layout, everything except the D16:D71 is in Bank 8. In the NORTH_NW lauout I believe that all of D16:D71 (and its associated strobes and masks) is in Bank 0. DDR4 Interface Package Ball Option 2 -------- Option 2 Option 2 INTERFACE_PIN NORTH_NE NORTH_NW ------------- -------- -------- A[0] AG28 AH6 A[1] Y22 AD8 A[2] AC26 AC11 A[3] Y23 AE7 A[4] AE26 AH7 A[5] AC27 AC12 A[6] AG27 AF8 A[7] AC22 AC13 A[8] Y21 AG11 A[9] AC28 AG6 A[10] AE25 AH8 A[11] W21 AB12 A[12] AA22 AG9 A[13] AB22 AD11 WE_N AF25 AG12 CAS_N AF28 AE10 RAS_N AF27 AA12 BA[0] AD24 AF10 BA[1] AD28 AD9 BG[0] AF24 AH9 BG[1] AD26 AF9 ODT AH26 AF12 ODT1 AC23 AG7 CK AB25 Y13 CK_N AB24 AA13 CKE AG26 AE12 CK1 AE27 AB14 CK1_N AE28 AC14 CKE1 AG25 AH12 CS_N AH27 AG10 CS1_N AD23 AF7 ALERT_N/A17 W22 Y12 PAR_IN AC24 AD10 ACT_N AD25 AH11 RESET_N AD21 AE11 TEN/EVENT_N AA23 AE8 DQ[0] AG24 Y14 DQ[1] AE23 AA14 DQ[2] AF23 Y15 DQ[3] AH23 AA15 DQ[4] AH22 AB15 DQ[5] AG21 AB16 DQ[6] AH21 W17 DQ[7] AF22 Y17 DQS[0] AE21 Y16 DQS_N[0] AE22 W15 DM_N[0] AG22 AA17 DQ[8] AG20 AD14 DQ[9] AD19 AD13 DQ[10] AC19 AD15 DQ[11] AG19 AE15 DQ[12] AF19 AE13 DQ[13] AH19 AF13 DQ[14] AH18 AH13 DQ[15] AF18 AH14 DQS[1] AE20 AF14 DQS_N[1] AD20 AG14 DM_N[1] AE18 AF15 DQ[16] AC21 AC16 DQ[17] AB21 AC17 DQ[18] Y20 AG16 DQ[19] W20 AH16 DQ[20] Y19 AG17 DQ[21] W19 AH17 DQ[22] AA19 AD18 DQ[23] AB19 AC18 DQS[2] AB20 AE17 DQS_N[2] AA20 AF17 DM_N[2] AA18 AD16 DQ[24] AE16 Y18 DQ[25] AD16 AA18 DQ[26] AC18 AB19 DQ[27] AD18 AA19 DQ[28] AH17 W19 DQ[29] AG17 Y19 DQ[30] AH16 W20 DQ[31] AG16 Y20 DQS[3] AE17 AB20 DQS_N[3] AF17 AA20 DM_N[3] AC17 AB21 DQ[32] AG15 AF18 DQ[33] AF15 AH18 DQ[34] AH14 AH19 DQ[35] AH13 AF19 DQ[36] AF13 AG19 DQ[37] AE13 AC19 DQ[38] AE15 AD19 DQ[39] AD15 AF20 DQS[4] AF14 AE20 DQS_N[4] AG14 AD20 DM_N[4] AD13 AG20 DQ[40] AB17 AG22 DQ[41] AA17 AF22 DQ[42] Y17 AH21 DQ[43] W17 AG21 DQ[44] AB16 AH23 DQ[45] AB15 AF23 DQ[46] AA15 AE23 DQ[47] Y15 AH24 DQS[5] Y16 AE21 DQS_N[5] W15 AE22 DM_N[5] AA14 AG24 DQ[48] AH12 AG25 DQ[49] AH11 AG26 DQ[50] AF12 AH26 DQ[51] AG12 AH27 DQ[52] AE12 AF25 DQ[53] AE11 AF27 DQ[54] AH9 AF28 DQ[55] AG9 AE26 DQS[6] AG10 AG27 DQS_N[6] AG11 AG28 DM_N[6] AF10 AE25 DQ[56] AA12 Y21 DQ[57] Y12 W21 DQ[58] AC13 AA22 DQ[59] AB12 AB22 DQ[60] AC14 AC23 DQ[61] AB14 W22 DQ[62] AD11 Y22 DQ[63] AD10 AA23 DQS[7] Y13 AD21 DQS_N[7] AA13 AC22 DM_N[7] AC11 Y23 DQ[64] AD8 AD24 DQ[65] AH8 AC24 DQ[66] AH7 AD26 DQ[67] AF9 AD25 DQ[68] AF8 AB24 DQ[69] AG7 AD28 DQ[70] AF7 AC28 DQ[71] AE7 AC27 DQS[8] AG6 AE27 DQS_N[8] AH6 AE28 DM_N[8] AE8 AC26 I believe that the "Option 2" version of this pinout immediately above is just like the original version of the pinout starting at the top of this document except that it has: 2x ODT 2x CLKs and 2x Chip Selects i.e. I believe that Option 2 is just the Dual Rank setup. Micron MT40A1G16: ------------------ Pins in Physical Pin Layout Order: ---------------------------------- Pin Function Number -------- ------ VDDQ A1 VSSQ A2 DQ8 A3 UDQS_c A7 VSSQ A8 VDDQ A9 VPP B1 VSS B2 VDD B3 UDQS_t B7 DQ9 B8 VDD B9 VDDQ C1 DQ12 C2 DQ10 C3 DQ11 C7 DQ13 C8 VSSQ C9 VDD D1 VSSQ D2 DQ14 D3 DQ15 D7 VSSQ D8 VDDQ D9 VSS E1 NF/UDM_n/UDBI_n E2 VSSQ E3 NF/LDM_n/LDBI_n E7 VSSQ E8 VSS E9 VSSQ F1 VDDQ F2 LDQS_c F3 DQ1 F7 VDDQ F8 ZQ F9 VDDQ G1 DQ0 G2 LDQS_t G3 VDD G7 VSS G8 VDDQ G9 VSSQ H1 DQ4 H2 DQ2 H3 DQ3 H7 DQ5 H8 VSSQ H9 VDD J1 VDDQ J2 DQ6 J3 DQ7 J7 VDDQ J8 VDD J9 VSS K1 CKE K2 ODT K3 CK_t K7 CK_c K8 VSS K9 VDD L1 WE_n/A14 L2 ACT_n L3 CS_n L7 RAS_n/A16 L8 VDD L9 VREFCA M1 BG0 M2 A10/AP M3 A12/BC_n M7 CAS_n/A15 M8 VSS M9 VSS N1 BA0 N2 A4 N3 A3 N7 BA1 N8 TEN N9 RESET_n P1 A6 P2 A0 P3 A1 P7 A5 P8 ALERT_n P9 VDD R1 A8 R2 A2 R3 A9 R7 A7 R8 VPP R9 VSS T1 A11 T2 PAR T3 NF/NC T7 A13 T8 VDD T9 Now the pins sorted into a Function order: ------------------------------------------ Pin Function Number -------- ------ A0 P3 A1 P7 A2 R3 A3 N7 A4 N3 A5 P8 A6 P2 A7 R8 A8 R2 A9 R7 A10/AP M3 A11 T2 A12/BC_n M7 A13 T8 WE_n/A14 L2 CAS_n/A15 M8 RAS_n/A16 L8 BA0 N2 BA1 N8 BG0 M2 ODT K3 CK_t K7 CK_c K8 CKE K2 CS_n L7 ALERT_n P9 NF/LDM_n/LDBI_n E7 NF/UDM_n/UDBI_n E2 PAR T3 ACT_n L3 RESET_n P1 ZQ F9 TEN N9 DQ0 G2 DQ1 F7 DQ2 H3 DQ3 H7 DQ4 H2 DQ5 H8 DQ6 J3 DQ7 J7 LDQS_t G3 LDQS_c F3 DQ8 A3 DQ9 B8 DQ10 C3 DQ11 C7 DQ12 C2 DQ13 C8 DQ14 D3 DQ15 D7 UDQS_t B7 UDQS_c A7 VDD B3 VDD B9 VDD D1 VDD G7 VDD J1 VDD J9 VDD L1 VDD L9 VDD R1 VDD T9 VDDQ A1 VDDQ A9 VDDQ C1 VDDQ D9 VDDQ F2 VDDQ F8 VDDQ G1 VDDQ G9 VDDQ J2 VDDQ J8 VPP B1 VPP R9 VREFCA M1 VSS B2 VSS E1 VSS E9 VSS G8 VSS K1 VSS K9 VSS M9 VSS N1 VSS T1 VSSQ A2 VSSQ A8 VSSQ C9 VSSQ D2 VSSQ D8 VSSQ E3 VSSQ E8 VSSQ F1 VSSQ H1 VSSQ H9 NF/NC T7 Deffinition of the Pins from Micron: ------------------------------------ A[17:0] Input Address inputs: Provide the row address for ACTIVATE commands and the column address for READ/WRITE commands to select one location out of the memory array in the respective bank. (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, RAS_n/A16 have additional functions, see individual entries in this table.) The address inputs also provide the op-code during the MODE REGISTER SET command. A16 is used on some 8Gb and 16Gb parts. A17 connection is part-number specific; Contact vendor for more information. A10/AP Input Auto precharge: A10 is sampled during READ and WRITE commands to determine whether auto precharge should be performed to the accessed bank after a READ or WRITE operation. (HIGH = auto precharge; LOW = no auto precharge.) A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by the bank group and bank addresses. A12/BC_n Input Burst chop: A12/BC_n is sampled during READ and WRITE commands to determine if burst chop (on-the-fly) will be performed. (HIGH = no burst chop; LOW = burst chopped). See the Command Truth Table. ACT_n Input Command input: ACT_n indicates an ACTIVATE command. When ACT_n (along with CS_n) is LOW, the input pins RAS_n/A16, CAS_n/A15, and WE_n/A14 are treated as row address inputs for the ACTIVATE command. When ACT_n is HIGH (along with CS_n LOW), the input pins RAS_n/ A16, CAS_n/A15, and WE_n/A14 are treated as normal commands that use the RAS_n, CAS_n, and WE_n signals. See the Command Truth Table. BA[1:0] Input Bank address inputs: Define the bank (within a bank group) to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. Also determines which mode register is to be accessed during a MODE REGISTER SET command. BG[1:0] Input Bank group address inputs: Define the bank group to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. Also determines which mode register is to be accessed during a MODE REGISTER SET command. BG[1:0] are used in the x4 and x8 configurations. BG1 is not used in the x16 configuration. C0/CKE1, C1/CS1_n, C2/ODT1 Input Stack address inputs: These inputs are used only when devices are stacked; that is, they are used in 2H, 4H, and 8H stacks for x4 and x8 configurations (these pins are not used in the x16 configuration, and are N C on the x4/x8 SDP). DDR4 will support a traditional DDP package, which uses these three signals for control of the second die (CS1_n, CK E1, ODT1). DDR4 is not expected to support a traditional QDP package. For all other stack configurations, such as a 4H or 8H, it is assumed to be a single-load (master/slave) type of configuration where C0, C1, and C2 are used as chip ID selects in conjunction w ith a single CS_n, CK E, and ODT signal. CK_t, CK_c Input Clock: Differential clock inputs. All address, command, and control input signals are sampled on the crossing of the positive edge of CK_t and the negative edge of CK_c. CKE Input Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals, device input buffers, and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is asynchronous for self refresh exit, however, timing parameters such as t XS are still calculated from the first rising clock edge where CKE HIGH satisfies t IS. After V REFCA has become stable during the power-on and initialization sequence, it must be maintained during all operations (including SELF REFRESH). CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK_t, CK_c, ODT, RESET_n, and CKE) are disabled during power-down. Input buffers (excluding CKE and RESET_n) are disabled during self refresh. CS_n Input Chip select: All commands are masked when CS_n is registered HIGH. CS_n provides for external rank selection on systems with multiple ranks. CS_n is considered part of the command code. DM_n, UDM_n, LDM_n Input Input data mask: DM_n is an input mask signal for write data. Input data is masked when DM is sampled LOW coincident with that input data during a write access. DM is sampled on both edges of DQS. DM is not supported on x4 configurations. The UDM_n and LDM_n pins are used in the x16 configuration: UDM_n is associated with DQ[15:8]; LDM_n is associated with DQ[7:0]. The DM, DBI, and TDQS functions are enabled by mode register settings. See the Data Mask section. ODT Input On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR4 SDRAM. When enabled, ODT (Rtt) is applied only to each DQ, DQS_t, DQS_c, DM_n/DBI_n/TDQS_t, and TDQS_c signal for the x4 and x8 configurations (when the TDQS function is enabled via mode register). For the x16 configuration, Rtt is applied to each DQ, UDQS_t, UDQS_c, LDQS_t, LDQS_c, UDM_n, and LDM_n signal. The ODT pin will be ignored if the mode registers are programmed to disable Rtt. PAR Input Parity for command and address: This function can be enabled or disabled via the mode register. When enabled, the parity signal covers all command and address inputs, including ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, A[17:0], A10/AP, A12/BC_n, BA[1:0], and BG[1:0] with C0, C1, and C2 on 3DS only devices. Control pins NOT covered by the parity signal are CS_n, CK E, and ODT. Unused address pins that are density and configuration specific should be treated internally as 0s by the DRAM parity logic. Command and address inputs will have parity check performed when commands are latched via the rising edge of CK_t and when CS_n is LOW. RAS_n/A16, CAS_n/A15, WE_n/A14 Input Command inputs: RAS_n/A16, CAS_n/A15, and WE_n/A14 (along with CS_n and ACT_n) define the command and/or address being entered. See the ACT_n description in this table. RESET_n Input Active LOW asynchronous reset: Reset is active when RESET_n is LOW, and inactive when RESET_n is HIGH. RESET_n must be HIGH during normal operation. RESET_n is a CMOS rail-to-rail signal with DC HIGH and LOW at 80% and 20% of V DD (960 mV for DC HIGH and 240 mV for DC LOW). TEN Input Connectivity test mode: TEN is active when HIGH and inactive when LOW. TEN must be LOW during normal operation. TEN is a CMOS rail-to-rail signal with DC HIGH and LOW at 80% and 20% of V DD (960mV for DC HIGH and 240mV for DC LOW). On Micron 3DS devices, connectivity test mode is not supported and the TEN pin should be considered NF maintained LOW at all times. DQ I/O Data input/output: Bidirectional data bus. DQ represents DQ[3:0], DQ[7:0], and DQ[15:0] for the x4, x8, and x16 configurations, respectively. If write CRC is enabled via mode register, the write CRC code is added at the end of data burst. Any one or all of DQ0, DQ1, DQ2, and DQ3 may be used to monitor the internal Vref level during test via mode register setting MR[4] A[4] = HIGH, training times change when enabled. During this mode, the Rtt value should be set to High-Z. This measurement is for verification purposes and is NOT an external voltage supply pin. DBI_n, UDBI_n, LDBI_n I/O DBI input/output: Data bus inversion. DBI_n is an input/output signal used for data bus inversion in the x8 configuration. UDBI_n and LDBI_n are used in the x16 configuration; UDBI_n is associated with DQ[15:8], and LDBI_n is associated with DQ[7:0]. The DBI feature is not supported on the x4 configuration. DBI is not supported for 3DS devices and should be disabled in MR5. DBI can be configured for both READ (output) and WRITE (input) operations depending on the mode register settings. The DM, DBI, and TDQS functions are enabled by mode register settings. See the Data Bus Inversion section. DQS_t, DQS_c, UDQS_t, UDQS_c, LDQS_t, LDQS_c I/O Data strobe: Output with READ data, input with WRITE data. Edge-aligned with READ data, centered-aligned with WRITE data. For the x16, LDQS corresponds to the data on DQ[7:0]; UDQS corresponds to the data on DQ[15:8]. For the x4 and x8 configurations, DQS corresponds to the data on DQ[3:0] and DQ[7:0], re spectively. DDR4 SDRAM supports a differential data strobe only and does not support a single-ended data strobe. ALERT_n Output Alert output: This signal allows the DRAM to indicate to the system's memory controller that a specific alert or event has occurred. Alerts will include the command/address parity error and the CRC data error when either of these functions is enabled in the mode register. TDQS_t, TDQS_c Output Termination data strobe: TDQS_t and TDQS_c are used by x8 DRAMs only. When enabled via the mode register, the DRAM will enable the same Rtt termination resistance on TDQS_t and TDQS_c that is applied to DQS_t and DQS_c. When the TDQS function is disabled via the mode register, the DM/TDQS_t pin will provide the DATA MASK (DM) function, and the TDQS_c pin is not used. The TDQS function must be disabled in the mode register for both the x4 and x16 configurations. The DM function is supported only in x8 and x16 configurations. VDD Supply Power supply: 1.200V +-0.060V VDDQ Supply DQ power supply: 1.200V +-0.060V VPP Supply DRAM activating power supply: 2.500V -0.125V +0.250V VREFCA Supply Reference voltage for: control, command, and address pins. VSS Supply Ground. VSSQ Supply DQ ground. ZQ Reference Reference ball for ZQ calibration: This ball is tied to an external 240 Ohm resistor (RZQ), which is tied to V SSQ. NC No Connect: No internal electrical connection is present. NF No Function: Internal connection is present but has no function.