DDR4 FPGA Routing List ------------------------ Initial Rev. 10-Sept-2024 Current Rev. 10-Sept-2024 These CA Bus Signals are in physical order moving across the chip: FPGA DDR4 DDR4 Controller Pin Signal Layer Terminator Pin ---- ---------- ----- ---------- ---------- K2 CKE L3 R325 AH24 K3 ODT L4 R324 AG25 K7 CK L9 R326 AN28 K8 CK_B L10 R327 AM28 L2 WE_B L3 R323 AK26 L3 ACT_B L4 R322 AF27 L7 CS_B L9 R321 AG24 L8 RAS_B L10 R320 AH26 M2 BG0 L3 R319 AE26 M3 A10 L4 R318 AK27 M7 A12 L9 R317 AJ24 M8 CAS_B L10 R316 AK25 N2 BA0 L3 R315 AH27 N3 A4 L4 R314 AP26 N7 A3 L9 R313 AP28 N8 BA1 L10 R312 AG27 P2 A6 L3 R311 AM27 P3 A0 L4 R310 AM29 P7 A1 L9 R309 AN29 P8 A5 L10 R308 AP25 R2 A8 L3 R307 AJ27 R3 A2 L4 R306 AP29 R7 A9 L9 R305 AJ26 R8 A7 L10 R304 AM26 T2 A11 L3 R303 AL27 T3 PAR L4 R302 AF25 T7 --- -- ---- --- T8 A13 L9/10 R301 AJ25 Non-Clocked Signals Associated with the CA Bus: FPGA DDR4 DDR4 Controller Pin Signal Layer Terminator Pin ---- ---------- ----- ---------- ---------- N9 TEN ?? R332 PD AL25 P1 RESET_B ?? R331 PD AG26 P9 ALERT_B ?? R330 PU AM25