DDR4 Memory  Routing Details
         ----------------------------

                                    Initial Date:   7-Sept-2023
                                    Current Date:   8-Sept-2023


The purpose of this file is to hold the technical details
of routing the DDR4 Memories on the DK Board for both the
FPGA and for the CPU.


FPGA DDR4 Memory:
-----------------

The pinout used for routing the FPGA memory will use the
default "migrateable" Controller pinout as described in the
xlsx pin table for the mpft250t-fcvg784,  i.e.  I will NOT
use the "OPT-2" pinout for the FPGA's memory.

The DK FPGA memory setup will use the  North-NE  Anchor.

I will allow swapping in the 8 bit Data Lanes  (as they do
on their Demo Board)  but for now I'm not going to swap bit
zero in each lane because some brands of DDR4 seem to require
that the zero bit in each lane connects to the zero pin on
the memory device.

At the FPGA Controller end I will plan to use the Internal
Vref  as that is what the MicroChip datasheet seems to suggest
is the better option.  Internal Vref for the Controller seem
to be the way that they run their Demo Brds, but on the Demo
Brds they also include a Vref pin  in the HSIO bank  which they
run out to a jumper header.  At the header the put 100 nFd from
the Vref pin to Gnd  and  if you installed a jumper cap then
it connectes to the  0V6  reference supply.  By default the
jumper cap is Off.  See page 98 of the  "Memory Controller
User's Guide".

Does the mpft250t-fcvg784 use any  Gaurd  Pins in the I/O Bank
for the FPGA's DDR4 memory ?   I do not see any in the xlsx
pin table  but  they sure talk about Gaurd pins in other places
in their Memory Controller documentation.

List of unused pins in  Bank 0  in the DK's DDR4 memory setup:

    Y18
    AC16,  AC23
    AD23,  AD26    <--- Note AD26 is BG1 but BG1 is not used on DK
    AE27,  AE28
    AF20
    AG25
    AH24

Verified that of the 10 not used pins listed above, that
9 of them  (all but AD26)  are NOT in the xlsx pin table
for the default migratable FPGA DDR4 memory.

So we could have:

    8  pins that could be used as  Gaurd  pins
    1  Vref pin  that we do not plan on actually using
    1  pin, AD26, is part of the memory controller but
            not used in the DK board setup.


In total 74 pins are used for the FPGA DDR4 memory:

    30 pins for Address and Control
    22 pins for Data 0:15
    22 pins for Data 16:31.

One additional pin, AD26, is defined in xlsx pin table as
part of the default migratable FPGA Memory Controller which
has a total of 75 pins   when running at 32 data bit wide.



CPU DDR4 Memory:
----------------

The pinout in the xlsx pin table for the Bank 6 CPU DDR4
memory is quite specific - with the exceptions:

   No pin is give for the  TEN  signal.

   No pin is given for the  PARITY  signal  but it is given
   as U6 in the overall pinout tab.

   No pin is given for the  ALERT_N  signal but it is given
   as V6 in the overall pinout tab.

Unused Pins in Bank 6:

    T2     CKE1
    T3      CS1
    T5     ODT1
    U4      BG1      <---- Part of the Controller but not used by DK
    V11    DDR3_WE_N
    W8      CK1
    W9      CK1_N
    W11     DM4
    Y7      DQS_P4
    Y8      DQS_N4
    Y10    VREF      <---- Shout take to a pad ?   Will use Internal Vref
    Y11    DQ35
   AA10    DQ34
   AB10    DQ32
   AB11    DQ33