DDR Memory  for the  CPU  (aka MSS)
      -------------------------------------


                                     Initial Rev.  17-Nov-2022
                                     Current Rev.   8-Mar-2023


This file describes the DDR Memory that is connected to the
CPU  (aka MSS)  of the MTFS250T-FCVG784  FPGA/CPU  on the
Disco-Kraken circuit board.

This is a  4 GByte  DDR4  memory that is made using two memory
chips that hold 16 Gbits each.  Each memory chip is 16 bits
wide by 1 G addresses.   The whole system provides 1 G
locations that each hold 32 bits of data.

This is a single  Rank  memory system.

This memory system does  not  have  Error Correcting Code,
i.e. does not have ECC.

The CPU's DDR Memory Controller uses Bank 6 for its I/O to
the memory chips.  The address and control bus from the DDR
Controller is routed "fly by" to both memory chips in parallel
and to the terminator resistors for this bus.  16 data bits
with their associated clock and control signals run between
the DDR Controller and just one or the other memory chip.

The memory chips are:  Micron  MT40A1G16.

Current list of big questions:

 - Why are the  Parity  and  Alert_B  signals missing from the
   MSS DDR4 tab of the  pin table .xlsx   (but listed in the
   overall pin list)  ???

 - Does section 3.11.14 of the MSS Technical Reference Manual
   officially approve this memory configuration in its Table
   3-51  and  3-52   ???

 - What do I do with the 15 un-used pins on the CPU's DDR4
   Memory Controller ???  e.g.

      The 7 ECC pins  ???

      The single MSS_DDR_VREF_IN pin ???