FPGA DDR4 Memory Default Pinout ----------------------------------- Rev. 7-Sept-2023 The first table is 100% direct from the MPFS250T-FCVG784 xlsx pinout tabel from 30-June-2023 from the DDR4 "Default Migratable" tab. The second table is just the first table cleaned up into rational columns. The third table is just the secont table put into pin order based on the NORTH-NE column and has dropped the signals for > 32 data lines. The forth short table just list the 5 additional DDR4 signals as the appear in the DDR4 "Optimized" tab of the MPFS250T-FCVG784 xlsx pinout tabel from 30-June-2023. These 5 signals are the only differences between "Default Migratable" and "Optimized". First Table - 100% from MicroChip xlsx Pin File: ------------------------------------------------ INTERFACE_PIN NORTH_NE NORTH_NW A[0] AG28 AH6 A[1] Y22 AD8 CK AB25 Y13 CK_N AB24 AA13 A[2] AC26 AC11 A[3] Y23 AE7 TEN/EVENT_N AA23 AE8 ALERT_N/A17 W22 Y12 A[4] AE26 AH7 A[5] AC27 AC12 A[6] AG27 AF8 A[7] AC22 AC13 A[8] Y21 AG11 A[9] AC28 AG6 A[10] AE25 AH8 A[11] W21 AB12 A[12] AA22 AG9 A[13] AB22 AD11 WE_N AF25 AG12 CAS_N AF28 AE10 RAS_N AF27 AA12 BA[0] AD24 AF10 BA[1] AD28 AD9 ACT_N AD25 AH11 BG[0] AF24 AH9 BG[1] AD26 AF9 CS_N AH27 AG10 CKE AG26 AE12 ODT AH26 AF12 RESET_N AD21 AE11 PAR_IN AC24 AD10 DQ[0] AG24 Y14 DQ[1] AE23 AA14 DQ[2] AF23 Y15 DQ[3] AH23 AA15 DQS[0] AE21 Y16 DQS_N[0] AE22 W15 DQ[4] AH22 AB15 DQ[5] AG21 AB16 DQ[6] AH21 W17 DQ[7] AF22 Y17 DM_N[0] AG22 AA17 DQ[8] AG20 AD14 DQ[9] AD19 AD13 DQ[10] AC19 AD15 DQ[11] AG19 AE15 DQS[1] AE20 AF14 DQS_N[1] AD20 AG14 DQ[12] AF19 AE13 DQ[13] AH19 AF13 DQ[14] AH18 AH13 DQ[15] AF18 AH14 DM_N[1] AE18 AF15 DQ[16] AC21 AC16 DQ[17] AB21 AC17 DQ[18] Y20 AG16 DQ[19] W20 AH16 DQS[2] AB20 AE17 DQS_N[2] AA20 AF17 DQ[20] Y19 AG17 DQ[21] W19 AH17 DQ[22] AA19 AD18 DQ[23] AB19 AC18 DM_N[2] AA18 AD16 DQ[24] AE16 Y18 DQ[25] AD16 AA18 DQ[26] AC18 AB19 DQ[27] AD18 AA19 DQS[3] AE17 AB20 DQS_N[3] AF17 AA20 DQ[28] AH17 W19 DQ[29] AG17 Y19 DQ[30] AH16 W20 DQ[31] AG16 Y20 DM_N[3] AC17 AB21 DQ[32] AG15 AF18 DQ[33] AF15 AH18 DQ[34] AH14 AH19 DQ[35] AH13 AF19 DQS[4] AF14 AE20 DQS_N[4] AG14 AD20 DQ[36] AF13 AG19 DQ[37] AE13 AC19 DQ[38] AE15 AD19 DQ[39] AD15 AF20 DM_N[4] AD13 AG20 DQ[40] AB17 AG22 DQ[41] AA17 AF22 DQ[42] Y17 AH21 DQ[43] W17 AG21 DQS[5] Y16 AE21 DQS_N[5] W15 AE22 DQ[44] AB16 AH23 DQ[45] AB15 AF23 DQ[46] AA15 AE23 DQ[47] Y15 AH24 DM_N[5] AA14 AG24 DQ[48] AH12 AG25 DQ[49] AH11 AG26 DQ[50] AF12 AH26 DQ[51] AG12 AH27 DQS[6] AG10 AG27 DQS_N[6] AG11 AG28 DQ[52] AE12 AF25 DQ[53] AE11 AF27 DQ[54] AH9 AF28 DQ[55] AG9 AE26 DM_N[6] AF10 AE25 DQ[56] AA12 Y21 DQ[57] Y12 W21 DQ[58] AC13 AA22 DQ[59] AB12 AB22 DQS[7] Y13 AD21 DQS_N[7] AA13 AC22 DQ[60] AC14 AC23 DQ[61] AB14 W22 DQ[62] AD11 Y22 DQ[63] AD10 AA23 DM_N[7] AC11 Y23 DQ[64] AD8 AD24 DQ[65] AH8 AC24 DQ[66] AH7 AD26 DQ[67] AF9 AD25 DQS[8] AG6 AE27 DQS_N[8] AH6 AE28 DQ[68] AF8 AB24 DQ[69] AG7 AD28 DQ[70] AF7 AC28 DQ[71] AE7 AC27 DM_N[8] AE8 AC26 Second Table - Now Rational Columns: ------------------------------------ INTERFACE_PIN NORTH_NE NORTH_NW A[0] AG28 AH6 A[1] Y22 AD8 CK AB25 Y13 CK_N AB24 AA13 A[2] AC26 AC11 A[3] Y23 AE7 TEN/EVENT_N AA23 AE8 ALERT_N/A17 W22 Y12 A[4] AE26 AH7 A[5] AC27 AC12 A[6] AG27 AF8 A[7] AC22 AC13 A[8] Y21 AG11 A[9] AC28 AG6 A[10] AE25 AH8 A[11] W21 AB12 A[12] AA22 AG9 A[13] AB22 AD11 WE_N AF25 AG12 CAS_N AF28 AE10 RAS_N AF27 AA12 BA[0] AD24 AF10 BA[1] AD28 AD9 ACT_N AD25 AH11 BG[0] AF24 AH9 BG[1] AD26 AF9 CS_N AH27 AG10 CKE AG26 AE12 ODT AH26 AF12 RESET_N AD21 AE11 PAR_IN AC24 AD10 DQ[0] AG24 Y14 DQ[1] AE23 AA14 DQ[2] AF23 Y15 DQ[3] AH23 AA15 DQS[0] AE21 Y16 DQS_N[0] AE22 W15 DQ[4] AH22 AB15 DQ[5] AG21 AB16 DQ[6] AH21 W17 DQ[7] AF22 Y17 DM_N[0] AG22 AA17 DQ[8] AG20 AD14 DQ[9] AD19 AD13 DQ[10] AC19 AD15 DQ[11] AG19 AE15 DQS[1] AE20 AF14 DQS_N[1] AD20 AG14 DQ[12] AF19 AE13 DQ[13] AH19 AF13 DQ[14] AH18 AH13 DQ[15] AF18 AH14 DM_N[1] AE18 AF15 DQ[16] AC21 AC16 DQ[17] AB21 AC17 DQ[18] Y20 AG16 DQ[19] W20 AH16 DQS[2] AB20 AE17 DQS_N[2] AA20 AF17 DQ[20] Y19 AG17 DQ[21] W19 AH17 DQ[22] AA19 AD18 DQ[23] AB19 AC18 DM_N[2] AA18 AD16 DQ[24] AE16 Y18 DQ[25] AD16 AA18 DQ[26] AC18 AB19 DQ[27] AD18 AA19 DQS[3] AE17 AB20 DQS_N[3] AF17 AA20 DQ[28] AH17 W19 DQ[29] AG17 Y19 DQ[30] AH16 W20 DQ[31] AG16 Y20 DM_N[3] AC17 AB21 DQ[32] AG15 AF18 DQ[33] AF15 AH18 DQ[34] AH14 AH19 DQ[35] AH13 AF19 DQS[4] AF14 AE20 DQS_N[4] AG14 AD20 DQ[36] AF13 AG19 DQ[37] AE13 AC19 DQ[38] AE15 AD19 DQ[39] AD15 AF20 DM_N[4] AD13 AG20 DQ[40] AB17 AG22 DQ[41] AA17 AF22 DQ[42] Y17 AH21 DQ[43] W17 AG21 DQS[5] Y16 AE21 DQS_N[5] W15 AE22 DQ[44] AB16 AH23 DQ[45] AB15 AF23 DQ[46] AA15 AE23 DQ[47] Y15 AH24 DM_N[5] AA14 AG24 DQ[48] AH12 AG25 DQ[49] AH11 AG26 DQ[50] AF12 AH26 DQ[51] AG12 AH27 DQS[6] AG10 AG27 DQS_N[6] AG11 AG28 DQ[52] AE12 AF25 DQ[53] AE11 AF27 DQ[54] AH9 AF28 DQ[55] AG9 AE26 DM_N[6] AF10 AE25 DQ[56] AA12 Y21 DQ[57] Y12 W21 DQ[58] AC13 AA22 DQ[59] AB12 AB22 DQS[7] Y13 AD21 DQS_N[7] AA13 AC22 DQ[60] AC14 AC23 DQ[61] AB14 W22 DQ[62] AD11 Y22 DQ[63] AD10 AA23 DM_N[7] AC11 Y23 DQ[64] AD8 AD24 DQ[65] AH8 AC24 DQ[66] AH7 AD26 DQ[67] AF9 AD25 DQS[8] AG6 AE27 DQS_N[8] AH6 AE28 DQ[68] AF8 AB24 DQ[69] AG7 AD28 DQ[70] AF7 AC28 DQ[71] AE7 AC27 DM_N[8] AE8 AC26 Third Table - Now in Pin Number Order and has dropped the signals for > 32 data lines Total of 75 pins listed for our use on DK: ------------------------------------------- NORTH_NE INTERFACE_PIN NORTH_NW W19 DQ[21] AH17 W20 DQ[19] AH16 W21 A[11] AB12 W22 ALERT_N/A17 Y12 Y19 DQ[20] AG17 Y20 DQ[18] AG16 Y21 A[8] AG11 Y22 A[1] AD8 Y23 A[3] AE7 AA18 DM_N[2] AD16 AA19 DQ[22] AD18 AA20 DQS_N[2] AF17 AA22 A[12] AG9 AA23 TEN/EVENT_N AE8 AB19 DQ[23] AC18 AB20 DQS[2] AE17 AB21 DQ[17] AC17 AB22 A[13] AD11 AB24 CK_N AA13 AB25 CK Y13 AC17 DM_N[3] AB21 AC18 DQ[26] AB19 AC19 DQ[10] AD15 AC21 DQ[16] AC16 AC22 A[7] AC13 AC24 PAR_IN AD10 AC26 A[2] AC11 AC27 A[5] AC12 AC28 A[9] AG6 AD16 DQ[25] AA18 AD18 DQ[27] AA19 AD19 DQ[9] AD13 AD20 DQS_N[1] AG14 AD21 RESET_N AE11 AD24 BA[0] AF10 AD25 ACT_N AH11 AD26 BG[1] AF9 AD28 BA[1] AD9 AE16 DQ[24] Y18 AE17 DQS[3] AB20 AE18 DM_N[1] AF15 AE20 DQS[1] AF14 AE21 DQS[0] Y16 AE22 DQS_N[0] W15 AE23 DQ[1] AA14 AE25 A[10] AH8 AE26 A[4] AH7 AF17 DQS_N[3] AA20 AF18 DQ[15] AH14 AF19 DQ[12] AE13 AF22 DQ[7] Y17 AF23 DQ[2] Y15 AF24 BG[0] AH9 AF25 WE_N AG12 AF27 RAS_N AA12 AF28 CAS_N AE10 AG16 DQ[31] Y20 AG17 DQ[29] Y19 AG19 DQ[11] AE15 AG20 DQ[8] AD14 AG21 DQ[5] AB16 AG22 DM_N[0] AA17 AG24 DQ[0] Y14 AG26 CKE AE12 AG27 A[6] AF8 AG28 A[0] AH6 AH16 DQ[30] W20 AH17 DQ[28] W19 AH18 DQ[14] AH13 AH19 DQ[13] AF13 AH21 DQ[6] W17 AH22 DQ[4] AB15 AH23 DQ[3] AA15 AH26 ODT AF12 AH27 CS_N AG10 Note that the following signal is in the above list #3 but is not used in the DK design: AD26 BG[1] AF9 Forth Table - this table shows the 5 additional signals that appear in the DDR4 "Optimized" tab of the MPFS250T-FCVG784 xlsx pinout tabel: ------------------------------------------------ INTERFACE_PIN NORTH_NE_OPT_2 NORTH_NW_OPT_2 CK1 AE27 AB14 CK1_N AE28 AC14 CKE1 AG25 AH12 CS1_N AD23 AF7 ODT1 AC23 AG7 So it looks like the "OPT_2" pin pin table provides a second Clock and Clock Enable, and a second Chip Select, and a second On Die Terminator control. Reading the Memory Controller User's Guide makes things even more confusing. This guide says that the normal default migratable pin arrangement has a maximun of: 127 signals, max data width of 64, and can NOT do ECC at max data width. This is for FCVG784 at the North-NE "anchor". The same guide says that for "OPT-2" that it has: 139 signals, max data width of 64, and can do ECC at max data width. I do not understand this but it seems likely that the CK1, CS1, ODT1 are to be used with data lines 64:71 i.e. the ECC bits I assume. The pins for the data lines 64:71 and their DQS, DQS_B, and DM_B are all defined in the normal default migratable pin table.