Bank #6 CPU DDR4 AB1 MSS_DDR_A0 AB2 MSS_DDR_A1 AE3 MSS_DDR_A2 AD1 MSS_DDR_A3 AA2 MSS_DDR_A4 AA3 MSS_DDR_A5 AB4 MSS_DDR_A6 AC3 MSS_DDR_A7 AA4 MSS_DDR_A8 AD3 MSS_DDR_A9 AC6 MSS_DDR_A10 AB5 MSS_DDR_A11 AB6 MSS_DDR_A12 AB7 MSS_DDR_A13 AD8 MSS_DDR_A14 AD9 MSS_DDR_A15 AC4 MSS_DDR_A16 AD4 MSS_DDR_BA0 AD5 MSS_DDR_BA1 AC12 MSS_DDR_BG0 AB11 MSS_DDR_ODT0 AC1 MSS_DDR_CK0/DDR_PLL0_OUT0 AC2 MSS_DDR_CK_N0 AC11 MSS_DDR_CKE0 AC14 MSS_DDR_CS0 AD10 MSS_DDR_ALERT_N AB9 MSS_DDR_PARITY AC9 MSS_DDR_ACT_N AB12 MSS_DDR_RAM_RST_N/DDR_PLL0_OUT1 AF8 MSS_DDR_DQ0 AF7 MSS_DDR_DQ1 AE8 MSS_DDR_DQ2 AE7 MSS_DDR_DQ3 AH7 MSS_DDR_DQ4 AH8 MSS_DDR_DQ5 AF5 MSS_DDR_DQ6 AF4 MSS_DDR_DQ7 AE6 MSS_DDR_DQS_P0 AE5 MSS_DDR_DQS_N0 AG7 MSS_DDR_DM0 AF3 MSS_DDR_DQ8 AF2 MSS_DDR_DQ9 AE2 MSS_DDR_DQ10 AE1 MSS_DDR_DQ11 AG1 MSS_DDR_DQ12 AH1 MSS_DDR_DQ13 AH3 MSS_DDR_DQ14 AJ3 MSS_DDR_DQ15 AG2 MSS_DDR_DQS_P1 AH2 MSS_DDR_DQS_N1 AJ1 MSS_DDR_DM1 AJ6 MSS_DDR_DQ16 AG5 MSS_DDR_DQ17 AH6 MSS_DDR_DQ18 AH4 MSS_DDR_DQ19 AG6 MSS_DDR_DQ20 AG4 MSS_DDR_DQ21 AK5 MSS_DDR_DQ22 AL5 MSS_DDR_DQ23 AJ4 MSS_DDR_DQS_P2 AJ5 MSS_DDR_DQS_N2 AK6 MSS_DDR_DM2 AK3 MSS_DDR_DQ24 AL3 MSS_DDR_DQ25 AK2 MSS_DDR_DQ26 AK1 MSS_DDR_DQ27 AL2 MSS_DDR_DQ28 AM1 MSS_DDR_DQ29 AM2 MSS_DDR_DQ30 AN2 MSS_DDR_DQ31 AL4 MSS_DDR_DQS_P3 AM4 MSS_DDR_DQS_N3 AN1 MSS_DDR_DM3 AE12 MSS_DDR_VREF_IN Not Used: AD6 MSS_DDR3_WE_N AD13 MSS_DDR_BG1 AB10 MSS_DDR_ODT1 AC8 MSS_DDR_CK_N1 AC7 MSS_DDR_CK1/DDR_PLL0_OUT0 AB14 MSS_DDR_CKE1 AC13 MSS_DDR_CS1 AE10 MSS_DDR_DQ32 AE11 MSS_DDR_DQ33 AG10 MSS_DDR_DQ34 AF10 MSS_DDR_DQ35 AG9 MSS_DDR_DQS_P4 AF9 MSS_DDR_DQS_N4 AD11 MSS_DDR_DM4