This section
provides information on the extpll Module Instance.
Each of the module registers is described below.
Register Lock Bits can
prevent the XCVR configuration registers from being overwritten by hosts that
have access to these registers. The lock bits can be managed using the
Configure Register Lock Bits utility in the Libero SoC.
The following registers can be locked.
·
EXTPLL_EXTPLL_CLK_SEL
·
EXTPLL_EXTPLL_CLKBUF
·
EXTPLL_EXTPLL_CTRL
·
EXTPLL_EXTPLL_DIV_1
·
EXTPLL_EXTPLL_DIV_2
·
EXTPLL_SOFT_RESET
Return to mpfs_ioscb_memmap_dri
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
RW |
32 |
0x0000 0000 |
0x000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
|
RW |
32 |
0x00CE 0009 |
0x008 |
|
RW |
32 |
0x0000 1F00 |
0x00C |
|
RW |
32 |
0x0014 0014 |
0x010 |
|
RW |
32 |
0x0100 0001 |
0x014 |
|
RW |
32 |
0x0064 0064 |
0x018 |
|
RW |
32 |
0x0000 0064 |
0x01C |
|
RW |
32 |
0x000A 0064 |
0x020 |
|
RW |
32 |
0x0101 000F |
0x024 |
|
RW |
32 |
0x0101 0101 |
0x028 |
|
RW |
32 |
0x0101 0101 |
0x02C |
|
RW |
32 |
0x0700 0001 |
0x030 |
|
RW |
32 |
0x0000 0000 |
0x034 |
|
RW |
32 |
0x0018 0014 |
0x038 |
|
RO |
32 |
0x0000 0000 |
0x03C |
|
RW |
32 |
0x0000 0055 |
0x040 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0204 4000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x0204 4004 |
|
RW |
32 |
0x00CE 0009 |
0x008 |
0x0204 4008 |
|
RW |
32 |
0x0000 1F00 |
0x00C |
0x0204 400C |
|
RW |
32 |
0x0014 0014 |
0x010 |
0x0204 4010 |
|
RW |
32 |
0x0100 0001 |
0x014 |
0x0204 4014 |
|
RW |
32 |
0x0064 0064 |
0x018 |
0x0204 4018 |
|
RW |
32 |
0x0000 0064 |
0x01C |
0x0204 401C |
|
RW |
32 |
0x000A 0064 |
0x020 |
0x0204 4020 |
|
RW |
32 |
0x0101 000F |
0x024 |
0x0204 4024 |
|
RW |
32 |
0x0101 0101 |
0x028 |
0x0204 4028 |
|
RW |
32 |
0x0101 0101 |
0x02C |
0x0204 402C |
|
RW |
32 |
0x0700 0001 |
0x030 |
0x0204 4030 |
|
RW |
32 |
0x0000 0000 |
0x034 |
0x0204 4034 |
|
RW |
32 |
0x0018 0014 |
0x038 |
0x0204 4038 |
|
RO |
32 |
0x0000 0000 |
0x03C |
0x0204 403C |
|
RW |
32 |
0x0000 0055 |
0x040 |
0x0204 4040 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0204 8000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x0204 8004 |
|
RW |
32 |
0x00CE 0009 |
0x008 |
0x0204 8008 |
|
RW |
32 |
0x0000 1F00 |
0x00C |
0x0204 800C |
|
RW |
32 |
0x0014 0014 |
0x010 |
0x0204 8010 |
|
RW |
32 |
0x0100 0001 |
0x014 |
0x0204 8014 |
|
RW |
32 |
0x0064 0064 |
0x018 |
0x0204 8018 |
|
RW |
32 |
0x0000 0064 |
0x01C |
0x0204 801C |
|
RW |
32 |
0x000A 0064 |
0x020 |
0x0204 8020 |
|
RW |
32 |
0x0101 000F |
0x024 |
0x0204 8024 |
|
RW |
32 |
0x0101 0101 |
0x028 |
0x0204 8028 |
|
RW |
32 |
0x0101 0101 |
0x02C |
0x0204 802C |
|
RW |
32 |
0x0700 0001 |
0x030 |
0x0204 8030 |
|
RW |
32 |
0x0000 0000 |
0x034 |
0x0204 8034 |
|
RW |
32 |
0x0018 0014 |
0x038 |
0x0204 8038 |
|
RO |
32 |
0x0000 0000 |
0x03C |
0x0204 803C |
|
RW |
32 |
0x0000 0055 |
0x040 |
0x0204 8040 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0401 0000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x0401 0004 |
|
RW |
32 |
0x00CE 0009 |
0x008 |
0x0401 0008 |
|
RW |
32 |
0x0000 1F00 |
0x00C |
0x0401 000C |
|
RW |
32 |
0x0014 0014 |
0x010 |
0x0401 0010 |
|
RW |
32 |
0x0100 0001 |
0x014 |
0x0401 0014 |
|
RW |
32 |
0x0064 0064 |
0x018 |
0x0401 0018 |
|
RW |
32 |
0x0000 0064 |
0x01C |
0x0401 001C |
|
RW |
32 |
0x000A 0064 |
0x020 |
0x0401 0020 |
|
RW |
32 |
0x0101 000F |
0x024 |
0x0401 0024 |
|
RW |
32 |
0x0101 0101 |
0x028 |
0x0401 0028 |
|
RW |
32 |
0x0101 0101 |
0x02C |
0x0401 002C |
|
RW |
32 |
0x0700 0001 |
0x030 |
0x0401 0030 |
|
RW |
32 |
0x0000 0000 |
0x034 |
0x0401 0034 |
|
RW |
32 |
0x0018 0014 |
0x038 |
0x0401 0038 |
|
RO |
32 |
0x0000 0000 |
0x03C |
0x0401 003C |
|
RW |
32 |
0x0000 0055 |
0x040 |
0x0401 0040 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0402 0000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x0402 0004 |
|
RW |
32 |
0x00CE 0009 |
0x008 |
0x0402 0008 |
|
RW |
32 |
0x0000 1F00 |
0x00C |
0x0402 000C |
|
RW |
32 |
0x0014 0014 |
0x010 |
0x0402 0010 |
|
RW |
32 |
0x0100 0001 |
0x014 |
0x0402 0014 |
|
RW |
32 |
0x0064 0064 |
0x018 |
0x0402 0018 |
|
RW |
32 |
0x0000 0064 |
0x01C |
0x0402 001C |
|
RW |
32 |
0x000A 0064 |
0x020 |
0x0402 0020 |
|
RW |
32 |
0x0101 000F |
0x024 |
0x0402 0024 |
|
RW |
32 |
0x0101 0101 |
0x028 |
0x0402 0028 |
|
RW |
32 |
0x0101 0101 |
0x02C |
0x0402 002C |
|
RW |
32 |
0x0700 0001 |
0x030 |
0x0402 0030 |
|
RW |
32 |
0x0000 0000 |
0x034 |
0x0402 0034 |
|
RW |
32 |
0x0018 0014 |
0x038 |
0x0402 0038 |
|
RO |
32 |
0x0000 0000 |
0x03C |
0x0402 003C |
|
RW |
32 |
0x0000 0055 |
0x040 |
0x0402 0040 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0404 0000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x0404 0004 |
|
RW |
32 |
0x00CE 0009 |
0x008 |
0x0404 0008 |
|
RW |
32 |
0x0000 1F00 |
0x00C |
0x0404 000C |
|
RW |
32 |
0x0014 0014 |
0x010 |
0x0404 0010 |
|
RW |
32 |
0x0100 0001 |
0x014 |
0x0404 0014 |
|
RW |
32 |
0x0064 0064 |
0x018 |
0x0404 0018 |
|
RW |
32 |
0x0000 0064 |
0x01C |
0x0404 001C |
|
RW |
32 |
0x000A 0064 |
0x020 |
0x0404 0020 |
|
RW |
32 |
0x0101 000F |
0x024 |
0x0404 0024 |
|
RW |
32 |
0x0101 0101 |
0x028 |
0x0404 0028 |
|
RW |
32 |
0x0101 0101 |
0x02C |
0x0404 002C |
|
RW |
32 |
0x0700 0001 |
0x030 |
0x0404 0030 |
|
RW |
32 |
0x0000 0000 |
0x034 |
0x0404 0034 |
|
RW |
32 |
0x0018 0014 |
0x038 |
0x0404 0038 |
|
RO |
32 |
0x0000 0000 |
0x03C |
0x0404 003C |
|
RW |
32 |
0x0000 0055 |
0x040 |
0x0404 0040 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0408 0000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x0408 0004 |
|
RW |
32 |
0x00CE 0009 |
0x008 |
0x0408 0008 |
|
RW |
32 |
0x0000 1F00 |
0x00C |
0x0408 000C |
|
RW |
32 |
0x0014 0014 |
0x010 |
0x0408 0010 |
|
RW |
32 |
0x0100 0001 |
0x014 |
0x0408 0014 |
|
RW |
32 |
0x0064 0064 |
0x018 |
0x0408 0018 |
|
RW |
32 |
0x0000 0064 |
0x01C |
0x0408 001C |
|
RW |
32 |
0x000A 0064 |
0x020 |
0x0408 0020 |
|
RW |
32 |
0x0101 000F |
0x024 |
0x0408 0024 |
|
RW |
32 |
0x0101 0101 |
0x028 |
0x0408 0028 |
|
RW |
32 |
0x0101 0101 |
0x02C |
0x0408 002C |
|
RW |
32 |
0x0700 0001 |
0x030 |
0x0408 0030 |
|
RW |
32 |
0x0000 0000 |
0x034 |
0x0408 0034 |
|
RW |
32 |
0x0018 0014 |
0x038 |
0x0408 0038 |
|
RO |
32 |
0x0000 0000 |
0x03C |
0x0408 003C |
|
RW |
32 |
0x0000 0055 |
0x040 |
0x0408 0040 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0410 0000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x0410 0004 |
|
RW |
32 |
0x00CE 0009 |
0x008 |
0x0410 0008 |
|
RW |
32 |
0x0000 1F00 |
0x00C |
0x0410 000C |
|
RW |
32 |
0x0014 0014 |
0x010 |
0x0410 0010 |
|
RW |
32 |
0x0100 0001 |
0x014 |
0x0410 0014 |
|
RW |
32 |
0x0064 0064 |
0x018 |
0x0410 0018 |
|
RW |
32 |
0x0000 0064 |
0x01C |
0x0410 001C |
|
RW |
32 |
0x000A 0064 |
0x020 |
0x0410 0020 |
|
RW |
32 |
0x0101 000F |
0x024 |
0x0410 0024 |
|
RW |
32 |
0x0101 0101 |
0x028 |
0x0410 0028 |
|
RW |
32 |
0x0101 0101 |
0x02C |
0x0410 002C |
|
RW |
32 |
0x0700 0001 |
0x030 |
0x0410 0030 |
|
RW |
32 |
0x0000 0000 |
0x034 |
0x0410 0034 |
|
RW |
32 |
0x0018 0014 |
0x038 |
0x0410 0038 |
|
RO |
32 |
0x0000 0000 |
0x03C |
0x0410 003C |
|
RW |
32 |
0x0000 0055 |
0x040 |
0x0410 0040 |
Address offset |
0x000 |
||
Physical address |
0x0410 0000 |
Instance |
serdes_35_ext |
0x0408 0000 |
serdes_24_ext |
||
0x0401 0000 |
serdes_01_ext |
||
0x0204 4000 |
pciess_quad_pll0 |
||
0x0404 0000 |
serdes_02_ext |
||
0x0402 0000 |
serdes_13_ext |
||
0x0204 8000 |
pciess_quad_pll1 |
||
Description |
Compulsory register for all SCB slaves, facilitating
global soft reset. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:16 |
BLOCKID |
This returns the block type and chip location. |
RO |
0x0000 |
|
|
|
Read 0x0000 |
[block_address_extpll] Indicates
the Block chip location. |
|
|
15:9 |
Reserved |
|
RO |
0x00 |
|
8 |
PERIPH |
This asserts functional reset of the peripheral block. It is
asserted and left asserted at power-up. |
WO |
0 |
|
|
|
Write 0 |
[scb_periph_not_in_soft_reset_extpll]
Reset not asserted. |
|
|
|
|
Write 1 |
[scb_periph_reset_extpll] SCB
registers reset pulsed. |
|
|
7:2 |
Reserved |
|
RO |
0x00 |
|
1 |
V_MAP |
Resets all the volatile register bits. |
WO |
0 |
|
|
|
Write 0 |
[scb_v_regs_not_in_soft_reset_extpll]
Reset not asserted. |
|
|
|
|
Write 1 |
[scb_v_regs_reset_extpll] SCB
Volatile reset (i.e. RW-X registers are reset) |
|
|
0 |
NV_MAP |
Resets all the non-volatile register bits (e.g. RW-P
bits). |
WO |
0 |
|
|
|
Write 0 |
[scb_nv_regs_not_in_soft_reset_extpll]
Reset not asserted. |
|
|
|
|
Write 1 |
[scb_nv_regs_reset_extpll] SCB
Non-Volatile reset (i.e. RW-P registers are reset. |
|
Address offset |
0x004 |
||
Physical address |
0x0410 0004 |
Instance |
serdes_35_ext |
0x0408 0004 |
serdes_24_ext |
||
0x0401 0004 |
serdes_01_ext |
||
0x0204 4004 |
pciess_quad_pll0 |
||
0x0404 0004 |
serdes_02_ext |
||
0x0402 0004 |
serdes_13_ext |
||
0x0204 8004 |
pciess_quad_pll1 |
||
Description |
External TX PLL Clock Buffer Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:17 |
Reserved |
|
RO |
0x0000 |
|
16 |
EXTPLL_CLKBUF_EN_APAD |
This register is NOT for customers. Please mark this
register as RESERVED. |
RW |
0 |
|
|
|
0 |
[extpll_dualclk1_analog_output_disabled] Disables allowing
EXT PLL Dual Clock 1 input to be used as an analoog
output |
|
|
|
|
1 |
[extpll_dualclk1_analog_output_enabled] enableds allowing EXT PLL Dual Clock 1 input to be used
as an analoog output |
|
|
15:14 |
Reserved |
|
RO |
0x0 |
|
13 |
EXTPLL_CLKBUF_EN_PULLUP |
Enable a pullup on both Dual Reference Clock inputs. |
RW |
0 |
|
|
|
0 |
[extpll_clkbuf_pullup_disabled]
Disables pullup on both EXT PLL Dual Reference Clock inputs. |
|
|
|
|
1 |
[extpll_clkbuf_pullup_enabled]
Enables pullup on both EXT PLL Dual Reference Clock inputs. |
|
|
12 |
EXTPLL_CLKBUF_EN_UDRIVE_N |
Enable Underdrive capability on CMOS receiver |
RW |
0 |
|
|
|
0 |
[extpll_clkbuf1_underdrive_disabled] Disables EXT PLL
LVCMOS Clock 1 Underdrive |
|
|
|
|
1 |
[extpll_clkbuf1_underdrive_enabled] Enables EXT PLL LVCMOS
Clock 1 Underdrive |
|
|
11 |
EXTPLL_CLKBUF_EN_UDRIVE_P |
Enable Underdrive capability on CMOS receiver |
RW |
0 |
|
|
|
0 |
[extpll_clkbuf0_underdrive_disabled] Disables EXT PLL
LVCMOS Clock 0 Underdrive |
|
|
|
|
1 |
[extpll_clkbuf0_underdrive_enabled] Enables EXT PLL LVCMOS
Clock 0 Underdrive |
|
|
10 |
EXTPLL_CLKBUF_EN_RDIFF |
Enable 100 Ohm Differential Termination (P to N) |
RW |
0 |
|
|
|
0 |
[extpll_dualclk_100ohm_differential_term_disabled]
Disables 100 Ohms Differential Termination (P to N) of EXT PLL Dual Clock
buffer |
|
|
|
|
1 |
[extpll_dualclk_100ohm_differential_term_enabled] Enables
100 Ohms Differential Termination (P to N) of EXT PLL Dual Clock buffer |
|
|
9 |
EXTPLL_DUALCLK0_EN_HYST |
Enable Hysteresis for DUALCLK0 |
RW |
0 |
|
|
|
0 |
[extpll_dualclk0_hysteresis_disabled] Disables Hysteresis
for EXT PLL Dual Clock 0 |
|
|
|
|
1 |
[extpll_dualclk0_hysteresis_enabled] Enables Hysteresis
for EXT PLL Dual Clock 0 |
|
|
8 |
EXTPLL_DUALCLK1_EN_HYST |
Enable Hysteresis for DUALCLK1 |
RW |
0 |
|
|
|
0 |
[extpll_dualclk1_hysteresis_disabled] Disables Hysteresis
for EXT PLL Dual Clock 1 |
|
|
|
|
1 |
[extpll_dualclk1_hysteresis_enabled] Enables Hysteresis
for EXT PLL Dual Clock 1 |
|
|
7:6 |
EXTPLL_DUALCLK0_ENTERM |
Determines Single Ended Termination for DUALCLK0 |
RW |
0x0 |
|
|
|
0x0 |
[extpll_dualclk0_single_end_term_hz_sel] Select infinite
resistance for Dual Clock 0 single ended termination. |
|
|
|
|
0x1 |
[extpll_dualclk0_single_end_term_75ohms_sel] Select 75
ohms for Dual Clock 0 single ended termination. |
|
|
|
|
0x2 |
[extpll_dualclk0_single_end_term_150ohms_sel] Select 150
ohms for Dual Clock 0 single ended termination. |
|
|
|
|
0x3 |
[extpll_dualclk0_single_end_term_50ohms_sel] Select 50 ohms
for Dual Clock 0 single ended termination. |
|
|
5:4 |
EXTPLL_DUALCLK0_MODE |
Determines mode/negative input for DUALCLK0 |
RW |
0x0 |
|
|
|
0x0 |
[extpll_dualclk0_mode_buf_off_sel] Select clock buffer powerdown mode. EXT PLL Dual Clock 0 (P) buffer off. The
output of the buffer pulled high |
|
|
|
|
0x1 |
[extpll_dualclk0_mode_cmos_rcvr_act_sel] Select CMOS Clock
receiver mode. EXT PLL Dual Clock 0 (P) buffer sets to CMOS receiver active
mode. |
|
|
|
|
0x2 |
[extpll_dualclk0_mode_diff_rcvr_act_vref_sel] Select
differential clock receive mode with VREF pin. EXT PLL Dual Clock 0 (P)
buffer sets to differential receiver active mode with VREF pin. |
|
|
|
|
0x3 |
[extpll_dualclk0_mode_diff_rcvr_act_diff_in_sel] Select
differential clock receive mode with differenctial
input. EXT PLL Dual Clock 0 (P) buffer sets to differential receiver active
mode with Dual Clock 1 (N) pin. |
|
|
3:2 |
EXTPLL_DUALCLK1_ENTERM |
Determines Single Ended Termination for DUALCLK1 |
RW |
0x0 |
|
|
|
0x0 |
[extpll_dualclk1_single_end_term_hz_sel] Select infinite resistance
for Dual Clock 1 single ended termination. |
|
|
|
|
0x1 |
[extpll_dualclk1_single_end_term_75ohms_sel] Select 75
ohms for Dual Clock 1 single ended termination. |
|
|
|
|
0x2 |
[extpll_dualclk1_single_end_term_150ohms_sel] Select 150
ohms for Dual Clock 1 single ended termination. |
|
|
|
|
0x3 |
[extpll_dualclk1_single_end_term_50ohms_sel] Select 50
ohms for Dual Clock 1 single ended termination. |
|
|
1:0 |
EXTPLL_DUALCLK1_MODE |
Determines mode/negative input for DUALCLK1 |
RW |
0x0 |
|
|
|
0x0 |
[extpll_dualclk1_mode_buf_off_sel] Select clock buffer powerdown mode. EXT PLL Dual Clock1 (N) buffer off. The
output of the buffer pulled high |
|
|
|
|
0x1 |
[extpll_dualclk1_mode_cmos_rcvr_act_sel] Select CMOS Clock
receiver mode. EXT PLL Dual Clock1 (N) buffer sets to CMOS receiver active
mode. |
|
|
|
|
0x2 |
[extpll_dualclk1_mode_diff_rcvr_act_vref_sel] Select differential
clock receive mode with VREF pin. EXT PLL Dual Clock1 (N) buffer sets to
differential receiver active mode with VREF pin. |
|
|
|
|
0x3 |
[extpll_dualclk1_mode_diff_rcvr_act_diff_in_sel] Select
differential clock receive mode with differenctial
input. EXT PLL Dual Clock1 (N) buffer sets to differential receiver active
mode with Dual Clock0 (P) pin. |
|
Address offset |
0x008 |
||
Physical address |
0x0410 0008 |
Instance |
serdes_35_ext |
0x0408 0008 |
serdes_24_ext |
||
0x0401 0008 |
serdes_01_ext |
||
0x0204 4008 |
pciess_quad_pll0 |
||
0x0404 0008 |
serdes_02_ext |
||
0x0402 0008 |
serdes_13_ext |
||
0x0204 8008 |
pciess_quad_pll1 |
||
Description |
External TXPLL Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:25 |
Reserved |
|
RO |
0x00 |
|
24 |
EXTPLL_LOCK |
External Transmit PLL lock output |
RO |
0 |
|
23 |
EXTPLL_FOUTAUXDIV2_SEL |
Select divided by 2 of auxilary
clock output |
RW |
1 |
|
|
|
0 |
[extpll_auxdiv2_disable] Select Auxilary
clock output |
|
|
|
|
1 |
[extpll_auxdiv_enable] Select
divided by 2 of auxilary clock output |
|
|
22 |
EXTPLL_RESET_RTL |
Reset all RTL for EXTPLL |
RW |
1 |
|
|
|
0 |
[extpll_rtl_reset_deasserted]
EXT PLL RTL reset is deasserted |
|
|
|
|
1 |
[extpll_rtl_reset_asserted] EXT
PLL RTL reset is asserted |
|
|
21 |
EXTPLL_CLKRESET |
Reset signal synchronized and sent to serializers |
RW |
0 |
|
|
|
0 |
[extpll_clock_reset_deasserted]
EXT PLL clock reset is deasserted |
|
|
|
|
1 |
[extpll_clock_reset_asserted]
EXT PLL clock reset is asserted |
|
|
20 |
EXTPLL_CLKRESETEN |
Enable for EXTPLL_CLKRESET |
RW |
0 |
|
|
|
0 |
[extpll_clock_reset_disabled]
Disables EXT PLL clock reset logic |
|
|
|
|
1 |
[extpll_clock_reset_enabled]
Enables EXT PLL clock reset logic |
|
|
19 |
EXTPLL_BIAS_PD |
Powerdown Bias
Currents to fracpll |
RW |
1 |
|
|
|
0 |
[extpll_bias_current_powerdown_off]
EXT PLL Bias Current is in power up |
|
|
|
|
1 |
[extpll_bias_current_powerdown_on]
EXT PLL Bias Current is in power down |
|
|
18 |
EXTPLL_AUXDIVPD |
Active High powerdown for auxilary clock output from TXPLL |
RW |
1 |
|
|
|
0 |
[extpll_auxdiv_powerdown_off] Auxilary clock output from EXT PLL is in power up |
|
|
|
|
1 |
[extpll_auxdiv_powerdown_on] Auxilary clock output from EXT PLL is in power down |
|
|
17 |
EXTPLL_PD |
Transmit PLL Power Down Control |
RW |
1 |
|
|
|
0 |
[extpll_powerdown_off] EXT PLL
is in power up |
|
|
|
|
1 |
[extpll_powerdown_on] EXT PLL is
in power down |
|
|
16 |
EXTPLL_STEP_PHASE |
Step PLL Phase for one PFD period |
RW |
0 |
|
15:8 |
EXTPLL_PHASESTEPAMOUNT |
Signed fractional step for phase stepping (+/- 1/2 integer
bit) |
RW |
0x00 |
|
7:4 |
Reserved |
|
RO |
0x0 |
|
3 |
EXTPLL_DSMPD |
External Transmit PLL fractional modulator PD |
RW |
1 |
|
|
|
0 |
[extpll_fractional_mode_sel]
Sets EXT PLL in fractional mode |
|
|
|
|
1 |
[extpll_integer_mode_sel] Sets
EXT PLL in integer mode |
|
|
2 |
EXTPLL_FBDIV_SEL |
Selects modulation for TXPLL |
RW |
0 |
|
|
|
0 |
[extpll_feedback_div_from_extpll_fbdiv_frac_sel]
Select EXTPLL_FBDIV and EXTPLL_FRAC register values for EXTPLL_FBDIV and
EXTPLL_FRAC |
|
|
|
|
1 |
[extpll_feedback_div_from_ja_int_frac_sel]
Select Jitter Attenuator INT and Jitter Attenuator FRAC for EXTPLL_FBDIV and
EXTPLL_FRAC |
|
|
1 |
EXTPLL_VBGREF_SEL |
Select VBG Reference for PLL voltage regulator |
RW |
0 |
|
|
|
0 |
[extpll_vbgref_vdda_extpll_voltreg_sel]
Select VDDA for VBG Reference for EXT PLL voltage regulator |
|
|
|
|
1 |
[extpll_vbgref_1p1v_extpll_voltreg_sel] Select 1.1V for
VBG Reference for EXT PLL voltage regulator |
|
|
0 |
EXTPLL_PLLBW |
Transmit PLL Bandwidth Control |
RW |
1 |
|
|
|
0 |
[extpll_low_bandwidth_sel]
Select low bandwidth for EXT PLL bandwidth |
|
|
|
|
1 |
[extpll_high_bandwidth_sel]
Select high bandwidth for EXT PLL bandwdith |
|
Address offset |
0x00C |
||
Physical address |
0x0410 000C |
Instance |
serdes_35_ext |
0x0408 000C |
serdes_24_ext |
||
0x0401 000C |
serdes_01_ext |
||
0x0204 400C |
pciess_quad_pll0 |
||
0x0404 000C |
serdes_02_ext |
||
0x0402 000C |
serdes_13_ext |
||
0x0204 800C |
pciess_quad_pll1 |
||
Description |
External TXPLL Clock Select |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:19 |
Reserved |
|
RO |
0x0000 |
|
18:16 |
EXTPLL_JA_FREF_SEL |
Select External PLL Jitter Attenuator Reference Clock |
RW |
0x0 |
|
|
|
0x0 |
[extpll_ja_fref_extpll_refclk_in_sel]
Select EXTPLL Reference Clock input for EXTPLL Jitter Attenuator input clock |
|
|
|
|
0x1 |
[extpll_ja_fref_extpll_cascade_clk_in_sm_sel]
Select cascaded clock soft macro input for EXTPLL Jitter Attenuator input
clock |
|
|
|
|
0x2 |
[extpll_ja_fref_extpll_dualclk0_in_sel] Select EXT PLL Dual
Reference Clock 0 input for EXTPLL Jitter Attenuator input clock |
|
|
|
|
0x3 |
[extpll_ja_fref_extpll_dualclk1_in_sel] Select EXT PLL
Dual Reference Clock 1 input for EXTPLL Jitter Attenuator input clock |
|
|
|
|
0x4 |
[extpll_ja_fref_cdrclk_in_up_sel]
Select CDR Clock in up for EXTPLL Jitter Attenuator input clock |
|
|
|
|
0x5 |
[extpll_ja_fref_cdrclk_in_down_sel]
Select CDR Clock in down for EXTPLL Jitter Attenuator input clock |
|
|
|
|
0x6 |
[extpll_ja_fref_logic0_sel] Select Logic 0 for EXTPLL
Jitter Attenuator input clock |
|
|
|
|
0x7 |
[extpll_ja_fref_atpg_testclk_sel]
Select ATPG test clock for EXTPLL Jitter Attenuator input clock |
|
|
15:13 |
Reserved |
|
RO |
0x0 |
|
12:10 |
EXTPLL_CASCADE_CLK_SEL_SM |
Select External PLL Soft Macro Cascade Clock |
RW |
0x7 |
|
|
|
0x0 |
[extpll_cascade_clk_sm_extpll_dualclk0_in_sel] Select EXT PLL
Dual Reference Clock 0 input for EXT PLL cascade soft macro mux input |
|
|
|
|
0x1 |
[extpll_cascade_clk_sm_extpll_dualclk1_in_sel] Select EXT
PLL Dual Reference Clock 1 input for EXT PLL cascade soft macro mux input |
|
|
|
|
0x2 |
[extpll_cascade_clk_sm_extpll_foutauxdiv_sel]
Select EXT PLL AUX DIV clock for EXT PLL cascade soft macro mux input |
|
|
|
|
0x3 |
[extpll_cascade_clk_sm_extpll_clksscg_sel]
Select EXT PLL SSCG clock for EXT PLL cascade soft macro mux input |
|
|
|
|
0x4 |
[extpll_cascade_clk_sm_extpll_lock_sel]
Select EXT PLL lock signal for EXT PLL cascade soft macro mux input |
|
|
|
|
0x5 |
[extpll_cascade_clk_sm_logic0_sel] Select logic 0 for EXT
PLL cascade soft macro mux input |
|
|
|
|
0x6 |
[extpll_cascade_clk_sm_logic0_sel2] Select logic 0 for EXT
PLL cascade soft macro mux input |
|
|
|
|
0x7 |
[extpll_cascade_clk_sm_extpll_cascade_clk_in_sm_sel]
Select EXT PLL cascade soft macro mux input for EXT PLL cascade soft macro
mux input |
|
|
9:8 |
EXTPLL_CASCADE_CLK_SEL_HM |
Select External PLL Hard Macro Cascade Clock |
RW |
0x3 |
|
|
|
0x0 |
[extpll_cascade_clk_hm_extpll_dualclk0_in_sel] Select EXT
PLL Dual Reference Clock 0 input for EXT PLL cascade hard macro clock input |
|
|
|
|
0x1 |
[extpll_cascade_clk_hm_extpll_dualclk1_in_sel] Select EXT
PLL Dual Reference Clock 1 input for EXT PLL cascade hard macro clock input |
|
|
|
|
0x2 |
[extpll_cascade_clk_hm_extpll_cascade_clk_in_hm_sel]
Select EXT PLL Cascade hard macro clock input from the external PLL above for
EXT PLL cascade hard macro clock input |
|
|
|
|
0x3 |
[extpll_cascade_clk_hm_extpll_cascade_clk_in_hm_sel2]
Select EXT PLL Cascade hard macro clock input from the external PLL above for
EXT PLL cascade hard macro clock input |
|
|
7:5 |
Reserved |
|
RO |
0x0 |
|
4:2 |
EXTPLL_REFCLK_SEL_SM |
Select External PLL Soft Macro Reference Clock |
RW |
0x0 |
|
|
|
0x0 |
[extpll_refclk_sm_extpll_refclk_in_sel]
Select EXTPLL Reference Clock input for EXTPLL soft macro reference clock
input |
|
|
|
|
0x1 |
[extpll_refclk_sm_extpll_cascade_clk_in_sm_sel]
Select cascaded clock soft macro input for EXTPLL soft macro reference clock
input |
|
|
|
|
0x2 |
[extpll_refclk_sm_extpll_dualclk0_in_sel] Select EXT PLL
Dual Reference Clock 0 input for EXTPLL soft macro reference clock input |
|
|
|
|
0x3 |
[extpll_refclk_sm_extpll_dualclk1_in_sel] Select EXT PLL
Dual Reference Clock 1 input for EXTPLL soft macro reference clock input |
|
|
|
|
0x4 |
[extpll_refclk_sm_cdrclk_in_up_sel]
Select CDR Clock in up for EXTPLL soft macro reference clock input |
|
|
|
|
0x5 |
[extpll_refclk_sm_cdrclk_in_down_sel]
Select CDR Clock in down for EXTPLL soft macro reference clock input |
|
|
|
|
0x6 |
[extpll_refclk_sm_logic0_sel] Select Logic 0 for EXTPLL
soft macro reference clock input |
|
|
|
|
0x7 |
[extpll_refclk_sm_logic0_sel2] Select Logic 0 for EXTPLL
soft macro reference clock input |
|
|
1:0 |
EXTPLL_REFCLK_SEL_HM |
EXT PLL Reference Clock Mux |
RW |
0x0 |
|
|
|
0x0 |
[extpll_refclk_hm_extpll_dualclk0_in_sel] Select EXT PLL
Dual-Reference clock 0 for EXT PLL hard macro reference clock input |
|
|
|
|
0x1 |
[extpll_refclk_hm_extpll_cascade_clk_in_hm_sel]
Select hard macro cascade clock input for EXT PLL hard macro reference clock
input |
|
|
|
|
0x2 |
[extpll_refclk_hm_extpll_refclk_hm_sm_out_sel]
Select EXTPLL_REFCLK_SEL_SM mux output clock for EXT PLL hard macro reference
clock input |
|
|
|
|
0x3 |
[extpll_refclk_hm_extpll_refclk_hm_sm_out_sel2] Select
EXTPLL_REFCLK_SEL_SM mux output clock for EXT PLL hard macro reference clock
input |
|
Address offset |
0x010 |
||
Physical address |
0x0410 0010 |
Instance |
serdes_35_ext |
0x0408 0010 |
serdes_24_ext |
||
0x0401 0010 |
serdes_01_ext |
||
0x0204 4010 |
pciess_quad_pll0 |
||
0x0404 0010 |
serdes_02_ext |
||
0x0402 0010 |
serdes_13_ext |
||
0x0204 8010 |
pciess_quad_pll1 |
||
Description |
External TXPLL Dividers |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:28 |
Reserved |
|
RO |
0x0 |
27:16 |
EXTPLL_FBDIV |
Transmit PLL feedback divide value from (16 in integer
mode) |
RW |
0x014 |
15:12 |
Reserved |
|
RO |
0x0 |
11:0 |
EXTPLL_AUXDIV |
External Transmit PLL auxilary
clock output |
RW |
0x014 |
Address offset |
0x014 |
||
Physical address |
0x0410 0014 |
Instance |
serdes_35_ext |
0x0408 0014 |
serdes_24_ext |
||
0x0401 0014 |
serdes_01_ext |
||
0x0204 4014 |
pciess_quad_pll0 |
||
0x0404 0014 |
serdes_02_ext |
||
0x0402 0014 |
serdes_13_ext |
||
0x0204 8014 |
pciess_quad_pll1 |
||
Description |
External TXPLL Dividers |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:30 |
Reserved |
|
RO |
0x0 |
29:24 |
EXTPLL_REFDIV |
Transmit PLL reference divide value (1 to 63) |
RW |
0x01 |
23:0 |
EXTPLL_FRAC |
PLL fractional part of feedback divide value |
RW |
0x00 0001 |
Address offset |
0x018 |
||
Physical address |
0x0410 0018 |
Instance |
serdes_35_ext |
0x0408 0018 |
serdes_24_ext |
||
0x0401 0018 |
serdes_01_ext |
||
0x0204 4018 |
pciess_quad_pll0 |
||
0x0404 0018 |
serdes_02_ext |
||
0x0402 0018 |
serdes_13_ext |
||
0x0204 8018 |
pciess_quad_pll1 |
||
Description |
External TXPLL JA Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
EXTPLL_JA_DIVFFB |
Jitter Attenuator PLL |
RW |
0x0064 |
15:0 |
EXTPLL_JA_DIVFIN |
Jitter Attenuator PLL |
RW |
0x0064 |
Address offset |
0x01C |
||
Physical address |
0x0410 001C |
Instance |
serdes_35_ext |
0x0408 001C |
serdes_24_ext |
||
0x0401 001C |
serdes_01_ext |
||
0x0204 401C |
pciess_quad_pll0 |
||
0x0404 001C |
serdes_02_ext |
||
0x0402 001C |
serdes_13_ext |
||
0x0204 801C |
pciess_quad_pll1 |
||
Description |
External TXPLL JA Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
EXTPLL_JA_SYNCCNTMAX |
Jitter Attenuator PLL |
RW |
0x0000 0064 |
Address offset |
0x020 |
||
Physical address |
0x0410 0020 |
Instance |
serdes_35_ext |
0x0408 0020 |
serdes_24_ext |
||
0x0401 0020 |
serdes_01_ext |
||
0x0204 4020 |
pciess_quad_pll0 |
||
0x0404 0020 |
serdes_02_ext |
||
0x0402 0020 |
serdes_13_ext |
||
0x0204 8020 |
pciess_quad_pll1 |
||
Description |
External TXPLL JA Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
EXTPLL_JA_TARGETCNT |
Jitter Attenuator PLL |
RW |
0x000A |
15:0 |
EXTPLL_JA_CNTOFFSET |
Jitter Attenuator PLL |
RW |
0x0064 |
Address offset |
0x024 |
||
Physical address |
0x0410 0024 |
Instance |
serdes_35_ext |
0x0408 0024 |
serdes_24_ext |
||
0x0401 0024 |
serdes_01_ext |
||
0x0204 4024 |
pciess_quad_pll0 |
||
0x0404 0024 |
serdes_02_ext |
||
0x0402 0024 |
serdes_13_ext |
||
0x0204 8024 |
pciess_quad_pll1 |
||
Description |
External TXPLL JA Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:29 |
Reserved |
|
RO |
0x0 |
28:24 |
EXTPLL_JA_FKI |
Jitter Attenuator PLL |
RW |
0x01 |
23:16 |
EXTPLL_JA_FMI |
Jitter Attenuator PLL |
RW |
0x01 |
15:0 |
EXTPLL_JA_OTDLY |
Jitter Attenuator PLL |
RW |
0x000F |
Address offset |
0x028 |
||
Physical address |
0x0410 0028 |
Instance |
serdes_35_ext |
0x0408 0028 |
serdes_24_ext |
||
0x0401 0028 |
serdes_01_ext |
||
0x0204 4028 |
pciess_quad_pll0 |
||
0x0404 0028 |
serdes_02_ext |
||
0x0402 0028 |
serdes_13_ext |
||
0x0204 8028 |
pciess_quad_pll1 |
||
Description |
External TXPLL JA Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
EXTPLL_JA_PMI2 |
Jitter Attenuator PLL |
RW |
0x01 |
23:16 |
EXTPLL_JA_PMI1 |
Jitter Attenuator PLL |
RW |
0x01 |
15:8 |
EXTPLL_JA_PMP2 |
Jitter Attenuator PLL |
RW |
0x01 |
7:0 |
EXTPLL_JA_PMP1 |
Jitter Attenuator PLL |
RW |
0x01 |
Address offset |
0x02C |
||
Physical address |
0x0410 002C |
Instance |
serdes_35_ext |
0x0408 002C |
serdes_24_ext |
||
0x0401 002C |
serdes_01_ext |
||
0x0204 402C |
pciess_quad_pll0 |
||
0x0404 002C |
serdes_02_ext |
||
0x0402 002C |
serdes_13_ext |
||
0x0204 802C |
pciess_quad_pll1 |
||
Description |
External TXPLL JA Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:29 |
Reserved |
|
RO |
0x0 |
28:24 |
EXTPLL_JA_PKI2 |
Jitter Attenuator PLL |
RW |
0x01 |
23:21 |
Reserved |
|
RO |
0x0 |
20:16 |
EXTPLL_JA_PKI1 |
Jitter Attenuator PLL |
RW |
0x01 |
15:13 |
Reserved |
|
RO |
0x0 |
12:8 |
EXTPLL_JA_PKP2 |
Jitter Attenuator PLL |
RW |
0x01 |
7:5 |
Reserved |
|
RO |
0x0 |
4:0 |
EXTPLL_JA_PKP1 |
Jitter Attenuator PLL |
RW |
0x01 |
Address offset |
0x030 |
||
Physical address |
0x0410 0030 |
Instance |
serdes_35_ext |
0x0408 0030 |
serdes_24_ext |
||
0x0401 0030 |
serdes_01_ext |
||
0x0204 4030 |
pciess_quad_pll0 |
||
0x0404 0030 |
serdes_02_ext |
||
0x0402 0030 |
serdes_13_ext |
||
0x0204 8030 |
pciess_quad_pll1 |
||
Description |
External TXPLL JA Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:27 |
Reserved |
|
RO |
0x00 |
|
26 |
EXTPLL_JA_PROGRAM |
Jitter Attenuator PLL |
RW |
1 |
|
|
|
0 |
[extpll_ja_program_diagnostic_mode_sel]
Select dignostic mode |
|
|
|
|
1 |
[extpll_ja_program_normal_mode_sel]
Select normal mode |
|
|
25 |
EXTPLL_JA_ONTARGETOV |
Jitter Attenuator PLL |
RW |
1 |
|
|
|
0 |
[extpll_ja_ontargetov_diagnostic_mode_sel]
Select dignostic mode |
|
|
|
|
1 |
[extpll_ja_ontargetov_normal_mode_sel]
Select normal mode |
|
|
24 |
EXTPLL_JA_FDONLY |
Jitter Attenuator PLL |
RW |
1 |
|
|
|
0 |
[extpll_ja_frequency_phase_control_sel]
Select Frequency and Phase control for EXT PLL Jitter Attenuator. |
|
|
|
|
1 |
[extpll_ja_frequency_only_control_sel]
Select Frequency only control for EXT PLL Jitter Attenuator. |
|
|
23:0 |
EXTPLL_JA_DELAYK |
Jitter Attenuator PLL |
RW |
0x00 0001 |
Address offset |
0x034 |
||
Physical address |
0x0410 0034 |
Instance |
serdes_35_ext |
0x0408 0034 |
serdes_24_ext |
||
0x0401 0034 |
serdes_01_ext |
||
0x0204 4034 |
pciess_quad_pll0 |
||
0x0404 0034 |
serdes_02_ext |
||
0x0402 0034 |
serdes_13_ext |
||
0x0204 8034 |
pciess_quad_pll1 |
||
Description |
External TXPLL JA Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:26 |
Reserved |
|
RO |
0x00 |
|
25 |
EXTPLL_JA_HOLD |
Jitter Attenuator PLL |
RW |
0 |
|
|
|
0 |
[extpll_ja_hold_output_disabled]
Normal operational mode. |
|
|
|
|
1 |
[extpll_ja_hold_output_enabled]
Enables holding output state of the DPLL. The DPLL will not phase lock in
this state. |
|
|
24 |
EXTPLL_JA_PRESET_EN |
Jitter Attenuator PLL |
RW |
0 |
|
|
|
0 |
[extpll_ja_preset_disabled] Diables loading preset INT and FRAC values into DPLL |
|
|
|
|
1 |
[extpll_ja_preset_enabled]
Enables loading preset INT and FRAC values into DPLL |
|
|
23:0 |
EXTPLL_JA_FRAC_PRESET |
Jitter Attenuator PLL |
RW |
0x00 0000 |
Address offset |
0x038 |
||
Physical address |
0x0410 0038 |
Instance |
serdes_35_ext |
0x0408 0038 |
serdes_24_ext |
||
0x0401 0038 |
serdes_01_ext |
||
0x0204 4038 |
pciess_quad_pll0 |
||
0x0404 0038 |
serdes_02_ext |
||
0x0402 0038 |
serdes_13_ext |
||
0x0204 8038 |
pciess_quad_pll1 |
||
Description |
External TXPLL JA Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:28 |
Reserved |
|
RO |
0x0 |
27:16 |
EXTPLL_JA_INT_PD_OUT |
Jitter Attenuator PLL |
RO |
0x018 |
15:12 |
Reserved |
|
RO |
0x0 |
11:0 |
EXTPLL_JA_INT_PRESET |
Jitter Attenuator PLL |
RW |
0x014 |
Address offset |
0x03C |
||
Physical address |
0x0410 003C |
Instance |
serdes_35_ext |
0x0408 003C |
serdes_24_ext |
||
0x0401 003C |
serdes_01_ext |
||
0x0204 403C |
pciess_quad_pll0 |
||
0x0404 003C |
serdes_02_ext |
||
0x0402 003C |
serdes_13_ext |
||
0x0204 803C |
pciess_quad_pll1 |
||
Description |
External TXPLL JA Control |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:26 |
Reserved |
|
RO |
0x00 |
25 |
EXTPLL_JA_PHASE_LOCK |
Jitter Attenuator PLL |
RO |
0 |
24 |
EXTPLL_JA_FLOCK |
Jitter Attenuator PLL |
RO |
0 |
23:0 |
EXTPLL_JA_FRAC_PD_OUT |
Jitter Attenuator PLL |
RO |
0x00 0000 |
Address offset |
0x040 |
||
Physical address |
0x0410 0040 |
Instance |
serdes_35_ext |
0x0408 0040 |
serdes_24_ext |
||
0x0401 0040 |
serdes_01_ext |
||
0x0204 4040 |
pciess_quad_pll0 |
||
0x0404 0040 |
serdes_02_ext |
||
0x0402 0040 |
serdes_13_ext |
||
0x0204 8040 |
pciess_quad_pll1 |
||
Description |
External TXPLL JA RESETs |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:7 |
Reserved |
|
RO |
0x000 0000 |
|
6 |
EXTPLL_JA_RESET_CLKS_EXT |
Jitter Attenuator PLL |
RW |
1 |
|
|
|
0 |
[extpll_jareset_clks_ext_deasserted]
EXT PLL Jitter Attenuator reset for PLL Sync clock domain is deasserted ( Active when
EXTPLL_JA_RESET_CLKS_OVERRIDE = 1'b1) |
|
|
|
|
1 |
[extpll_jareset_clks_ext_asserted]
EXT PLL Jitter Attenuator reset for PLL Sync clock domain is asserted. ( Active when EXTPLL_JA_RESET_CLKS_OVERRIDE = 1'b1) |
|
|
5 |
EXTPLL_JA_RESET_CLKS_OVERRIDE |
Jitter Attenuator PLL |
RW |
0 |
|
|
|
0 |
[extpll_ja_reset_clks_override_disabled]
Disables EXT PLL Jitter Attenuator override signal for PLL Sync clock domain
reset signal. |
|
|
|
|
1 |
[extpll_ja_reset_clks_override_enabled]
Enables EXT PLL Jitter Attenuator override signal for PLL Sync clock domain
reset signal. |
|
|
4 |
EXTPLL_JA_RESET_FIN_EXT |
Jitter Attenuator PLL |
RW |
1 |
|
|
|
0 |
[extpll_jareset_fin_ext_deasserted]
EXT PLL Jitter Attenuator reset for input clock domain is deasserted
( Active when EXTPLL_JA_RESET_FIN_OVERRIDE = 1'b1) |
|
|
|
|
1 |
[extpll_jareset_fin_ext_asserted]
EXT PLL Jitter Attenuator reset for input clock domain is asserted. ( Active when EXTPLL_JA_RESET_FIN_OVERRIDE = 1'b1) |
|
|
3 |
EXTPLL_JA_RESET_FIN_OVERRIDE |
Jitter Attenuator PLL |
RW |
0 |
|
|
|
0 |
[extpll_ja_reset_fin_override_disabled]
Disables EXT PLL Jitter Attenuator override signal for input clock domain
reset signal. |
|
|
|
|
1 |
[extpll_ja_reset_fin_override_enabled]
Enables EXT PLL Jitter Attenuator override signal for input clock domain
reset signal. |
|
|
2 |
EXTPLL_JA_RESET_FFB_EXT |
Jitter Attenuator PLL |
RW |
1 |
|
|
|
0 |
[extpll_jareset_ffb_ext_deasserted]
EXT PLL Jitter Attenuator reset for feedback clock domain is deasserted ( Active when
EXTPLL_JA_RESET_FFB_OVERRIDE = 1'b1) |
|
|
|
|
1 |
[extpll_jareset_ffb_ext_asserted]
EXT PLL Jitter Attenuator reset for feedback clock domain is asserted. ( Active when EXTPLL_JA_RESET_FFB_OVERRIDE = 1'b1) |
|
|
1 |
EXTPLL_JA_RESET_FFB_OVERRIDE |
Jitter Attenuator PLL |
RW |
0 |
|
|
|
0 |
[extpll_ja_reset_ffb_override_disabled]
Disables EXT PLL Jitter Attenuator override signal for feedback clock domain
reset signal. |
|
|
|
|
1 |
[extpll_ja_reset_ffb_override_enabled]
Enables EXT PLL Jitter Attenuator override signal for feedback clock domain
reset signal. |
|
|
0 |
EXTPLL_JA_RESET |
Jitter Attenuator PLL |
RW |
1 |
|
|
|
0 |
[extpll_ja_reset_deasserted] EXT
PLL Jitter Attenuator reset is deasserted |
|
|
|
|
1 |
[extpll_ja_reset_asserted] EXT
PLL Jitter Attenuator reset is asserted |
|
extpll has no common memories.