Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

SOFT_RESET

RW

32

0x0000 0000

0x000

INMUX0

RW

32

0x0000 0000

0x004

INMUX1

RW

32

0x0000 0000

0x008

INMUX2

RW

32

0x0000 0000

0x00C

OUTMUX0

RW

32

0x0000 0000

0x010

OUTMUX1

RW

32

0x0000 0000

0x014

SPARE0

RW

32

0x0000 0000

0x018

IMIRROR_CTRL

RW

32

0x0000 0001

0x01C

IMIRROR_STAT

RO

32

0x0000 0000

0x020

FMETER_ADDR

RW

32

0x0000 0000

0x024

FMETER_DATAW

RW

32

0x0000 0000

0x028

FMETER_DATAR

RO

32

0x0000 0000

0x02C

IMIRROR_TRIM

RW

32

0x0000 0000

0x030

TEST_CTRL

RW

32

0x0000 0000

0x034

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0A01 0000

INMUX0

RW

32

0x0000 0000

0x004

0x0A01 0004

INMUX1

RW

32

0x0000 0000

0x008

0x0A01 0008

INMUX2

RW

32

0x0000 0000

0x00C

0x0A01 000C

OUTMUX0

RW

32

0x0000 0000

0x010

0x0A01 0010

OUTMUX1

RW

32

0x0000 0000

0x014

0x0A01 0014

SPARE0

RW

32

0x0000 0000

0x018

0x0A01 0018

IMIRROR_CTRL

RW

32

0x0000 0001

0x01C

0x0A01 001C

IMIRROR_STAT

RO

32

0x0000 0000

0x020

0x0A01 0020

FMETER_ADDR

RW

32

0x0000 0000

0x024

0x0A01 0024

FMETER_DATAW

RW

32

0x0000 0000

0x028

0x0A01 0028

FMETER_DATAR

RO

32

0x0000 0000

0x02C

0x0A01 002C

IMIRROR_TRIM

RW

32

0x0000 0000

0x030

0x0A01 0030

TEST_CTRL

RW

32

0x0000 0000

0x034

0x0A01 0034

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0A04 0000

INMUX0

RW

32

0x0000 0000

0x004

0x0A04 0004

INMUX1

RW

32

0x0000 0000

0x008

0x0A04 0008

INMUX2

RW

32

0x0000 0000

0x00C

0x0A04 000C

OUTMUX0

RW

32

0x0000 0000

0x010

0x0A04 0010

OUTMUX1

RW

32

0x0000 0000

0x014

0x0A04 0014

SPARE0

RW

32

0x0000 0000

0x018

0x0A04 0018

IMIRROR_CTRL

RW

32

0x0000 0001

0x01C

0x0A04 001C

IMIRROR_STAT

RO

32

0x0000 0000

0x020

0x0A04 0020

FMETER_ADDR

RW

32

0x0000 0000

0x024

0x0A04 0024

FMETER_DATAW

RW

32

0x0000 0000

0x028

0x0A04 0028

FMETER_DATAR

RO

32

0x0000 0000

0x02C

0x0A04 002C

IMIRROR_TRIM

RW

32

0x0000 0000

0x030

0x0A04 0030

TEST_CTRL

RW

32

0x0000 0000

0x034

0x0A04 0034

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0A10 0000

INMUX0

RW

32

0x0000 0000

0x004

0x0A10 0004

INMUX1

RW

32

0x0000 0000

0x008

0x0A10 0008

INMUX2

RW

32

0x0000 0000

0x00C

0x0A10 000C

OUTMUX0

RW

32

0x0000 0000

0x010

0x0A10 0010

OUTMUX1

RW

32

0x0000 0000

0x014

0x0A10 0014

SPARE0

RW

32

0x0000 0000

0x018

0x0A10 0018

IMIRROR_CTRL

RW

32

0x0000 0001

0x01C

0x0A10 001C

IMIRROR_STAT

RO

32

0x0000 0000

0x020

0x0A10 0020

FMETER_ADDR

RW

32

0x0000 0000

0x024

0x0A10 0024

FMETER_DATAW

RW

32

0x0000 0000

0x028

0x0A10 0028

FMETER_DATAR

RO

32

0x0000 0000

0x02C

0x0A10 002C

IMIRROR_TRIM

RW

32

0x0000 0000

0x030

0x0A10 0030

TEST_CTRL

RW

32

0x0000 0000

0x034

0x0A10 0034

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0A40 0000

INMUX0

RW

32

0x0000 0000

0x004

0x0A40 0004

INMUX1

RW

32

0x0000 0000

0x008

0x0A40 0008

INMUX2

RW

32

0x0000 0000

0x00C

0x0A40 000C

OUTMUX0

RW

32

0x0000 0000

0x010

0x0A40 0010

OUTMUX1

RW

32

0x0000 0000

0x014

0x0A40 0014

SPARE0

RW

32

0x0000 0000

0x018

0x0A40 0018

IMIRROR_CTRL

RW

32

0x0000 0001

0x01C

0x0A40 001C

IMIRROR_STAT

RO

32

0x0000 0000

0x020

0x0A40 0020

FMETER_ADDR

RW

32

0x0000 0000

0x024

0x0A40 0024

FMETER_DATAW

RW

32

0x0000 0000

0x028

0x0A40 0028

FMETER_DATAR

RO

32

0x0000 0000

0x02C

0x0A40 002C

IMIRROR_TRIM

RW

32

0x0000 0000

0x030

0x0A40 0030

TEST_CTRL

RW

32

0x0000 0000

0x034

0x0A40 0034

Address offset

0x000

Physical address

0x0A40 0000

Instance

cfm_ccm_sw

0x0A04 0000

cfm_ccm_ne

0x0A10 0000

cfm_ccm_iob_ccc_nw

0x0A01 0000

cfm_ccm_iob_ccc_se

Description

This is a compulsory register for all SCB slaves and must be at the same offset in all slaves to facilitate global soft reset of all SCB registers with a single broadcast write from the SCB master.

Type

RW

31:16

BLOCKID

This returns the block type and chip location. (IO SCB bus only)

RO

0x0000

Read 0x0000

[block_address_IOSCB_CFM]

15:9

Reserved

RO
Rreturns0s

0x00

8

PERIPH

This asserts the functional reset of the block. It is asserted at power up. When written is stays asserted until written to 0.

WO

0

Write 0

[scb_periph_not_in_soft_reset_IOSCB_CFM]

Write 1

[scb_periph_reset_IOSCB_CFM]

7:2

Reserved

RO
Rreturns0s

0x00

1

V_MAP

This when asserted resets all the register bits apart from the non-volatile registers, the bit self clears. i.e. is similar to a W1P bit

WO

0

Write 0

[scb_v_regs_not_in_soft_reset_IOSCB_CFM]

Write 1

[scb_v_regs_reset_IOSCB_CFM]

0

NV_MAP

This when asserted resets all the non-volatile register bits e.g. RW-P bits, the bit self clears i.e. is similar to a W1P bit

WO

0

Write 0

[scb_nv_regs_not_in_soft_reset_IOSCB_CFM]

Write 1

[scb_nv_regs_reset_IOSCB_CFM]

Address offset

0x004

Physical address

0x0A40 0004

Instance

cfm_ccm_sw

0x0A04 0004

cfm_ccm_ne

0x0A10 0004

cfm_ccm_iob_ccc_nw

0x0A01 0004

cfm_ccm_iob_ccc_se

Description

Input mux selections

Type

RW

31:28

cimux_ref2_sel

RW

0x0

27:24

cimux_ref1_sel

RW

0x0

23:20

cimux_ref0_sel

RW

0x0

19:18

cimux_gen5_sel

RW

0x0

17:16

cimux_gen4_sel

RW

0x0

15:12

cimux_gen3_sel

RW

0x0

11:8

cimux_gen2_sel

RW

0x0

7:4

cimux_gen1_sel

RW

0x0

3:0

cimux_gen0_sel

RW

0x0

Address offset

0x008

Physical address

0x0A40 0008

Instance

cfm_ccm_sw

0x0A04 0008

cfm_ccm_ne

0x0A10 0008

cfm_ccm_iob_ccc_nw

0x0A01 0008

cfm_ccm_iob_ccc_se

Description

Input mux selections

Type

RW

31

cdmux2_sel

RW

0

30

cdmux1_sel

RW

0

29:28

cdmux0_sel

RW

0x0

27:24

cimux_ref9_sel

RW

0x0

23:20

cimux_ref8_sel

RW

0x0

19:16

cimux_ref7_sel

RW

0x0

15:12

cimux_ref6_sel

RW

0x0

11:8

cimux_ref5_sel

RW

0x0

7:4

cimux_ref4_sel

RW

0x0

3:0

cimux_ref3_sel

RW

0x0

Address offset

0x00C

Physical address

0x0A40 000C

Instance

cfm_ccm_sw

0x0A04 000C

cfm_ccm_ne

0x0A10 000C

cfm_ccm_iob_ccc_nw

0x0A01 000C

cfm_ccm_iob_ccc_se

Description

Configurable delay line selections

Type

RW

31:26

Reserved

RO

0x00

25

delay_test_b

RO

0

24

delay_test_a

RO

0

23

delay_test_en

RW

0

22

cdelay1_en

RW

0

21

cdelay0_en

RW

0

20:13

cdelay1_sel

RW

0x00

12:5

cdelay0_sel

RW

0x00

4

cdmux6_sel

RW

0

3

cdmux5_sel

RW

0

2

cdmux4_sel

RW

0

1:0

cdmux3_sel

RW

0x0

Address offset

0x010

Physical address

0x0A40 0010

Instance

cfm_ccm_sw

0x0A04 0010

cfm_ccm_ne

0x0A10 0010

cfm_ccm_iob_ccc_nw

0x0A01 0010

cfm_ccm_iob_ccc_se

Description

output mux selection

Type

RW

31:28

comux7_sel

RW

0x0

27:24

comux6_sel

RW

0x0

23:20

comux5_sel

RW

0x0

19:16

comux4_sel

RW

0x0

15:12

comux3_sel

RW

0x0

11:8

comux2_sel

RW

0x0

7:4

comux1_sel

RW

0x0

3:0

comux0_sel

RW

0x0

Address offset

0x014

Physical address

0x0A40 0014

Instance

cfm_ccm_sw

0x0A04 0014

cfm_ccm_ne

0x0A10 0014

cfm_ccm_iob_ccc_nw

0x0A01 0014

cfm_ccm_iob_ccc_se

Description

Feeder clocks enable

Type

RW

31:24

Reserved

RO

0x00

23:20

srmux1_sel

RW

0x0

19:16

srmux0_sel

RW

0x0

15:8

crnfdr_vert_en

RW

0x00

7:0

crnfdr_horz_en

RW

0x00

Address offset

0x018

Physical address

0x0A40 0018

Instance

cfm_ccm_sw

0x0A04 0018

cfm_ccm_ne

0x0A10 0018

cfm_ccm_iob_ccc_nw

0x0A01 0018

cfm_ccm_iob_ccc_se

Description

spare logic

Type

RW

31:28

Reserved

RO
Rreturns0s

0x0

27:0

spare0

RW

0x000 0000

Address offset

0x01C

Physical address

0x0A40 001C

Instance

cfm_ccm_sw

0x0A04 001C

cfm_ccm_ne

0x0A10 001C

cfm_ccm_iob_ccc_nw

0x0A01 001C

cfm_ccm_iob_ccc_se

Description

Imirror_control_selections

Type

RW

31:23

Reserved

RO

0x000

22

en_v1p2buf

RW

0

21

calib_poffset_dir

RW

0

20:15

calib_poffset

RW

0x00

14:7

calib_pcode

RW

0x00

6

calib_trim

RW

0

5

calib_start

RW

0

4

calib_move_pcode

RW

0

3

calib_lock

RW

0

2

calib_load

RW

0

1

calib_direction

RW

0

0

calib_rst_b

RW

1

Address offset

0x020

Physical address

0x0A40 0020

Instance

cfm_ccm_sw

0x0A04 0020

cfm_ccm_ne

0x0A10 0020

cfm_ccm_iob_ccc_nw

0x0A01 0020

cfm_ccm_iob_ccc_se

Description

Imirror_status_register

Type

RO

31:29

Reserved

RO

0x0

28:26

sro_ref_bg_code

RO

0x0

25:23

sro_bg_code

RO

0x0

22

sro_comp_out

RO

0

21

sro_power_on

RO

0

20:13

sro_cc_code

RO

0x00

12

sro_ioen_out

RO

0

11

sro_comp_sel

RO

0

10:3

sro_ref_cc_code

RO

0x00

2

sro_comp_en

RO

0

1

sro_calib_status

RO

0

0

sro_calib_intrpt

RO

0

Address offset

0x024

Physical address

0x0A40 0024

Instance

cfm_ccm_sw

0x0A04 0024

cfm_ccm_ne

0x0A10 0024

cfm_ccm_iob_ccc_nw

0x0A01 0024

cfm_ccm_iob_ccc_se

Description

Frequency_meter_address_selections

Type

RW

31:6

Reserved

RO

0x000 0000

5:2

addr

RW

0x0

1:0

Reserved

RO

0x0

Address offset

0x028

Physical address

0x0A40 0028

Instance

cfm_ccm_sw

0x0A04 0028

cfm_ccm_ne

0x0A10 0028

cfm_ccm_iob_ccc_nw

0x0A01 0028

cfm_ccm_iob_ccc_se

Description

Frequency_meter_data_write

Type

RW

31:25

Reserved

RO

0x00

24

strobe

RW
W1P

0

23:0

data

RW

0x00 0000

Address offset

0x02C

Physical address

0x0A40 002C

Instance

cfm_ccm_sw

0x0A04 002C

cfm_ccm_ne

0x0A10 002C

cfm_ccm_iob_ccc_nw

0x0A01 002C

cfm_ccm_iob_ccc_se

Description

Frequency_meter_data_read

Type

RO

31:24

Reserved

RO

0x00

23:0

data

RO

0x00 0000

Address offset

0x030

Physical address

0x0A40 0030

Instance

cfm_ccm_sw

0x0A04 0030

cfm_ccm_ne

0x0A10 0030

cfm_ccm_iob_ccc_nw

0x0A01 0030

cfm_ccm_iob_ccc_se

Description

Imirror TRIM Bits

Type

RW

31:11

Reserved

RO

0x00 0000

10:3

cc_code

RW

0x00

2:0

bg_code

RW

0x0

Address offset

0x034

Physical address

0x0A40 0034

Instance

cfm_ccm_sw

0x0A04 0034

cfm_ccm_ne

0x0A10 0034

cfm_ccm_iob_ccc_nw

0x0A01 0034

cfm_ccm_iob_ccc_se

Description

Test MUX Controls

Type

RW

31:16

Reserved

RO

0x0000

15:11

dtest_sel

RW

0x00

10

dtest_en

RW

0

9:5

atest_sel

RW

0x00

4

atest_en

RW

0

3:0

osc_enable

RW

0x0