Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x00

0x0E00 2000

BCLKMUX

RW

32

0x0000 0000

0x04

0x0E00 2004

PLL_CKMUX

RW

32

0x0000 0000

0x08

0x0E00 2008

MSSCLKMUX

RW

32

0x0000 0000

0x0C

0x0E00 200C

SPARE0

RW

32

0x0000 0000

0x10

0x0E00 2010

FMETER_ADDR

RW

32

0x0000 0000

0x14

0x0E00 2014

FMETER_DATAW

RW

32

0x0000 0000

0x18

0x0E00 2018

FMETER_DATAR

RO

32

0x0000 0000

0x1C

0x0E00 201C

TEST_CTRL

RW

32

0x0000 0000

0x20

0x0E00 2020

Address offset

0x00

Physical address

0x0E00 2000

Instance

cfm_mss

Description

This is a compulsory register for all SCB slaves and must be at the same offset in all slaves to facilitate global soft reset of all SCB registers with a single broadcast write from the SCB master.

Type

RW

31:16

BLOCKID

This returns the block type and chip location. (IO SCB bus only)

RO

0x0000

Read 0x0000

[block_address_IOSCB_CFM_MSS]

15:9

Reserved

RO
Rreturns0s

0x00

8

PERIPH

This asserts the functional reset of the block. It is asserted at power up. When written is stays asserted until written to 0.

WO

0

Write 0

[scb_periph_not_in_soft_reset_IOSCB_CFM_MSS]

Write 1

[scb_periph_reset_IOSCB_CFM_MSS]

7:2

Reserved

RO
Rreturns0s

0x00

1

V_MAP

This when asserted resets all the register bits apart from the non-volatile registers, the bit self clears. i.e. is similar to a W1P bit

WO

0

Write 0

[scb_v_regs_not_in_soft_reset_IOSCB_CFM_MSS]

Write 1

[scb_v_regs_reset_IOSCB_CFM_MSS]

0

NV_MAP

This when asserted resets all the non-volatile register bits e.g. RW-P bits, the bit self clears i.e. is similar to a W1P bit

WO

0

Write 0

[scb_nv_regs_not_in_soft_reset_IOSCB_CFM_MSS]

Write 1

[scb_nv_regs_reset_IOSCB_CFM_MSS]

Address offset

0x04

Physical address

0x0E00 2004

Instance

cfm_mss

Description

BCLK mux selections

Type

RW

31:30

Reserved

RO

0x0

29:25

bclk5_sel

RW

0x00

24:20

bclk4_sel

RW

0x00

19:15

bclk3_sel

RW

0x00

14:10

bclk2_sel

RW

0x00

9:5

bclk1_sel

RW

0x00

4:0

bclk0_sel

RW

0x00

Address offset

0x08

Physical address

0x0E00 2008

Instance

cfm_mss

Description

PLL RF clk mux selections

Type

RW

31:15

Reserved

RO

0x0 0000

14:10

pll1_fdr_sel

RW

0x00

9:8

pll1_rfclk1_sel

RW

0x0

7:6

pll1_rfclk0_sel

RW

0x0

5:4

pll0_rfclk1_sel

RW

0x0

3:2

pll0_rfclk0_sel

RW

0x0

1:0

clk_in_mac_tsu_sel

RW

0x0

Address offset

0x0C

Physical address

0x0E00 200C

Instance

cfm_mss

Description

MSS Clock mux selections

Type

RW

31:5

Reserved

RO

0x000 0000

4

clk_standby_sel

RW

0

3:2

mssclk_mux_md

RW

0x0

1:0

mssclk_mux_sel

RW

0x0

Address offset

0x10

Physical address

0x0E00 2010

Instance

cfm_mss

Description

spare logic

Type

RW

31:0

spare0

RW

0x0000 0000

Address offset

0x14

Physical address

0x0E00 2014

Instance

cfm_mss

Description

Frequency_meter_address_selections

Type

RW

31:6

Reserved

RO

0x000 0000

5:2

addr

RW

0x0

1:0

Reserved

RO

0x0

Address offset

0x18

Physical address

0x0E00 2018

Instance

cfm_mss

Description

Frequency_meter_data_write

Type

RW

31:25

Reserved

RO

0x00

24

strobe

RW
W1P

0

23:0

data

RW

0x00 0000

Address offset

0x1C

Physical address

0x0E00 201C

Instance

cfm_mss

Description

Frequency_meter_data_read

Type

RO

31:24

Reserved

RO

0x00

23:0

data

RO

0x00 0000

Address offset

0x20

Physical address

0x0E00 2020

Instance

cfm_mss

Description

Test MUX Controls

Type

RW

31:12

Reserved

RO

0x0 0000

11:7

dtest_sel

RW

0x00

6

dtest_en

RW

0

5:1

atest_sel

RW

0x00

0

atest_en

RW

0