Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

SOFT_RESET

RW

32

0x0000 0000

0x000

DLL_CTRL0

RW

32

0x0004 2000

0x004

DLL_CTRL1

RW

32

0x0000 0000

0x008

DLL_STAT0

RW

32

0x0000 301D

0x00C

DLL_STAT1

RO

32

0x0000 0000

0x010

DLL_STAT2

RO

32

0x0000 0000

0x014

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0901 0000

DLL_CTRL0

RW

32

0x0004 2000

0x004

0x0901 0004

DLL_CTRL1

RW

32

0x0000 0000

0x008

0x0901 0008

DLL_STAT0

RW

32

0x0000 301D

0x00C

0x0901 000C

DLL_STAT1

RO

32

0x0000 0000

0x010

0x0901 0010

DLL_STAT2

RO

32

0x0000 0000

0x014

0x0901 0014

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0902 0000

DLL_CTRL0

RW

32

0x0004 2000

0x004

0x0902 0004

DLL_CTRL1

RW

32

0x0000 0000

0x008

0x0902 0008

DLL_STAT0

RW

32

0x0000 301D

0x00C

0x0902 000C

DLL_STAT1

RO

32

0x0000 0000

0x010

0x0902 0010

DLL_STAT2

RO

32

0x0000 0000

0x014

0x0902 0014

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0904 0000

DLL_CTRL0

RW

32

0x0004 2000

0x004

0x0904 0004

DLL_CTRL1

RW

32

0x0000 0000

0x008

0x0904 0008

DLL_STAT0

RW

32

0x0000 301D

0x00C

0x0904 000C

DLL_STAT1

RO

32

0x0000 0000

0x010

0x0904 0010

DLL_STAT2

RO

32

0x0000 0000

0x014

0x0904 0014

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0908 0000

DLL_CTRL0

RW

32

0x0004 2000

0x004

0x0908 0004

DLL_CTRL1

RW

32

0x0000 0000

0x008

0x0908 0008

DLL_STAT0

RW

32

0x0000 301D

0x00C

0x0908 000C

DLL_STAT1

RO

32

0x0000 0000

0x010

0x0908 0010

DLL_STAT2

RO

32

0x0000 0000

0x014

0x0908 0014

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0910 0000

DLL_CTRL0

RW

32

0x0004 2000

0x004

0x0910 0004

DLL_CTRL1

RW

32

0x0000 0000

0x008

0x0910 0008

DLL_STAT0

RW

32

0x0000 301D

0x00C

0x0910 000C

DLL_STAT1

RO

32

0x0000 0000

0x010

0x0910 0010

DLL_STAT2

RO

32

0x0000 0000

0x014

0x0910 0014

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0920 0000

DLL_CTRL0

RW

32

0x0004 2000

0x004

0x0920 0004

DLL_CTRL1

RW

32

0x0000 0000

0x008

0x0920 0008

DLL_STAT0

RW

32

0x0000 301D

0x00C

0x0920 000C

DLL_STAT1

RO

32

0x0000 0000

0x010

0x0920 0010

DLL_STAT2

RO

32

0x0000 0000

0x014

0x0920 0014

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0940 0000

DLL_CTRL0

RW

32

0x0004 2000

0x004

0x0940 0004

DLL_CTRL1

RW

32

0x0000 0000

0x008

0x0940 0008

DLL_STAT0

RW

32

0x0000 301D

0x00C

0x0940 000C

DLL_STAT1

RO

32

0x0000 0000

0x010

0x0940 0010

DLL_STAT2

RO

32

0x0000 0000

0x014

0x0940 0014

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0980 0000

DLL_CTRL0

RW

32

0x0004 2000

0x004

0x0980 0004

DLL_CTRL1

RW

32

0x0000 0000

0x008

0x0980 0008

DLL_STAT0

RW

32

0x0000 301D

0x00C

0x0980 000C

DLL_STAT1

RO

32

0x0000 0000

0x010

0x0980 0010

DLL_STAT2

RO

32

0x0000 0000

0x014

0x0980 0014

Address offset

0x000

Physical address

0x0901 0000

Instance

dll_se_0

0x0902 0000

dll_se_1

0x0940 0000

dll_sw_0

0x0904 0000

dll_ne_0

0x0910 0000

dll_nw_0

0x0980 0000

dll_sw_1

0x0920 0000

dll_nw_1

0x0908 0000

dll_ne_1

Description

This is a compulsory register for all SCB slaves and must be at the same offset in all slaves to facilitate global soft reset of all SCB registers with a single broadcast write from the SCB master.

Type

RW

31:16

BLOCKID

This returns the block type and chip location. (IO SCB bus only)

RO

0x0000

Read 0x0000

[block_address_IOSCB_DLL]

15:9

Reserved

RO
Rreturns0s

0x00

8

PERIPH

This asserts the functional reset of the block. It is asserted at power up. When written is stays asserted until written to 0.

WO

0

Write 0

[scb_periph_not_in_soft_reset_IOSCB_DLL]

Write 1

[scb_periph_reset_IOSCB_DLL]

7:2

Reserved

RO
Rreturns0s

0x00

1

V_MAP

This when asserted resets all the register bits apart from the non-volatile registers, the bit self clears. i.e. is similar to a W1P bit

WO

0

Write 0

[scb_v_regs_not_in_soft_reset_IOSCB_DLL]

Write 1

[scb_v_regs_reset_IOSCB_DLL]

0

NV_MAP

This when asserted resets all the non-volatile register bits e.g. RW-P bits, the bit self clears i.e. is similar to a W1P bit

WO

0

Write 0

[scb_nv_regs_not_in_soft_reset_IOSCB_DLL]

Write 1

[scb_nv_regs_reset_IOSCB_DLL]

Address offset

0x004

Physical address

0x0901 0004

Instance

dll_se_0

0x0902 0004

dll_se_1

0x0940 0004

dll_sw_0

0x0904 0004

dll_ne_0

0x0910 0004

dll_nw_0

0x0980 0004

dll_sw_1

0x0920 0004

dll_nw_1

0x0908 0004

dll_ne_1

Description

DLL control register 0

Type

RW

31:28

reg_lock_low

 accumulating 3~15 cycles of phase detector lock low, 00xx=3 cycles

RW

0x0

27:24

reg_lock_high

 accumulating 3~15 cycles of phase detector lock high, 00xx=3 cycles

RW

0x0

23:22

reg_lock_dbg

RW

0x0

21:20

reg_lock_flt

Phase lock tolerance: 00 (Default) +/- 50~130ps, 01 +/- 110~270ps, 10 +/- 200~470ps, 11 +/- 280~680ps

RW

0x0

19

reg_lock_frc

force lock high for debugging purpose

RW

0

18:16

reg_fphase_code

RW

0x4

15:14

reg_alu_upd

00=ALU update after 16 accumulated cycles of add or subtract; 01=8 cycles; 10=32 cycles; 11=4 cycles 

RW

0x0

13:11

reg_fphase_clk

RW

0x4

10

reg_div_sel

divided feedback clock select in clock injection removal mode: 0=M4/M5 selects 0/1; 1=M4/M5 selects 2/3 

RW

0

9

reg_fb_sel

feedback clock selection: 0=direct feedback or through dummy delay to match divider on reference; 1=2*pi shift for clock phase reference mode or feedback through dummy delay inversion 

RW

0

8

reg_ref_sel

reference clock selection: 0=/1 or /2 0 shift; 1=pi shift for delay match mode or /4 0 shift 

RW

0

7:6

reg_sel_s

secondary clock output selection: 00=normal; 01=/2; 10=/4; 11=duty 50 when ref_sel=0 and fb_sel=1 for clock phase reference mode (reg_div_sel=0)

RW

0x0

5:4

reg_sel_p

primary clock output selection: 00=normal; 01=normal through dummy delay to match divider on clko_s; 10=duty 50 when ref_sel=0 and fb_sel=1 for clock phase reference mode (reg_div_sel=0); 11=duty 50 inversion

RW

0x0

3:2

reg_phase_s

 secondary clock phase selection: 00=pi/2 shift; 01=pi shift; 10=3*pi/2 shift; 11=2*pi shift

RW

0x0

1:0

reg_phase_p

 primary clock phase selection: 00=0 shift; 01=pi/2 shift; 10=pi shift; 11=2*pi shift

RW

0x0

Address offset

0x008

Physical address

0x0901 0008

Instance

dll_se_0

0x0902 0008

dll_se_1

0x0940 0008

dll_sw_0

0x0904 0008

dll_ne_0

0x0910 0008

dll_nw_0

0x0980 0008

dll_sw_1

0x0920 0008

dll_nw_1

0x0908 0008

dll_ne_1

Description

DLL control register 1

Type

RW

31

reg_powerdown_en

RW

0

30

reg_relock_fast

At unlock, keep locking without counting down to 0 first in clock injection removal mode

RW

0

29:24

reg_init_code

force ALU to count to the minimum initial delay in each delay cell from 0 (00000) to 63 (11111) taps 

RW

0x00

23

reg_test_ring

enable ring oscillator test mode 

RW

0

22:16

reg_adj_code

RW

0x00

15

reg_test_s

select clko_s to drive ring oscillator in test mode 

RW

0

14:8

reg_adj_del4

adjust fine phase shift in DEL4, when MSB=1, subtract reg_adj_del4[5:0]; otherwise add reg_adj_del4[5:0] 

RW

0x00

7:0

reg_set_alu

when reg_set_alu[7]=1, manual set ALU to reg_set_alu[6:0]

RW

0x00

Address offset

0x00C

Physical address

0x0901 000C

Instance

dll_se_0

0x0902 000C

dll_se_1

0x0940 000C

dll_sw_0

0x0904 000C

dll_ne_0

0x0910 000C

dll_nw_0

0x0980 000C

dll_sw_1

0x0920 000C

dll_nw_1

0x0908 000C

dll_ne_1

Description

DLL status register 0

Type

RW

31:24

sro_adj_code

RO

0x00

23:16

sro_delay_code

RO

0x00

15:14

Reserved

RO

0x0

13

reg_phase_move_code

RW

1

12

reg_phase_move_clk

fine phase shifting on clko_s when going high, has to go low before the next shifting 

RW

1

11

reg_unlock_int

unlock interrupt

RW
W1toClr

0

10

reg_lock_int

lock interrupt

RW
W1toClr

0

9

reg_unlock_int_en

enable unlock interrupt

RW

0

8

reg_lock_int_en

enable lock interrupt 

RW

0

7:5

reg_diff_range

RW

0x0

4

reg_phase_direction

RW

1

3

reg_phase_load

RW

1

2

reg_code_upd

RW

1

1

reg_alu_hold

RW

0

0

reg_reset

active high reset of DLL 

RW

1

Address offset

0x010

Physical address

0x0901 0010

Instance

dll_se_0

0x0902 0010

dll_se_1

0x0940 0010

dll_sw_0

0x0904 0010

dll_ne_0

0x0910 0010

dll_nw_0

0x0980 0010

dll_sw_1

0x0920 0010

dll_nw_1

0x0908 0010

dll_ne_1

Description

DLL status register 1

Type

RO

31:30

sro_del3

RO

0x0

29:28

sro_del2

RO

0x0

27:26

sro_del1

RO

0x0

25

sro_inc

RO

0

24:16

sro_alu_cnt

 ALU counter value, upper 7-bits are DEL0 setting

RO

0x000

15:8

sro_adj_del4

RO

0x00

7

sro_phase_done_clk

RO

0

6:0

sro_del4

 same as delay_code output

RO

0x00

Address offset

0x014

Physical address

0x0901 0014

Instance

dll_se_0

0x0902 0014

dll_se_1

0x0940 0014

dll_sw_0

0x0904 0014

dll_ne_0

0x0910 0014

dll_nw_0

0x0980 0014

dll_sw_1

0x0920 0014

dll_nw_1

0x0908 0014

dll_ne_1

Description

DLL status register 2

Type

RO

31:24

code_readback1

RO

0x00

23:16

code_readback0

RO

0x00

15:7

Reserved

RO

0x000

6

sro_up

RO

0

5

sro_updn

RO

0

4

sro_dn

RO

0

3

sro_delay_diff

RO

0

2

sro_lock

 same as lock output

RO

0

1

sro_phase_done_code

RO

0

0

sro_ring_osc

RO

0