This section
provides information on the IOSCB_ICB Module Instance. Each of the module
registers is described below.
Return to mpfs_ioscb_memmap_dri
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
RW |
32 |
0x0000 0000 |
0x000 |
|
RW |
32 |
0x00FF FFFF |
0x004 |
|
RW |
32 |
0x00FF FFFF |
0x008 |
|
RW |
32 |
0x00FF FFFF |
0x00C |
|
RW |
32 |
0x0000 0000 |
0x010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
|
RW |
32 |
0x0000 0000 |
0x01C |
|
RW |
32 |
0x0000 0000 |
0x020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
|
RW |
32 |
0x0000 0000 |
0x030 |
|
RW |
32 |
0x0000 0000 |
0x034 |
|
RW |
32 |
0x0000 0000 |
0x038 |
|
RW |
32 |
0x0000 0000 |
0x03C |
|
RO |
32 |
0x0000 0000 |
0x040 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0501 0000 |
|
RW |
32 |
0x00FF FFFF |
0x004 |
0x0501 0004 |
|
RW |
32 |
0x00FF FFFF |
0x008 |
0x0501 0008 |
|
RW |
32 |
0x00FF FFFF |
0x00C |
0x0501 000C |
|
RW |
32 |
0x0000 0000 |
0x010 |
0x0501 0010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x0501 0014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x0501 0018 |
|
RW |
32 |
0x0000 0000 |
0x01C |
0x0501 001C |
|
RW |
32 |
0x0000 0000 |
0x020 |
0x0501 0020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x0501 0024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x0501 0028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
0x0501 002C |
|
RW |
32 |
0x0000 0000 |
0x030 |
0x0501 0030 |
|
RW |
32 |
0x0000 0000 |
0x034 |
0x0501 0034 |
|
RW |
32 |
0x0000 0000 |
0x038 |
0x0501 0038 |
|
RW |
32 |
0x0000 0000 |
0x03C |
0x0501 003C |
|
RO |
32 |
0x0000 0000 |
0x040 |
0x0501 0040 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0502 0000 |
|
RW |
32 |
0x00FF FFFF |
0x004 |
0x0502 0004 |
|
RW |
32 |
0x00FF FFFF |
0x008 |
0x0502 0008 |
|
RW |
32 |
0x00FF FFFF |
0x00C |
0x0502 000C |
|
RW |
32 |
0x0000 0000 |
0x010 |
0x0502 0010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x0502 0014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x0502 0018 |
|
RW |
32 |
0x0000 0000 |
0x01C |
0x0502 001C |
|
RW |
32 |
0x0000 0000 |
0x020 |
0x0502 0020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x0502 0024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x0502 0028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
0x0502 002C |
|
RW |
32 |
0x0000 0000 |
0x030 |
0x0502 0030 |
|
RW |
32 |
0x0000 0000 |
0x034 |
0x0502 0034 |
|
RW |
32 |
0x0000 0000 |
0x038 |
0x0502 0038 |
|
RW |
32 |
0x0000 0000 |
0x03C |
0x0502 003C |
|
RO |
32 |
0x0000 0000 |
0x040 |
0x0502 0040 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0504 0000 |
|
RW |
32 |
0x00FF FFFF |
0x004 |
0x0504 0004 |
|
RW |
32 |
0x00FF FFFF |
0x008 |
0x0504 0008 |
|
RW |
32 |
0x00FF FFFF |
0x00C |
0x0504 000C |
|
RW |
32 |
0x0000 0000 |
0x010 |
0x0504 0010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x0504 0014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x0504 0018 |
|
RW |
32 |
0x0000 0000 |
0x01C |
0x0504 001C |
|
RW |
32 |
0x0000 0000 |
0x020 |
0x0504 0020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x0504 0024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x0504 0028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
0x0504 002C |
|
RW |
32 |
0x0000 0000 |
0x030 |
0x0504 0030 |
|
RW |
32 |
0x0000 0000 |
0x034 |
0x0504 0034 |
|
RW |
32 |
0x0000 0000 |
0x038 |
0x0504 0038 |
|
RW |
32 |
0x0000 0000 |
0x03C |
0x0504 003C |
|
RO |
32 |
0x0000 0000 |
0x040 |
0x0504 0040 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0510 0000 |
|
RW |
32 |
0x00FF FFFF |
0x004 |
0x0510 0004 |
|
RW |
32 |
0x00FF FFFF |
0x008 |
0x0510 0008 |
|
RW |
32 |
0x00FF FFFF |
0x00C |
0x0510 000C |
|
RW |
32 |
0x0000 0000 |
0x010 |
0x0510 0010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x0510 0014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x0510 0018 |
|
RW |
32 |
0x0000 0000 |
0x01C |
0x0510 001C |
|
RW |
32 |
0x0000 0000 |
0x020 |
0x0510 0020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x0510 0024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x0510 0028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
0x0510 002C |
|
RW |
32 |
0x0000 0000 |
0x030 |
0x0510 0030 |
|
RW |
32 |
0x0000 0000 |
0x034 |
0x0510 0034 |
|
RW |
32 |
0x0000 0000 |
0x038 |
0x0510 0038 |
|
RW |
32 |
0x0000 0000 |
0x03C |
0x0510 003C |
|
RO |
32 |
0x0000 0000 |
0x040 |
0x0510 0040 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0520 0000 |
|
RW |
32 |
0x00FF FFFF |
0x004 |
0x0520 0004 |
|
RW |
32 |
0x00FF FFFF |
0x008 |
0x0520 0008 |
|
RW |
32 |
0x00FF FFFF |
0x00C |
0x0520 000C |
|
RW |
32 |
0x0000 0000 |
0x010 |
0x0520 0010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x0520 0014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x0520 0018 |
|
RW |
32 |
0x0000 0000 |
0x01C |
0x0520 001C |
|
RW |
32 |
0x0000 0000 |
0x020 |
0x0520 0020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x0520 0024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x0520 0028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
0x0520 002C |
|
RW |
32 |
0x0000 0000 |
0x030 |
0x0520 0030 |
|
RW |
32 |
0x0000 0000 |
0x034 |
0x0520 0034 |
|
RW |
32 |
0x0000 0000 |
0x038 |
0x0520 0038 |
|
RW |
32 |
0x0000 0000 |
0x03C |
0x0520 003C |
|
RO |
32 |
0x0000 0000 |
0x040 |
0x0520 0040 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0540 0000 |
|
RW |
32 |
0x00FF FFFF |
0x004 |
0x0540 0004 |
|
RW |
32 |
0x00FF FFFF |
0x008 |
0x0540 0008 |
|
RW |
32 |
0x00FF FFFF |
0x00C |
0x0540 000C |
|
RW |
32 |
0x0000 0000 |
0x010 |
0x0540 0010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x0540 0014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x0540 0018 |
|
RW |
32 |
0x0000 0000 |
0x01C |
0x0540 001C |
|
RW |
32 |
0x0000 0000 |
0x020 |
0x0540 0020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x0540 0024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x0540 0028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
0x0540 002C |
|
RW |
32 |
0x0000 0000 |
0x030 |
0x0540 0030 |
|
RW |
32 |
0x0000 0000 |
0x034 |
0x0540 0034 |
|
RW |
32 |
0x0000 0000 |
0x038 |
0x0540 0038 |
|
RW |
32 |
0x0000 0000 |
0x03C |
0x0540 003C |
|
RO |
32 |
0x0000 0000 |
0x040 |
0x0540 0040 |
Address offset |
0x000 |
||
Physical address |
0x0540 0000 |
Instance |
icb_clock_mux_w |
0x0504 0000 |
icb_clock_mux_e |
||
0x0520 0000 |
icb_clock_mux_ne |
||
0x0510 0000 |
icb_clock_mux_nw |
||
0x0502 0000 |
icb_clock_mux_se |
||
0x0501 0000 |
icb_clock_mux_sw |
||
Description |
This is a compulsory register for all SCB slaves and must
be at the same offset in all slaves to facilitate global soft reset of all
SCB registers with a single broadcast write from the SCB master. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:16 |
BLOCKID |
This returns the block type and chip location. (IO SCB bus
only) |
RO |
0x0000 |
|
|
|
Read 0x0000 |
[block_address_IOSCB_ICB] |
|
|
15:9 |
Reserved |
|
RO |
0x00 |
|
8 |
PERIPH |
This asserts the functional reset of the block. It is
asserted at power up. When written is stays asserted until written to 0. |
WO |
0 |
|
|
|
Write 0 |
[scb_periph_not_in_soft_reset_IOSCB_ICB] |
|
|
|
|
Write 1 |
[scb_periph_reset_IOSCB_ICB] |
|
|
7:2 |
Reserved |
|
RO |
0x00 |
|
1 |
V_MAP |
This when asserted resets all the register bits apart from
the non-volatile registers, the bit self clears. i.e. is similar to a W1P bit
|
WO |
0 |
|
|
|
Write 0 |
[scb_v_regs_not_in_soft_reset_IOSCB_ICB] |
|
|
|
|
Write 1 |
[scb_v_regs_reset_IOSCB_ICB] |
|
|
0 |
NV_MAP |
This when asserted resets all the non-volatile register
bits e.g. RW-P bits, the bit self clears i.e. is similar to a W1P bit |
WO |
0 |
|
|
|
Write 0 |
[scb_nv_regs_not_in_soft_reset_IOSCB_ICB] |
|
|
|
|
Write 1 |
[scb_nv_regs_reset_IOSCB_ICB] |
|
Address offset |
0x004 |
||
Physical address |
0x0540 0004 |
Instance |
icb_clock_mux_w |
0x0504 0004 |
icb_clock_mux_e |
||
0x0520 0004 |
icb_clock_mux_ne |
||
0x0510 0004 |
icb_clock_mux_nw |
||
0x0502 0004 |
icb_clock_mux_se |
||
0x0501 0004 |
icb_clock_mux_sw |
||
Description |
Input Clk Mux selection (4 mux<3:0>) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23:0 |
dpc_nmux_sel0 |
Input Clk Mux selection. 4 muxes in this group. 6 bits per
mux to select input clock: bocw<1:0>, boccw<1:0>,
crnfdrcw<7:0>, crnfdrccw<7:0>, pio<5:0>,
gb<1:0>,eip<1:0>,tieoff |
RW |
0xFF FFFF |
Address offset |
0x008 |
||
Physical address |
0x0540 0008 |
Instance |
icb_clock_mux_w |
0x0504 0008 |
icb_clock_mux_e |
||
0x0520 0008 |
icb_clock_mux_ne |
||
0x0510 0008 |
icb_clock_mux_nw |
||
0x0502 0008 |
icb_clock_mux_se |
||
0x0501 0008 |
icb_clock_mux_sw |
||
Description |
Input Clk Mux selection (4 mux<7:4>) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23:0 |
dpc_nmux_sel1 |
Input Clk Mux selection. 4 muxes in this group. 6 bits per
mux to select input clock: bocw<1:0>, boccw<1:0>,
crnfdrcw<7:0>, crnfdrccw<7:0>, pio<5:0>,
gb<1:0>,eip<1:0>,tieoff |
RW |
0xFF FFFF |
Address offset |
0x00C |
||
Physical address |
0x0540 000C |
Instance |
icb_clock_mux_w |
0x0504 000C |
icb_clock_mux_e |
||
0x0520 000C |
icb_clock_mux_ne |
||
0x0510 000C |
icb_clock_mux_nw |
||
0x0502 000C |
icb_clock_mux_se |
||
0x0501 000C |
icb_clock_mux_sw |
||
Description |
Input Clk Mux selection (4 mux<11:8>) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23:0 |
dpc_nmux_sel2 |
Input Clk Mux selection. 4 muxes in this group. 6 bits per
mux to select input clock: bocw<1:0>, boccw<1:0>,
crnfdrcw<7:0>, crnfdrccw<7:0>, pio<5:0>,
gb<1:0>,eip<1:0>,tieoff |
RW |
0xFF FFFF |
Address offset |
0x010 |
||
Physical address |
0x0540 0010 |
Instance |
icb_clock_mux_w |
0x0504 0010 |
icb_clock_mux_e |
||
0x0520 0010 |
icb_clock_mux_ne |
||
0x0510 0010 |
icb_clock_mux_nw |
||
0x0502 0010 |
icb_clock_mux_se |
||
0x0501 0010 |
icb_clock_mux_sw |
||
Description |
Output Clk Mux selection (6 mux<5:0>) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:30 |
Reserved |
|
RO |
0x0 |
29:0 |
dpc_gb_sel0 |
Output Clk Mux selection. 6 muxes in this group. 5 bits
per mux to select gmx<1:0>, dv<3:0>, nclk<11:0> |
RW |
0x0000 0000 |
Address offset |
0x014 |
||
Physical address |
0x0540 0014 |
Instance |
icb_clock_mux_w |
0x0504 0014 |
icb_clock_mux_e |
||
0x0520 0014 |
icb_clock_mux_ne |
||
0x0510 0014 |
icb_clock_mux_nw |
||
0x0502 0014 |
icb_clock_mux_se |
||
0x0501 0014 |
icb_clock_mux_sw |
||
Description |
Output Clk Mux selection (6 mux<11:6>) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:30 |
Reserved |
|
RO |
0x0 |
29:0 |
dpc_gb_sel1 |
Output Clk Mux selection. 6 muxes in this group. 5 bits
per mux to select gmx<1:0>, dv<3:0>, nclk<11:0> |
RW |
0x0000 0000 |
Address offset |
0x018 |
||
Physical address |
0x0540 0018 |
Instance |
icb_clock_mux_w |
0x0504 0018 |
icb_clock_mux_e |
||
0x0520 0018 |
icb_clock_mux_ne |
||
0x0510 0018 |
icb_clock_mux_nw |
||
0x0502 0018 |
icb_clock_mux_se |
||
0x0501 0018 |
icb_clock_mux_sw |
||
Description |
Mux selection for 12 clock outputs stop feature |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23:0 |
dpc_stop_sel |
Mux selection for 12 clock outputs stop feature. 12 muxes.
2 bits per mux to select on, off, stop1, stop2. |
RW |
0x00 0000 |
Address offset |
0x01C |
||
Physical address |
0x0540 001C |
Instance |
icb_clock_mux_w |
0x0504 001C |
icb_clock_mux_e |
||
0x0520 001C |
icb_clock_mux_ne |
||
0x0510 001C |
icb_clock_mux_nw |
||
0x0502 001C |
icb_clock_mux_se |
||
0x0501 001C |
icb_clock_mux_sw |
||
Description |
Input Bank Clk Mux selection |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:12 |
Reserved |
|
RO |
0x0 0000 |
11:6 |
dpc_bo_cw_sel |
Input Bank Clk Mux selection. 2 muxes. 3 bits per mux to
select bclk<5:0> from clk wise(cw), tieoff |
RW |
0x00 |
5:0 |
dpc_bo_ccw_sel |
Input Bank Clk Mux selection. 2 muxes. 3 bits per mux to
select bclk<5:0> from counter clk wise(ccw), tieoff |
RW |
0x00 |
Address offset |
0x020 |
||
Physical address |
0x0540 0020 |
Instance |
icb_clock_mux_w |
0x0504 0020 |
icb_clock_mux_e |
||
0x0520 0020 |
icb_clock_mux_ne |
||
0x0510 0020 |
icb_clock_mux_nw |
||
0x0502 0020 |
icb_clock_mux_se |
||
0x0501 0020 |
icb_clock_mux_sw |
||
Description |
Bank Clk Feedback selection |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
Reserved |
|
RO |
0x0000 |
15:8 |
dpc_fb_cw_sel |
Bank Clk Feedback selection. 4 muxes. 2 bits per mux to
select div1 (del ir non-del), divn or nclk for Bank Clock Bridge clk wise
(cw) |
RW |
0x00 |
7:0 |
dpc_fb_ccw_sel |
Bank Clk Feedback selection. 4 muxes. 2 bits per mux to
select div1 (del ir non-del), divn or nclk for Bank Clock Bridge counter clk
wise (ccw) |
RW |
0x00 |
Address offset |
0x024 |
||
Physical address |
0x0540 0024 |
Instance |
icb_clock_mux_w |
0x0504 0024 |
icb_clock_mux_e |
||
0x0520 0024 |
icb_clock_mux_ne |
||
0x0510 0024 |
icb_clock_mux_nw |
||
0x0502 0024 |
icb_clock_mux_se |
||
0x0501 0024 |
icb_clock_mux_sw |
||
Description |
Glitchless mux Related |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
Reserved |
|
RO |
0x000 0000 |
5:4 |
dpc_gm_mode |
Select glitchless mode simple for running clocks or complex
for unknown state of clock. 2 glitchless muxes. 1 bit per mux. |
RW |
0x0 |
3:2 |
dpc_gm_selb |
Glitchless mux input b selection. 2 muxes. 1 bit per mux
to select dv<3:2>, nclk<3:2> |
RW |
0x0 |
1:0 |
dpc_gm_sela |
Glitchless mux input a selection. 2 muxes. 1 bit per mux
to select dv<1:0>, nclk<1:0> |
RW |
0x0 |
Address offset |
0x028 |
||
Physical address |
0x0540 0028 |
Instance |
icb_clock_mux_w |
0x0504 0028 |
icb_clock_mux_e |
||
0x0520 0028 |
icb_clock_mux_ne |
||
0x0510 0028 |
icb_clock_mux_nw |
||
0x0502 0028 |
icb_clock_mux_se |
||
0x0501 0028 |
icb_clock_mux_sw |
||
Description |
Divider Related |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
Reserved |
|
RO |
0x0000 |
15:12 |
dpc_divone_sel |
Select delay or no-delay for bclk feedback bridging. 4
muxes. 1 bit per mux |
RW |
0x0 |
11:0 |
dpc_div |
Select divide ratio (2,3.5,4,5) of nclk<7:4>. 4
dividers. 3 bits per divider |
RW |
0x000 |
Address offset |
0x02C |
||
Physical address |
0x0540 002C |
Instance |
icb_clock_mux_w |
0x0504 002C |
icb_clock_mux_e |
||
0x0520 002C |
icb_clock_mux_ne |
||
0x0510 002C |
icb_clock_mux_nw |
||
0x0502 002C |
icb_clock_mux_se |
||
0x0501 002C |
icb_clock_mux_sw |
||
Description |
Delay Cell Related |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:28 |
dpc_dly_wide |
Delay setting fo wide range mode. 4 delay cells. 1 bit per
block |
RW |
0x0 |
27:0 |
dpc_dly_sel |
Delay setting for 4 delay cells. 7 bits per delay chain. |
RW |
0x000 0000 |
Address offset |
0x030 |
||
Physical address |
0x0540 0030 |
Instance |
icb_clock_mux_w |
0x0504 0030 |
icb_clock_mux_e |
||
0x0520 0030 |
icb_clock_mux_ne |
||
0x0510 0030 |
icb_clock_mux_nw |
||
0x0502 0030 |
icb_clock_mux_se |
||
0x0501 0030 |
icb_clock_mux_sw |
||
Description |
CCW bank mux input selection |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:30 |
Reserved |
|
RO |
0x0 |
29:0 |
dpc_bi2_sel |
CCW bank mux input selection. 6 muxes. 5 bits per mux |
RW |
0x0000 0000 |
Address offset |
0x034 |
||
Physical address |
0x0540 0034 |
Instance |
icb_clock_mux_w |
0x0504 0034 |
icb_clock_mux_e |
||
0x0520 0034 |
icb_clock_mux_ne |
||
0x0510 0034 |
icb_clock_mux_nw |
||
0x0502 0034 |
icb_clock_mux_se |
||
0x0501 0034 |
icb_clock_mux_sw |
||
Description |
CW bank mux input selection |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:30 |
Reserved |
|
RO |
0x0 |
29:0 |
dpc_bi1_sel |
CW bank mux input selection. 6 muxes. 5 bits per mux |
RW |
0x0000 0000 |
Address offset |
0x038 |
||
Physical address |
0x0540 0038 |
Instance |
icb_clock_mux_w |
0x0504 0038 |
icb_clock_mux_e |
||
0x0520 0038 |
icb_clock_mux_ne |
||
0x0510 0038 |
icb_clock_mux_nw |
||
0x0502 0038 |
icb_clock_mux_se |
||
0x0501 0038 |
icb_clock_mux_sw |
||
Description |
spare pc bits |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
Reserved |
|
RO |
0x00 0000 |
9:0 |
spare_icb |
spare pc bits |
RW |
0x000 |
Address offset |
0x03C |
||
Physical address |
0x0540 003C |
Instance |
icb_clock_mux_w |
0x0504 003C |
icb_clock_mux_e |
||
0x0520 003C |
icb_clock_mux_ne |
||
0x0510 003C |
icb_clock_mux_nw |
||
0x0502 003C |
icb_clock_mux_se |
||
0x0501 003C |
icb_clock_mux_sw |
||
Description |
DFT write registers |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:25 |
Reserved |
|
RO |
0x00 |
24:1 |
scb_dft_spare_rw |
DFT spare bits |
RW |
0x00 0000 |
0 |
scb_dft_dlytst_en |
enable delay test |
RW |
0 |
Address offset |
0x040 |
||
Physical address |
0x0540 0040 |
Instance |
icb_clock_mux_w |
0x0504 0040 |
icb_clock_mux_e |
||
0x0520 0040 |
icb_clock_mux_ne |
||
0x0510 0040 |
icb_clock_mux_nw |
||
0x0502 0040 |
icb_clock_mux_se |
||
0x0501 0040 |
icb_clock_mux_sw |
||
Description |
DFT read registers |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
Reserved |
|
RO |
0x0000 |
15:4 |
scb_dft_spare_ro |
DFT spare bits |
RO |
0x000 |
3:2 |
scb_dft_dlytstb |
delay compare |
RO |
0x0 |
1:0 |
scb_dft_dlytst |
delay compare |
RO |
0x0 |
IOSCB_ICB has no
common memories.