Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

SOFT_RESET

RW

32

0x0000 0000

0x000

IOC_REG0

RW

32

0x0000 0000

0x004

IOC_REG1

RO

32

0x0000 0000

0x008

IOC_REG2

RO

32

0x0000 0000

0x00C

IOC_REG3

RW

32

0x0000 0000

0x010

IOC_REG4

RW

32

0x0000 0000

0x014

IOC_REG5

RO

32

0x0000 0000

0x018

IOC_REG6

RW

32

0x0000 0000

0x01C

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0C00 1000

IOC_REG0

RW

32

0x0000 0000

0x004

0x0C00 1004

IOC_REG1

RO

32

0x0000 0000

0x008

0x0C00 1008

IOC_REG2

RO

32

0x0000 0000

0x00C

0x0C00 100C

IOC_REG3

RW

32

0x0000 0000

0x010

0x0C00 1010

IOC_REG4

RW

32

0x0000 0000

0x014

0x0C00 1014

IOC_REG5

RO

32

0x0000 0000

0x018

0x0C00 1018

IOC_REG6

RW

32

0x0000 0000

0x01C

0x0C00 101C

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0C00 2000

IOC_REG0

RW

32

0x0000 0000

0x004

0x0C00 2004

IOC_REG1

RO

32

0x0000 0000

0x008

0x0C00 2008

IOC_REG2

RO

32

0x0000 0000

0x00C

0x0C00 200C

IOC_REG3

RW

32

0x0000 0000

0x010

0x0C00 2010

IOC_REG4

RW

32

0x0000 0000

0x014

0x0C00 2014

IOC_REG5

RO

32

0x0000 0000

0x018

0x0C00 2018

IOC_REG6

RW

32

0x0000 0000

0x01C

0x0C00 201C

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0C00 4000

IOC_REG0

RW

32

0x0000 0000

0x004

0x0C00 4004

IOC_REG1

RO

32

0x0000 0000

0x008

0x0C00 4008

IOC_REG2

RO

32

0x0000 0000

0x00C

0x0C00 400C

IOC_REG3

RW

32

0x0000 0000

0x010

0x0C00 4010

IOC_REG4

RW

32

0x0000 0000

0x014

0x0C00 4014

IOC_REG5

RO

32

0x0000 0000

0x018

0x0C00 4018

IOC_REG6

RW

32

0x0000 0000

0x01C

0x0C00 401C

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0C00 8000

IOC_REG0

RW

32

0x0000 0000

0x004

0x0C00 8004

IOC_REG1

RO

32

0x0000 0000

0x008

0x0C00 8008

IOC_REG2

RO

32

0x0000 0000

0x00C

0x0C00 800C

IOC_REG3

RW

32

0x0000 0000

0x010

0x0C00 8010

IOC_REG4

RW

32

0x0000 0000

0x014

0x0C00 8014

IOC_REG5

RO

32

0x0000 0000

0x018

0x0C00 8018

IOC_REG6

RW

32

0x0000 0000

0x01C

0x0C00 801C

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0C04 0000

IOC_REG0

RW

32

0x0000 0000

0x004

0x0C04 0004

IOC_REG1

RO

32

0x0000 0000

0x008

0x0C04 0008

IOC_REG2

RO

32

0x0000 0000

0x00C

0x0C04 000C

IOC_REG3

RW

32

0x0000 0000

0x010

0x0C04 0010

IOC_REG4

RW

32

0x0000 0000

0x014

0x0C04 0014

IOC_REG5

RO

32

0x0000 0000

0x018

0x0C04 0018

IOC_REG6

RW

32

0x0000 0000

0x01C

0x0C04 001C

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0C40 0000

IOC_REG0

RW

32

0x0000 0000

0x004

0x0C40 0004

IOC_REG1

RO

32

0x0000 0000

0x008

0x0C40 0008

IOC_REG2

RO

32

0x0000 0000

0x00C

0x0C40 000C

IOC_REG3

RW

32

0x0000 0000

0x010

0x0C40 0010

IOC_REG4

RW

32

0x0000 0000

0x014

0x0C40 0014

IOC_REG5

RO

32

0x0000 0000

0x018

0x0C40 0018

IOC_REG6

RW

32

0x0000 0000

0x01C

0x0C40 001C

Address offset

0x000

Physical address

0x0C04 0000

Instance

pvt_bank_0_nec

0x0C40 0000

pvt_bank_1_swc

0x0C00 4000

pvt_bank_7_wi

0x0C00 1000

pvt_bank_9_sei

0x0C00 2000

pvt_bank_0_nwi

0x0C00 8000

pvt_bank_8_nei

Description

This is a compulsory register for all SCB slaves and must be at the same offset in all slaves to facilitate global soft reset of all SCB registers with a single broadcast write from the SCB master.

Type

RW

31:16

BLOCKID

This returns the block type and chip location. (IO SCB bus only)

RO

0x0000

Read 0x0000

[block_address_IOSCB_IO_CALIB]

15:9

Reserved

RO
Rreturns0s

0x00

8

PERIPH

This asserts the functional reset of the block. It is asserted at power up. When written is stays asserted until written to 0.

WO

0

Write 0

[scb_periph_not_in_soft_reset_IOSCB_IO_CALIB]

Write 1

[scb_periph_reset_IOSCB_IO_CALIB]

7:2

Reserved

RO
Rreturns0s

0x00

1

V_MAP

This when asserted resets all the register bits apart from the non-volatile registers, the bit self clears. i.e. is similar to a W1P bit

WO

0

Write 0

[scb_v_regs_not_in_soft_reset_IOSCB_IO_CALIB]

Write 1

[scb_v_regs_reset_IOSCB_IO_CALIB]

0

NV_MAP

This when asserted resets all the non-volatile register bits e.g. RW-P bits, the bit self clears i.e. is similar to a W1P bit

WO

0

Write 0

[scb_nv_regs_not_in_soft_reset_IOSCB_IO_CALIB]

Write 1

[scb_nv_regs_reset_IOSCB_IO_CALIB]

Address offset

0x004

Physical address

0x0C04 0004

Instance

pvt_bank_0_nec

0x0C40 0004

pvt_bank_1_swc

0x0C00 4004

pvt_bank_7_wi

0x0C00 1004

pvt_bank_9_sei

0x0C00 2004

pvt_bank_0_nwi

0x0C00 8004

pvt_bank_8_nei

Description

IO calib control register0

Type

RW

31:26

Reserved

RO

0x00

25:24

reg_diffr_vsel

RW

0x0

23

reg_calib_move_diffr

RW

0

22:19

reg_diffr

RW

0x0

18

reg_calib_move_ncode

RW

0

17

reg_calib_move_pcode

RW

0

16

reg_calib_direction

RW

0

15

reg_calib_load

RW

0

14

reg_calib_lock

RW

0

13

reg_calib_start

RW

0

12

reg_calib_trim

RW

0

11:6

reg_ncode

RW

0x00

5:0

reg_pcode

RW

0x00

Address offset

0x008

Physical address

0x0C04 0008

Instance

pvt_bank_0_nec

0x0C40 0008

pvt_bank_1_swc

0x0C00 4008

pvt_bank_7_wi

0x0C00 1008

pvt_bank_9_sei

0x0C00 2008

pvt_bank_0_nwi

0x0C00 8008

pvt_bank_8_nei

Description

IO calib control register1

Type

RO

31:23

Reserved

RO

0x000

22

sro_diffr_calib_intrpt

RO

0

21

sro_diffr_calib_status

RO

0

20

sro_diffr_comp_sel

RO

0

19

sro_diffr_comp_en

RO

0

18

sro_diffr_comp_out

RO

0

17

sro_diffr_ioen_out

RO

0

16

sro_diffr_power_on

RO

0

15:12

sro_ref_diffr

RO

0x0

11:8

sro_diffr

RO

0x0

7

sro_comp_en

RO

0

6

sro_comp_sel

RO

0

5

sro_power_on

RO

0

4

sro_ioen_out

RO

0

3

sro_calib_intrpt

RO

0

2

sro_calib_status

RO

0

1

sro_code_done_n

RO

0

0

sro_code_done_p

RO

0

Address offset

0x00C

Physical address

0x0C04 000C

Instance

pvt_bank_0_nec

0x0C40 000C

pvt_bank_1_swc

0x0C00 400C

pvt_bank_7_wi

0x0C00 100C

pvt_bank_9_sei

0x0C00 200C

pvt_bank_0_nwi

0x0C00 800C

pvt_bank_8_nei

Description

IO calib control register2

Type

RO

31:29

Reserved

RO

0x0

28

sro_comp_out

RO

0

27:21

sro_ref_ncode

RO

0x00

20:14

sro_ref_pcode

RO

0x00

13:7

sro_ncode

RO

0x00

6:0

sro_pcode

RO

0x00

Address offset

0x010

Physical address

0x0C04 0010

Instance

pvt_bank_0_nec

0x0C40 0010

pvt_bank_1_swc

0x0C00 4010

pvt_bank_7_wi

0x0C00 1010

pvt_bank_9_sei

0x0C00 2010

pvt_bank_0_nwi

0x0C00 8010

pvt_bank_8_nei

Description

IO calib control register3

Type

RW

31:23

Reserved

RO

0x000

22

reg_calib_foffset_dir

RW

0

21

reg_calib_roffset_dir

RW

0

20

reg_calib_move_slewf

RW

0

19

reg_calib_move_slewr

RW

0

18

reg_calib_noffset_dir

RW

0

17:12

reg_calib_noffset

RW

0x00

11

reg_calib_poffset_dir

RW

0

10:5

reg_calib_poffset

RW

0x00

4

reg_calib_doffset_dir

RW

0

3:0

reg_calib_doffset

RW

0x0

Address offset

0x014

Physical address

0x0C04 0014

Instance

pvt_bank_0_nec

0x0C40 0014

pvt_bank_1_swc

0x0C00 4014

pvt_bank_7_wi

0x0C00 1014

pvt_bank_9_sei

0x0C00 2014

pvt_bank_0_nwi

0x0C00 8014

pvt_bank_8_nei

Description

IO calib control register4

Type

RW

31

Reserved

RO

0

30

sro_slew_power_on

RO

0

29

sro_slew_ioen_out

RO

0

28

sro_slew_comp_sel

RO

0

27

sro_slew_comp_en

RO

0

26

sro_slew_comp_out

RO

0

25

sro_slew_status

RO

0

24

sro_slew_intrpt

RO

0

23:18

reg_slewf

RW

0x00

17:12

reg_slewr

RW

0x00

11:6

reg_foffset

RW

0x00

5:0

reg_roffset

RW

0x00

Address offset

0x018

Physical address

0x0C04 0018

Instance

pvt_bank_0_nec

0x0C40 0018

pvt_bank_1_swc

0x0C00 4018

pvt_bank_7_wi

0x0C00 1018

pvt_bank_9_sei

0x0C00 2018

pvt_bank_0_nwi

0x0C00 8018

pvt_bank_8_nei

Description

IO calib control register5

Type

RO

31:18

Reserved

RO

0x0000

17:6

sro_ref_slewf

RO

0x000

5:0

sro_ref_slewr

RO

0x00

Address offset

0x01C

Physical address

0x0C04 001C

Instance

pvt_bank_0_nec

0x0C40 001C

pvt_bank_1_swc

0x0C00 401C

pvt_bank_7_wi

0x0C00 101C

pvt_bank_9_sei

0x0C00 201C

pvt_bank_0_nwi

0x0C00 801C

pvt_bank_8_nei

Description

IO calibr control resgister6

Type

RW

31:3

reserve08

RO

0x0000 0000

2:1

reg_calib_clkdiv

RW

0x0

0

reg_calib_reset

RW

0