This section
provides information on the IOSCB_IO_CALIB_SGMII Module Instance. Each of the
module registers is described below.
Return to mpfs_ioscb_memmap_dri
|
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
|
RW |
32 |
0x0000 0000 |
0x00 |
0x0E80 0000 |
|
|
RW |
32 |
0x0000 0000 |
0x04 |
0x0E80 0004 |
|
|
RO |
32 |
0x0000 0000 |
0x08 |
0x0E80 0008 |
|
|
RO |
32 |
0x0000 0000 |
0x0C |
0x0E80 000C |
|
|
RW |
32 |
0x0000 0000 |
0x10 |
0x0E80 0010 |
|
|
RO |
32 |
0x0000 0000 |
0x14 |
0x0E80 0014 |
|
|
RO |
32 |
0x0000 0000 |
0x18 |
0x0E80 0018 |
|
|
RW |
32 |
0x0000 0000 |
0x1C |
0x0E80 001C |
|
Address offset |
0x00 |
||
|
Physical address |
0x0E80 0000 |
Instance |
pvt_eth |
|
Description |
This is a compulsory register for all SCB slaves and must
be at the same offset in all slaves to facilitate global soft reset of all
SCB registers with a single broadcast write from the SCB master. |
||
|
Type |
RW |
||
|
Bits |
Field Name |
Description |
Type |
Reset |
|
|
31:16 |
BLOCKID |
This returns the block type and chip location. (IO SCB bus
only) |
RO |
0x0000 |
|
|
|
|
Read 0x0000 |
[block_address_IOSCB_IO_CALIB_SGMII] |
|
|
|
15:9 |
Reserved |
|
RO |
0x00 |
|
|
8 |
PERIPH |
This asserts the functional reset of the block. It is
asserted at power up. When written is stays asserted until written to 0. |
WO |
0 |
|
|
|
|
Write 0 |
[scb_periph_not_in_soft_reset_IOSCB_IO_CALIB_SGMII] |
|
|
|
|
|
Write 1 |
[scb_periph_reset_IOSCB_IO_CALIB_SGMII] |
|
|
|
7:2 |
Reserved |
|
RO |
0x00 |
|
|
1 |
V_MAP |
This when asserted resets all the register bits apart from
the non-volatile registers, the bit self clears. i.e. is similar to a W1P bit
|
WO |
0 |
|
|
|
|
Write 0 |
[scb_v_regs_not_in_soft_reset_IOSCB_IO_CALIB_SGMII] |
|
|
|
|
|
Write 1 |
[scb_v_regs_reset_IOSCB_IO_CALIB_SGMII] |
|
|
|
0 |
NV_MAP |
This when asserted resets all the non-volatile register
bits e.g. RW-P bits, the bit self clears i.e. is similar to a W1P bit |
WO |
0 |
|
|
|
|
Write 0 |
[scb_nv_regs_not_in_soft_reset_IOSCB_IO_CALIB_SGMII] |
|
|
|
|
|
Write 1 |
[scb_nv_regs_reset_IOSCB_IO_CALIB_SGMII] |
|
|
|
Address offset |
0x04 |
||
|
Physical address |
0x0E80 0004 |
Instance |
pvt_eth |
|
Description |
IO calib control register0 |
||
|
Type |
RW |
||
|
Bits |
Field Name |
Description |
Type |
Reset |
|
31:26 |
Reserved |
|
RO |
0x00 |
|
25:24 |
reg_diffr_vsel |
|
RW |
0x0 |
|
23 |
reg_calib_move_diffr |
|
RW |
0 |
|
22:19 |
reg_diffr |
|
RW |
0x0 |
|
18 |
reg_calib_move_ncode |
|
RW |
0 |
|
17 |
reg_calib_move_pcode |
|
RW |
0 |
|
16 |
reg_calib_direction |
|
RW |
0 |
|
15 |
reg_calib_load |
|
RW |
0 |
|
14 |
reg_calib_lock |
|
RW |
0 |
|
13 |
reg_calib_start |
|
RW |
0 |
|
12 |
reg_calib_trim |
|
RW |
0 |
|
11:6 |
reg_ncode |
|
RW |
0x00 |
|
5:0 |
reg_pcode |
|
RW |
0x00 |
|
Address offset |
0x08 |
||
|
Physical address |
0x0E80 0008 |
Instance |
pvt_eth |
|
Description |
IO calib control register1 |
||
|
Type |
RO |
||
|
Bits |
Field Name |
Description |
Type |
Reset |
|
31:23 |
Reserved |
|
RO |
0x000 |
|
22 |
sro_diffr_calib_intrpt |
|
RO |
0 |
|
21 |
sro_diffr_calib_status |
|
RO |
0 |
|
20 |
sro_diffr_comp_sel |
|
RO |
0 |
|
19 |
sro_diffr_comp_en |
|
RO |
0 |
|
18 |
sro_diffr_comp_out |
|
RO |
0 |
|
17 |
sro_diffr_ioen_out |
|
RO |
0 |
|
16 |
sro_diffr_power_on |
|
RO |
0 |
|
15:12 |
sro_ref_diffr |
|
RO |
0x0 |
|
11:8 |
sro_diffr |
|
RO |
0x0 |
|
7 |
sro_comp_en |
|
RO |
0 |
|
6 |
sro_comp_sel |
|
RO |
0 |
|
5 |
sro_power_on |
|
RO |
0 |
|
4 |
sro_ioen_out |
|
RO |
0 |
|
3 |
sro_calib_intrpt |
|
RO |
0 |
|
2 |
sro_calib_status |
|
RO |
0 |
|
1 |
sro_code_done_n |
|
RO |
0 |
|
0 |
sro_code_done_p |
|
RO |
0 |
|
Address offset |
0x0C |
||
|
Physical address |
0x0E80 000C |
Instance |
pvt_eth |
|
Description |
IO calib control register2 |
||
|
Type |
RO |
||
|
Bits |
Field Name |
Description |
Type |
Reset |
|
31:29 |
Reserved |
|
RO |
0x0 |
|
28 |
sro_comp_out |
|
RO |
0 |
|
27:21 |
sro_ref_ncode |
|
RO |
0x00 |
|
20:14 |
sro_ref_pcode |
|
RO |
0x00 |
|
13:7 |
sro_ncode |
|
RO |
0x00 |
|
6:0 |
sro_pcode |
|
RO |
0x00 |
|
Address offset |
0x10 |
||
|
Physical address |
0x0E80 0010 |
Instance |
pvt_eth |
|
Description |
IO calib control register3 |
||
|
Type |
RW |
||
|
Bits |
Field Name |
Description |
Type |
Reset |
|
31:19 |
Reserved |
|
RO |
0x0000 |
|
18 |
reg_calib_noffset_dir |
|
RW |
0 |
|
17:12 |
reg_calib_noffset |
|
RW |
0x00 |
|
11 |
reg_calib_poffset_dir |
|
RW |
0 |
|
10:5 |
reg_calib_poffset |
|
RW |
0x00 |
|
4 |
reg_calib_doffset_dir |
|
RW |
0 |
|
3:0 |
reg_calib_doffset |
|
RW |
0x0 |
|
Address offset |
0x14 |
||
|
Physical address |
0x0E80 0014 |
Instance |
pvt_eth |
|
Description |
IO calib control register4 |
||
|
Type |
RO |
||
|
Bits |
Field Name |
Description |
Type |
Reset |
|
31:0 |
Reserved |
|
RO |
0x0000 0000 |
|
Address offset |
0x18 |
||
|
Physical address |
0x0E80 0018 |
Instance |
pvt_eth |
|
Description |
IO calib control register5 |
||
|
Type |
RO |
||
|
Bits |
Field Name |
Description |
Type |
Reset |
|
31:0 |
Reserved |
|
RO |
0x0000 0000 |
|
Address offset |
0x1C |
||
|
Physical address |
0x0E80 001C |
Instance |
pvt_eth |
|
Description |
IO calibr control resgister6 |
||
|
Type |
RW |
||
|
Bits |
Field Name |
Description |
Type |
Reset |
|
31:3 |
Reserved |
|
RO |
0x0000 0000 |
|
2:1 |
reg_calib_clkdiv |
|
RW |
0x0 |
|
0 |
reg_calib_reset |
|
RW |
0 |
IOSCB_IO_CALIB_SGMII
has no common memories.