Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x00

0x0E00 1000

PLL_CTRL

RW

32

0x0000 10C6

0x04

0x0E00 1004

PLL_REF_FB

RW

32

0x0000 0000

0x08

0x0E00 1008

PLL_FRACN

RW

32

0x0000 0000

0x0C

0x0E00 100C

PLL_DIV_0_1

RW

32

0x0000 0000

0x10

0x0E00 1010

PLL_DIV_2_3

RW

32

0x0000 0000

0x14

0x0E00 1014

PLL_CTRL2

RW

32

0x0000 1006

0x18

0x0E00 1018

PLL_CAL

RW

32

0x0000 0000

0x1C

0x0E00 101C

PLL_PHADJ

RW

32

0x0000 4001

0x20

0x0E00 1020

SSCG_REG_0

RW

32

0x0000 0000

0x24

0x0E00 1024

SSCG_REG_1

RW

32

0x0000 0000

0x28

0x0E00 1028

SSCG_REG_2

RW

32

0x0000 0000

0x2C

0x0E00 102C

SSCG_REG_3

RW

32

0x0000 0000

0x30

0x0E00 1030

Address offset

0x00

Physical address

0x0E00 1000

Instance

pll_mss

Description

This is a compulsory register for all SCB slaves and must be at the same offset in all slaves to facilitate global soft reset of all SCB registers with a single broadcast write from the SCB master.

Type

RW

31:16

BLOCKID

This returns the block type and chip location. (IO SCB bus only)

RO

0x0000

Read 0x0000

[block_address_IOSCB_PLL_MSS]

15:9

Reserved

RO
Rreturns0s

0x00

8

PERIPH

This asserts the functional reset of the block. It is asserted at power up. When written is stays asserted until written to 0.

WO

0

Write 0

[scb_periph_not_in_soft_reset_IOSCB_PLL_MSS]

Write 1

[scb_periph_reset_IOSCB_PLL_MSS]

7:2

Reserved

RO
Rreturns0s

0x00

1

V_MAP

This when asserted resets all the register bits apart from the non-volatile registers, the bit self clears. i.e. is similar to a W1P bit

WO

0

Write 0

[scb_v_regs_not_in_soft_reset_IOSCB_PLL_MSS]

Write 1

[scb_v_regs_reset_IOSCB_PLL_MSS]

0

NV_MAP

This when asserted resets all the non-volatile register bits e.g. RW-P bits, the bit self clears i.e. is similar to a W1P bit

WO

0

Write 0

[scb_nv_regs_not_in_soft_reset_IOSCB_PLL_MSS]

Write 1

[scb_nv_regs_reset_IOSCB_PLL_MSS]

Address offset

0x04

Physical address

0x0E00 1004

Instance

pll_mss

Description

PLL control register

Type

RW

31

LOCK_B

Inversion of LOCK (bit 25)

RO

0

30

Reserved

RO

0

29

UNLOCK_INT

pll unlock interrupt signal

RW
W1toClr

0

28

LOCK_INT

pll lock interrupt signal

RW
W1toClr

0

27

UNLOCK_INT_EN

Enable pll unlock interrupt

RW

0

26

LOCK_INT_EN

Enable pll lock interrupt

RW

0

25

LOCK

Lock detect output

LOCK goes high 2LOCKCOUNTSEL PFD cycles after the last cycle slip

LOCK goes low if two cycle slips are detected within 2LOCKCOUNTSEL PFD cycles

RO

0

24

LP_REQUIRES_LOCK

RW

0

23:20

REG_BYPASSPOST

 Bypass mux control for post divider output

One-hot mux selection for each post divider

1'b0 = Select post divider output to drive PLL_OUT

1'b1 = Select RFCLK or FBCLK (depending on BYPCKSEL) to drive PLL_OUT

RW

0x0

19:16

REG_BYPASSPRE

 Bypass mux control for input to post divider

One-hot mux selection for each post divider

1'b0 = Select VCO output as input to post divider

1'b1 = Select RFCLK or FBCLK (depending on BYPCKSEL) as input to post divider

RW

0x0

15:13

Reserved

RO

0x0

12

REG_BYPASS_GO_B

 Enable BYPASSPRE and BYAPSSPOST signals (active low)

RW

1

11:8

BYPCK_SEL

 MUX to select RFCLK or FBCLK for bypass mode

One-hot mux selection for each post divider

1'b0 = Select RFCLK for bypass mode

1'b1 = Select FBCLK for bypass mode

RW

0x0

7

RESETONLOCK

 Control signal to force a post divide reset on the rising edge of LOCK

1'b0 - Outputs are enabled based only on POSTDIVEN

1'b1 - Outputs are held low if LOCK is low, and reset on the rising edge of LOCK

RW

1

6

REG_RFCLK_SEL

 Reference clock select

1'b0 - Selects RFCKL[0] as reference clock for PLL

1'b1 - Selects RFCLK[1] as reference clock for PLL

RW

1

5

REG_DIVQ3_EN

Post divider 3 enable (glitchless start/stop)

RW

0

4

REG_DIVQ2_EN

Post divider 2 enable (glitchless start/stop)

RW

0

3

REG_DIVQ1_EN

Post divider 1 enable (glitchless start/stop) 

RW

0

2

REG_DIVQ0_EN

Post divider 0 enable (glitchless start/stop)

RW

1

1

REG_RFDIV_EN

 Reference divide enable (active low reset)

1'b0 - Reference divide is reset, reference clock is divided by 1

1'b1 - Reference divider is active

The reference divide value is loaded on the rising edge of RFCLK, so REFDIV_EN should change on the falling edge of RFCLK.

RW

1

0

REG_POWERDOWN_B

 PLL Core (PFD+CP+VCO+LF+FBDIV) enable signal.

1'b0 - low current power down state. VCO output will be zero unless IREF is input and IREF_EN=1'b1.

1'b1 - PLL core is enabled

RW

0

Address offset

0x08

Physical address

0x0E00 1008

Instance

pll_mss

Description

PLL reference and feedback registers

Type

RW

31:28

Reserved

RO

0x0

27:16

Reserved

RO

0x000

15:14

Reserved

RO

0x0

13:8

RFDIV

 Reference divide value (1 to 63)

Frequency into PFD is RFCLK/REFDIV

RW

0x00

7:4

Reserved

RO

0x0

3

FOUTFB_SELMUX_EN

 FOUT Feedback clock select enable

1'b0 - Selects feedback directly from 4X VCO

1'b1 - Selects feedback from FBCK_SEL mux output

RW

0

2:1

FBCK_SEL

 Feedback clock select

Selects the feedback clock form one of the post divider outputs (before the BYPASSPOST mux)

2'b00 - Selects feedback clock from post divide 0 output

2'b01 - Selects feedback clock from post divide 1 output

2'b10 - Selects feedback clock from post divide 2 output

2'b11 - Selects feedback clock from post divide 3 output

RW

0x0

0

FSE_B

PLL Deskew (external feedback) mode select

1'b0 - Internal (full-rate VCO) feedback mode to select output of VCO for feedback clock

1'b1 - External feedback mode to select FBCLK for feedback clock 

RW

0

Address offset

0x0C

Physical address

0x0E00 100C

Instance

pll_mss

Description

PLL fractional register

Type

RW

31:8

Reserved

RO

0x00 0000

7:2

Reserved

RO

0x00

1

FRACN_DAC_EN

Fractional noise cancellation DAC enable

1'b0 - Fractional noise cancellation DAC is disabled. Fractional quantization noise is attenuated only by passive loop filter.

1'b1 - Fractional noise cancellation DAC is enabled. DAC actively cancels fractional quantization noise. 

RW

0

0

FRACN_EN

Delta Sigma Modulator enable

1'b0 - Integer mode

1'b1 - Fractional mode 

RW

0

Address offset

0x10

Physical address

0x0E00 1010

Instance

pll_mss

Description

PLL 0/1 division registers

Type

RW

31

Reserved

RO

0

30:24

POST1DIV

 Post divide value for post divider 1 (PLL_OUT[1])

From: (1 to 127)

RW

0x00

23:22

Reserved

RO

0x0

21:19

DIV1_START

 VCO cycle delays after reset for post divider 1 (PLL_OUT[1])

RW

0x0

18:16

VCO1PH_SEL

 Selects one of eight VCO phases for post divider 1 (PLL_OUT[1])

RO

0x0

15

Reserved

RO

0

14:8

POST0DIV

 Post divide value for post divider 0 (PLL_OUT[0])

From: (1 to 127)

RW

0x00

7:6

Reserved

RO

0x0

5:3

DIV0_START

 VCO cycle delays after reset for post divider 0 (PLL_OUT[0])

RW

0x0

2:0

VCO0PH_SEL

 Selects one of eight VCO phases for post divider 0 (PLL_OUT[0])

RO

0x0

Address offset

0x14

Physical address

0x0E00 1014

Instance

pll_mss

Description

PLL 2/3 division registers

Type

RW

31

CKPOST3_SEL

 Selects input clock for post divide 3 (to PLL_OUT[3])

1'b0 - Selects 8-phase output or RFCLK, depending on BYPASSPRE setting

1'b1 - Selects PLL_OUT[2] as input to post divide 3 (cascaded dividers)

RW

0

30:24

POST3DIV

 Post divide value for post divider 3 (PLL_OUT[3])

From: (1 to 127)

RW

0x00

23:22

Reserved

RO

0x0

21:19

DIV3_START

VCO cycle delays after reset for post divider 3 (PLL_OUT[3]) 

RW

0x0

18:16

VCO3PH_SEL

 Selects one of eight VCO phases for post divider 3 (PLL_OUT[3])

RO

0x0

15

Reserved

RO

0

14:8

POST2DIV

 Post divide value for post divider 2 (PLL_OUT[2])

From: (1 to 127)

RW

0x00

7:6

Reserved

RO

0x0

5:3

DIV2_START

 VCO cycle delays after reset for post divider 2 (PLL_OUT[2])

RW

0x0

2:0

VCO2PH_SEL

 Selects one of eight VCO phases for post divider 2 (PLL_OUT[2])

RO

0x0

Address offset

0x18

Physical address

0x0E00 1018

Instance

pll_mss

Description

PLL control register

Type

RW

31:21

Reserved

RO

0x000

20:18

ATEST_SEL

 Analog test mux select

3'd7 - ATESTOUT = VDDPOST, or HighZ if ATESTEN=1'b0

3'd6 - ATESTOUT = VDDREF, or HighZ if ATESTEN=1'b0

3'd5 - ATESTOUT = VDDHV, or HighZ if ATESTEN=1'b0

3'd4 - ATESTOUT = psub, or HighZ if ATESTEN=1'b0

3'd3 - ATESTOUT = VSSREF, or HighZ if ATESTEN=1'b0

3'd2 - ATESTOUT = VSSHV, or HighZ if ATESTEN=1'b0

3'd1 - ATESTOUT = PLL proportional path tuning voltage, or HighZ if ATESTEN=1'b0

3'd0 - ATESTOUT = PLL integral path tuning voltage replica if ATESTEN=1'b1, or HighZ if ATESTEN=1'b0

RW

0x0

17

ATEST_EN

Analog test mux enable

1'b0 - ATESTOUT = HighZ

1'b1 - ATESTOUT = Local supply voltages, PLL integral path tuning voltage replica, or PLL proportional path tuning voltage

RW

0

16:13

Reserved

RO

0x0

12:9

LOCKCOUNTSEL

 Lock count select

Selects the number of PFD edges after the last cycle slip before the lock signal goes high

Count is defined as 2^LOCKCOUNTSEL (e.g. with  LOCKCOUNTSEL=4'd8,

LOCK will go high 256 PFD periods after the last cycle slip)

RW

0x8

8:6

Reserved

RO

0x0

5

IREF_TOGGLE

 IREF_TOGGLE is an option to force the PLL clock output to toggle even if the reference clock stops. IREF_TOGGLE=1 will usually be coupled with IREF_EN=1.

RW

0

4

IREF_EN

 Enables IREF to pass to the VCO

1'b0 - IREF is gated o  and not used by the VCO

1'b1 - IREF passes to the VCO to guarantee a minimum oscillation frequency

RW

0

3:2

BWP

 Proportional Path loop bandwidth control

For Integer mode: 2'b00=FPFD/55, 2'b01=FPFD/44, 2'b10=FPFD/36, 2'b11=FPFD/30

For Fractional mode: 2'b00=FPFD/91, 2'b01=FPFD/77, 2'b10=FPFD/65, 2'b11=FPFD/56

RW

0x1

1:0

BWI

 Integral Path loop bandwidth control

2'b00=Slowest integral path

2'b01=4X integral path by enabling all four elements charge pump elements instead of rotating

2'b10=4X integral path by increasing each element by 4X (still rotates) (recommended for deskew)

2'b11=16X integral path by enabling all four elements and increasing each element by 4X

RW

0x2

Address offset

0x1C

Physical address

0x0E00 101C

Instance

pll_mss

Description

PLL calibration register

Type

RW

31:23

Reserved

RO

0x000

22:16

DSKEWCALOUT

This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a buffered version of DSKEWCALIN[6:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration can be bypassed for faster locking. The value changes on the rising edge of RFCLK, so it can be clocked out on the falling edge of RFCLK.

RO

0x00

15

Reserved

RO

0

14:8

DSKEWCALIN

Override value for deskew calibration. It is a signed integer with positive values delaying the reset of the faster path, and negative values delaying the reset of the slower path. 5'b0 is the minimum value, with each count increasing the reset time by one bu er delay. For normal operation this should be set to 5'b0.

If DSKEWCALEN=1 and DSKEWCALBYP=1, this can be used to force a skew correction value based on a previous readout of DSKEWCALOUT[6:0] so that skew calibration can be bypassed.

RW

0x00

7:5

Reserved

RO

0x0

4

DSKEWCALBYP

 Deskew calibration bypass

1'b0 - use the skew calibration output (when DSKEWCALEN=1) to set the phase correction

1'b1 - use the DSKEWCALIN[6:0] value (when DSKEWCALEN=1) to set the phase correction

RW

0

3

DSKEWCAL_EN

Deskew calibration enable to actively adjust for input skew

1'b0 - skew calibration is disabled. Static phase o set is determined by analog matching only.

1'b1 - skew calibration is enabled. Static phase o set is adjusted by sensing phase at the input. 

RW

0

2:0

DSKEWCALCNT

 Programmable counter for deskew calibration loop

Selects the number of PFD edges to wait after each deskew calibration step

Count is de ned as 2DSKEWCALCNT+4 (e.g. if DSKEWCALCNT=3'd6, the loop will wait 1024 PFD periods before trying a new setting)

Recommended setting is 4'd10 if PLLBWI=2'b01 and 4'd12 if PLLBWI=2'b00

RW

0x0

Address offset

0x20

Physical address

0x0E00 1020

Instance

pll_mss

Description

PLL phase registers

Type

RW

31:15

Reserved

RO

0x0 0000

14

REG_LOADPHS_B

 Load the originally programmed phase for the PLL

RW

1

13:11

REG_OUT3_PHSINIT

 Initial phase value for output 3

RW

0x0

10:8

REG_OUT2_PHSINIT

 Initial phase value for output 2

RW

0x0

7:5

REG_OUT1_PHSINIT

 Initial phase value for output 1

RW

0x0

4:2

REG_OUT0_PHSINIT

 Initial phase value for output 0

RW

0x0

1

PLL_REG_ENABLE_SYNCREFDIV

 Register to enable synchronous reset of refernce dividers

RW

0

0

PLL_REG_SYNCREFDIV_EN

 Enable synchronizing the reference dividers for the two PLLs in the given corner of the device.

RW

1

Address offset

0x24

Physical address

0x0E00 1024

Instance

pll_mss

Description

SSCG registers 0

Type

RW

31:30

Reserved

RO

0x0

29:6

FRACIN

 Input fractional divide value

RW

0x00 0000

5:0

DIVVAL

 Divider required to set the modulation frequency

RW

0x00

Address offset

0x28

Physical address

0x0E00 1028

Instance

pll_mss

Description

SSCG registers 1

Type

RW

31:30

Reserved

RO

0x0

29:6

FRACMOD

 Modulated fractional divide value to PLL

RO

0x00 0000

5:1

SSMD

 Sets modulation depth

Modulation Depth = SPREAD * 0.1%

ie. SPREAD=5'b5 = Modulation Depth of 0.5%

RW

0x00

0

DOWNSPREAD

 Selects center spread or downspread

1'b0 -> Center spread

1'b1 -> Downspread

RW

0

Address offset

0x2C

Physical address

0x0E00 102C

Instance

pll_mss

Description

SSCG registers 2

Type

RW

31:24

Reserved

RO

0x00

23:12

INTMOD

 Modulated integer divide value to PLL

RO

0x000

11:0

INTIN

 Input integer divide value

RW

0x000

Address offset

0x30

Physical address

0x0E00 1030

Instance

pll_mss

Description

SSCG registers 3

Type

RW

31:23

Reserved

RO

0x000

22

Reserved

RO

0

21:20

RANDOM_SEL

 Selects between 3 different pseudo-noise patterns.

2'b00 -> Pattern 0

2'b01 -> Pattern 1

2'b1X -> Pattern 2

RW

0x0

19

RANDOM_FILTER

 Active high enables high-pass  filtering of pseudo-noise source.

RW

0

18:11

TBLADDR

 Outputs address to external wave table

RO

0x00

10:3

EXT_MAXADDR

 External wave table maximum address value input

RW

0x00

2:1

SEL_EXTWAVE

 Selects between EXTWAVEVAL data input, Pseudo-random Noise, and internal lookup table

2'b00 -> Internal 128 point triangular wave table

2'b01 -> External wave table

2'b1X -> Pseudo-random Noise

RW

0x0

0

SSE_B

 Bypass the modulator

1'b0 -> Normal Operation

1'b1 -> Bypass SSMOD

RW

0