Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x00

0x0E08 0000

PLL_CTRL

RW

32

0x0000 10C6

0x04

0x0E08 0004

PLL_REF_FB

RW

32

0x0000 0000

0x08

0x0E08 0008

PLL_FRACN

RW

32

0x0000 0000

0x0C

0x0E08 000C

PLL_DIV_0_1

RW

32

0x0000 0000

0x10

0x0E08 0010

PLL_DIV_2_3

RW

32

0x0000 0000

0x14

0x0E08 0014

PLL_CTRL2

RW

32

0x0000 1006

0x18

0x0E08 0018

PLL_CAL

RW

32

0x0000 0000

0x1C

0x0E08 001C

PLL_PHADJ

RW

32

0x0000 4001

0x20

0x0E08 0020

SSCG_REG_0

RW

32

0x0000 0000

0x24

0x0E08 0024

SSCG_REG_1

RW

32

0x0000 0000

0x28

0x0E08 0028

SSCG_REG_2

RW

32

0x0000 0000

0x2C

0x0E08 002C

SSCG_REG_3

RW

32

0x0000 0000

0x30

0x0E08 0030

Address offset

0x00

Physical address

0x0E08 0000

Instance

pll_eth

Description

This is a compulsory register for all SCB slaves and must be at the same offset in all slaves to facilitate global soft reset of all SCB registers with a single broadcast write from the SCB master.

Type

RW

31:16

BLOCKID

This returns the block type and chip location. (IO SCB bus only)

RO

0x0000

Read 0x0000

[block_address_IOSCB_PLL_SGMII]

15:9

Reserved

RO
Rreturns0s

0x00

8

PERIPH

This asserts the functional reset of the block. It is asserted at power up. When written is stays asserted until written to 0.

WO

0

Write 0

[scb_periph_not_in_soft_reset_IOSCB_PLL_SGMII]

Write 1

[scb_periph_reset_IOSCB_PLL_SGMII]

7:2

Reserved

RO
Rreturns0s

0x00

1

V_MAP

This when asserted resets all the register bits apart from the non-volatile registers, the bit self clears. i.e. is similar to a W1P bit

WO

0

Write 0

[scb_v_regs_not_in_soft_reset_IOSCB_PLL_SGMII]

Write 1

[scb_v_regs_reset_IOSCB_PLL_SGMII]

0

NV_MAP

This when asserted resets all the non-volatile register bits e.g. RW-P bits, the bit self clears i.e. is similar to a W1P bit

WO

0

Write 0

[scb_nv_regs_not_in_soft_reset_IOSCB_PLL_SGMII]

Write 1

[scb_nv_regs_reset_IOSCB_PLL_SGMII]

Address offset

0x04

Physical address

0x0E08 0004

Instance

pll_eth

Description

PLL control register

Type

RW

31

LOCK_B

Status of PLL lock_b

RO

0

30

Reserved

RO

0

29

UNLOCK_INT

pll unlock interrupt signal

RW
W1toClr

0

28

LOCK_INT

pll lock interrupt signal

RW
W1toClr

0

27

UNLOCK_INT_EN

Enable pll unlock interrupt

RW

0

26

LOCK_INT_EN

Enable pll lock interrupt

RW

0

25

LOCK

Status of PLL lock

RO

0

24

LP_REQUIRES_LOCK

RW

0

23:20

REG_BYPASSPOST

RW

0x0

19:16

REG_BYPASSPRE

RW

0x0

15:13

Reserved

RO

0x0

12

REG_BYPASS_GO_B

RW

1

11:8

BYPCK_SEL

RW

0x0

7

RESETONLOCK

RW

1

6

REG_RFCLK_SEL

RW

1

5

REG_DIVQ3_EN

RW

0

4

REG_DIVQ2_EN

RW

0

3

REG_DIVQ1_EN

RW

0

2

REG_DIVQ0_EN

RW

1

1

REG_RFDIV_EN

RW

1

0

REG_POWERDOWN_B

RW

0

Address offset

0x08

Physical address

0x0E08 0008

Instance

pll_eth

Description

PLL reference and feedback registers

Type

RW

31:28

Reserved

RO

0x0

27:16

Reserved

RO

0x000

15:14

Reserved

RO

0x0

13:8

RFDIV

RW

0x00

7:4

Reserved

RO

0x0

3

FOUTFB_SELMUX_EN

RW

0

2:1

FBCK_SEL

RW

0x0

0

FSE_B

RW

0

Address offset

0x0C

Physical address

0x0E08 000C

Instance

pll_eth

Description

PLL fractional register

Type

RW

31:8

Reserved

RO

0x00 0000

7:2

Reserved

RO

0x00

1

FRACN_DAC_EN

RW

0

0

FRACN_EN

RW

0

Address offset

0x10

Physical address

0x0E08 0010

Instance

pll_eth

Description

PLL 0/1 division registers

Type

RW

31

Reserved

RO

0

30:24

POST1DIV

RW

0x00

23:22

Reserved

RO

0x0

21:19

DIV1_START

RW

0x0

18:16

VCO1PH_SEL

RO

0x0

15

Reserved

RO

0

14:8

POST0DIV

RW

0x00

7:6

Reserved

RO

0x0

5:3

DIV0_START

RW

0x0

2:0

VCO0PH_SEL

RO

0x0

Address offset

0x14

Physical address

0x0E08 0014

Instance

pll_eth

Description

PLL 2/3 division registers

Type

RW

31

CKPOST3_SEL

RW

0

30:24

POST3DIV

RW

0x00

23:22

Reserved

RO

0x0

21:19

DIV3_START

RW

0x0

18:16

VCO3PH_SEL

RO

0x0

15

Reserved

RO

0

14:8

POST2DIV

RW

0x00

7:6

Reserved

RO

0x0

5:3

DIV2_START

RW

0x0

2:0

VCO2PH_SEL

RO

0x0

Address offset

0x18

Physical address

0x0E08 0018

Instance

pll_eth

Description

PLL control register

Type

RW

31:21

Reserved

RO

0x000

20:18

ATEST_SEL

RW

0x0

17

ATEST_EN

RW

0

16:13

Reserved

RO

0x0

12:9

LOCKCNT

RW

0x8

8:6

Reserved

RO

0x0

5

IREF_TOGGLE

RW

0

4

IREF_EN

RW

0

3:2

BWP

RW

0x1

1:0

BWI

RW

0x2

Address offset

0x1C

Physical address

0x0E08 001C

Instance

pll_eth

Description

PLL calibration register

Type

RW

31:23

Reserved

RO

0x000

22:16

DSKEWCALOUT

RO

0x00

15

Reserved

RO

0

14:8

DSKEWCALIN

RW

0x00

7:5

Reserved

RO

0x0

4

DSKEWCALBYP

RW

0

3

DSKEWCAL_EN

RW

0

2:0

DSKEWCALCNT

RW

0x0

Address offset

0x20

Physical address

0x0E08 0020

Instance

pll_eth

Description

PLL phase registers

Type

RW

31:15

Reserved

RO

0x0 0000

14

REG_LOADPHS_B

RW

1

13:11

REG_OUT3_PHSINIT

RW

0x0

10:8

REG_OUT2_PHSINIT

RW

0x0

7:5

REG_OUT1_PHSINIT

RW

0x0

4:2

REG_OUT0_PHSINIT

RW

0x0

1

PLL_REG_ENABLE_SYNCREFDIV

RW

0

0

PLL_REG_SYNCREFDIV_EN

RW

1

Address offset

0x24

Physical address

0x0E08 0024

Instance

pll_eth

Description

SSCG registers 0

Type

RW

31:30

Reserved

RO

0x0

29:6

FRACIN

RW

0x00 0000

5:0

DIVVAL

RW

0x00

Address offset

0x28

Physical address

0x0E08 0028

Instance

pll_eth

Description

SSCG registers 1

Type

RW

31:30

Reserved

RO

0x0

29:6

FRACMOD

RO

0x00 0000

5:1

SSMD

RW

0x00

0

DOWNSPREAD

RW

0

Address offset

0x2C

Physical address

0x0E08 002C

Instance

pll_eth

Description

SSCG registers 2

Type

RW

31:24

Reserved

RO

0x00

23:12

INTMOD

RO

0x000

11:0

INTIN

RW

0x000

Address offset

0x30

Physical address

0x0E08 0030

Instance

pll_eth

Description

SSCG registers 3

Type

RW

31:23

Reserved

RO

0x000

22

Reserved

RO

0

21:20

RANDOM_SEL

RW

0x0

19

RANDOM_FILTER

RW

0

18:11

TBLADDR

RO

0x00

10:3

EXT_MAXADDR

RW

0x00

2:1

SEL_EXTWAVE

RW

0x0

0

SSE_B

RW

0