This section
provides information on the PCIE_CTRL Module Instance. Each of the module
registers is described below.
Return to mpfs_ioscb_memmap_dri
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
RW |
32 |
0x0000 0000 |
0x000 |
|
RW |
32 |
0x0001 9110 |
0x004 |
|
RW |
32 |
0x1FC0 0000 |
0x008 |
|
RO |
32 |
0x0000 0000 |
0x010 |
|
RW |
32 |
0x0010 0002 |
0x014 |
|
RW |
32 |
0x0000 0000 |
0x020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
|
RW |
32 |
0x0000 1111 |
0x02C |
|
RW |
32 |
0x0000 0000 |
0x030 |
|
RW |
32 |
0x0000 1111 |
0x034 |
|
RW |
32 |
0x0000 0000 |
0x038 |
|
RW |
32 |
0x0000 0000 |
0x03C |
|
RW |
32 |
0x0000 0000 |
0x040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
|
RW |
32 |
0x0000 0000 |
0x048 |
|
RW |
32 |
0x0000 0000 |
0x050 |
|
RO |
32 |
0x0000 0000 |
0x05C |
|
RO |
32 |
0x0000 0000 |
0x060 |
|
RO |
32 |
0x0000 0000 |
0x064 |
|
RO |
32 |
0x0000 0000 |
0x068 |
|
RW |
32 |
0x0000 0000 |
0x06C |
|
RW |
32 |
0x0000 0000 |
0x080 |
|
RW |
32 |
0x0000 0000 |
0x084 |
|
RW |
32 |
0x0000 0000 |
0x088 |
|
RW |
32 |
0x0000 0000 |
0x08C |
|
RW |
32 |
0x0000 0200 |
0x0A0 |
|
RW |
32 |
0x0000 0000 |
0x0A4 |
|
RW |
32 |
0x0000 0000 |
0x100 |
|
RW |
32 |
0x0000 0000 |
0x104 |
|
RW |
32 |
0x0000 0000 |
0x108 |
|
RW |
32 |
0x0000 0000 |
0x120 |
|
RW |
32 |
0x0000 0000 |
0x124 |
|
RW |
32 |
0x0000 0000 |
0x128 |
|
RW |
32 |
0x0000 0000 |
0x140 |
|
RW |
32 |
0x0000 0000 |
0x144 |
|
RW |
32 |
0x0000 0000 |
0x148 |
|
RW |
32 |
0x0000 0000 |
0x14C |
|
RW |
32 |
0x0000 0000 |
0x150 |
|
RW |
32 |
0x0000 0000 |
0x180 |
|
RW |
32 |
0x0000 0000 |
0xC80 |
|
RW |
32 |
0x0000 0000 |
0xC84 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0300 6000 |
|
RW |
32 |
0x0001 9110 |
0x004 |
0x0300 6004 |
|
RW |
32 |
0x1FC0 0000 |
0x008 |
0x0300 6008 |
|
RO |
32 |
0x0000 0000 |
0x010 |
0x0300 6010 |
|
RW |
32 |
0x0010 0002 |
0x014 |
0x0300 6014 |
|
RW |
32 |
0x0000 0000 |
0x020 |
0x0300 6020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x0300 6024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x0300 6028 |
|
RW |
32 |
0x0000 1111 |
0x02C |
0x0300 602C |
|
RW |
32 |
0x0000 0000 |
0x030 |
0x0300 6030 |
|
RW |
32 |
0x0000 1111 |
0x034 |
0x0300 6034 |
|
RW |
32 |
0x0000 0000 |
0x038 |
0x0300 6038 |
|
RW |
32 |
0x0000 0000 |
0x03C |
0x0300 603C |
|
RW |
32 |
0x0000 0000 |
0x040 |
0x0300 6040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
0x0300 6044 |
|
RW |
32 |
0x0000 0000 |
0x048 |
0x0300 6048 |
|
RW |
32 |
0x0000 0000 |
0x050 |
0x0300 6050 |
|
RO |
32 |
0x0000 0000 |
0x05C |
0x0300 605C |
|
RO |
32 |
0x0000 0000 |
0x060 |
0x0300 6060 |
|
RO |
32 |
0x0000 0000 |
0x064 |
0x0300 6064 |
|
RO |
32 |
0x0000 0000 |
0x068 |
0x0300 6068 |
|
RW |
32 |
0x0000 0000 |
0x06C |
0x0300 606C |
|
RW |
32 |
0x0000 0000 |
0x080 |
0x0300 6080 |
|
RW |
32 |
0x0000 0000 |
0x084 |
0x0300 6084 |
|
RW |
32 |
0x0000 0000 |
0x088 |
0x0300 6088 |
|
RW |
32 |
0x0000 0000 |
0x08C |
0x0300 608C |
|
RW |
32 |
0x0000 0200 |
0x0A0 |
0x0300 60A0 |
|
RW |
32 |
0x0000 0000 |
0x0A4 |
0x0300 60A4 |
|
RW |
32 |
0x0000 0000 |
0x100 |
0x0300 6100 |
|
RW |
32 |
0x0000 0000 |
0x104 |
0x0300 6104 |
|
RW |
32 |
0x0000 0000 |
0x108 |
0x0300 6108 |
|
RW |
32 |
0x0000 0000 |
0x120 |
0x0300 6120 |
|
RW |
32 |
0x0000 0000 |
0x124 |
0x0300 6124 |
|
RW |
32 |
0x0000 0000 |
0x128 |
0x0300 6128 |
|
RW |
32 |
0x0000 0000 |
0x140 |
0x0300 6140 |
|
RW |
32 |
0x0000 0000 |
0x144 |
0x0300 6144 |
|
RW |
32 |
0x0000 0000 |
0x148 |
0x0300 6148 |
|
RW |
32 |
0x0000 0000 |
0x14C |
0x0300 614C |
|
RW |
32 |
0x0000 0000 |
0x150 |
0x0300 6150 |
|
RW |
32 |
0x0000 0000 |
0x180 |
0x0300 6180 |
|
RW |
32 |
0x0000 0000 |
0xC80 |
0x0300 6C80 |
|
RW |
32 |
0x0000 0000 |
0xC84 |
0x0300 6C84 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0300 A000 |
|
RW |
32 |
0x0001 9110 |
0x004 |
0x0300 A004 |
|
RW |
32 |
0x1FC0 0000 |
0x008 |
0x0300 A008 |
|
RO |
32 |
0x0000 0000 |
0x010 |
0x0300 A010 |
|
RW |
32 |
0x0010 0002 |
0x014 |
0x0300 A014 |
|
RW |
32 |
0x0000 0000 |
0x020 |
0x0300 A020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x0300 A024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x0300 A028 |
|
RW |
32 |
0x0000 1111 |
0x02C |
0x0300 A02C |
|
RW |
32 |
0x0000 0000 |
0x030 |
0x0300 A030 |
|
RW |
32 |
0x0000 1111 |
0x034 |
0x0300 A034 |
|
RW |
32 |
0x0000 0000 |
0x038 |
0x0300 A038 |
|
RW |
32 |
0x0000 0000 |
0x03C |
0x0300 A03C |
|
RW |
32 |
0x0000 0000 |
0x040 |
0x0300 A040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
0x0300 A044 |
|
RW |
32 |
0x0000 0000 |
0x048 |
0x0300 A048 |
|
RW |
32 |
0x0000 0000 |
0x050 |
0x0300 A050 |
|
RO |
32 |
0x0000 0000 |
0x05C |
0x0300 A05C |
|
RO |
32 |
0x0000 0000 |
0x060 |
0x0300 A060 |
|
RO |
32 |
0x0000 0000 |
0x064 |
0x0300 A064 |
|
RO |
32 |
0x0000 0000 |
0x068 |
0x0300 A068 |
|
RW |
32 |
0x0000 0000 |
0x06C |
0x0300 A06C |
|
RW |
32 |
0x0000 0000 |
0x080 |
0x0300 A080 |
|
RW |
32 |
0x0000 0000 |
0x084 |
0x0300 A084 |
|
RW |
32 |
0x0000 0000 |
0x088 |
0x0300 A088 |
|
RW |
32 |
0x0000 0000 |
0x08C |
0x0300 A08C |
|
RW |
32 |
0x0000 0200 |
0x0A0 |
0x0300 A0A0 |
|
RW |
32 |
0x0000 0000 |
0x0A4 |
0x0300 A0A4 |
|
RW |
32 |
0x0000 0000 |
0x100 |
0x0300 A100 |
|
RW |
32 |
0x0000 0000 |
0x104 |
0x0300 A104 |
|
RW |
32 |
0x0000 0000 |
0x108 |
0x0300 A108 |
|
RW |
32 |
0x0000 0000 |
0x120 |
0x0300 A120 |
|
RW |
32 |
0x0000 0000 |
0x124 |
0x0300 A124 |
|
RW |
32 |
0x0000 0000 |
0x128 |
0x0300 A128 |
|
RW |
32 |
0x0000 0000 |
0x140 |
0x0300 A140 |
|
RW |
32 |
0x0000 0000 |
0x144 |
0x0300 A144 |
|
RW |
32 |
0x0000 0000 |
0x148 |
0x0300 A148 |
|
RW |
32 |
0x0000 0000 |
0x14C |
0x0300 A14C |
|
RW |
32 |
0x0000 0000 |
0x150 |
0x0300 A150 |
|
RW |
32 |
0x0000 0000 |
0x180 |
0x0300 A180 |
|
RW |
32 |
0x0000 0000 |
0xC80 |
0x0300 AC80 |
|
RW |
32 |
0x0000 0000 |
0xC84 |
0x0300 AC84 |
Address offset |
0x000 |
||
Physical address |
0x0300 6000 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A000 |
pcie_top_1_PCIE_CTRL |
||
Description |
Compulsory register for all SCB slaves, facilitating
global soft reset. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:16 |
BLOCKID |
This returns the block type and chip location. |
RO |
0x0000 |
|
|
|
Read 0x0000 |
[block_address_PCIE_CTRL] |
|
|
15:9 |
Reserved |
|
RO |
0x00 |
|
8 |
PERIPH |
This asserts functional reset of the peripheral block. It
is asserted and left asserted at power-up. |
WO |
0 |
|
|
|
Write 0 |
[scb_periph_not_in_soft_reset_PCIE_CTRL]
Reset not asserted. |
|
|
|
|
Write 1 |
[scb_periph_reset_PCIE_CTRL] SCB
registers reset pulsed. |
|
|
7:2 |
Reserved |
|
RO |
0x00 |
|
1 |
V_MAP |
Resets all the volatile register bits. |
WO |
0 |
|
|
|
Write 0 |
[scb_v_regs_not_in_soft_reset_PCIE_CTRL]
Reset not asserted. |
|
|
|
|
Write 1 |
[scb_v_regs_reset_PCIE_CTRL] SCB
Volatile reset (i.e. RW-X registers are reset) |
|
|
0 |
NV_MAP |
Resets all the non-volatile register bits (e.g. RW-P bits). |
WO |
0 |
|
|
|
Write 0 |
[scb_nv_regs_not_in_soft_reset_PCIE_CTRL]
Reset not asserted. |
|
|
|
|
Write 1 |
[scb_nv_regs_reset_PCIE_CTRL]
SCB Non-Volatile reset (i.e. RW-P registers are
reset. |
|
Address offset |
0x004 |
||
Physical address |
0x0300 6004 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A004 |
pcie_top_1_PCIE_CTRL |
||
Description |
Controls the device configuration. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:20 |
Reserved |
|
RO |
0x000 |
|
19 |
ENABLE_NULLIFY_TLP_ON_TXBUF_ECC_ERR |
When asserted; nullfy TLP when
TX BUF ECC errors encountered is supported (k_gen); |
RW |
0 |
|
|
|
0 |
[nullify_tlp_on_txbuf_ecc_err_no_support]
nullify TLP on TXBUF ECC error is not supported |
|
|
|
|
1 |
[nullify_tlp_on_txbuf_ecc_err_support]
nullify TLP on TXBUF ECC error is supported |
|
|
18:17 |
Reserved |
|
RO |
0x0 |
|
16 |
USE_RXELECIDLE_TO_DETECT_ELECIDLE_ENTRY |
When asserted; treat fall edge of rxelecidle
as rcvd EIOS, see AppD of
PCIE Ref Manual (k_gen); |
RW |
1 |
|
|
|
0 |
[treat_falledge_rxelecidle_as_rcvd_eios_no_support]
treat fall edge of rxelecidle as rcvd EIOS is not supported |
|
|
|
|
1 |
[treat_falledge_rxelecidle_as_rcvd_eios_support]
treat fall edge of rxelecidle as rcvd EIOS is supported |
|
|
15 |
LANE_REVERSAL_SUPPORT |
When asserted; lane reversal is supported (k_gen); |
RW |
1 |
|
|
|
0 |
[lane_reversal_no_support] lane
reversal is not supported |
|
|
|
|
1 |
[lane_reversal_support] lane
reversal is supported |
|
|
14:13 |
Reserved |
|
RO |
0x0 |
|
12 |
LINK_SPEED_5GBPS_SUPPORT |
When asserted; 5.0 Gbps link-speed is supported (k_gen); |
RW |
1 |
|
|
|
0 |
[link_speed_5gbps_no_support] 5.0 Gbps link speed is not
supported |
|
|
|
|
1 |
[link_speed_5gbps_support] 5.0 Gbps link speed is
supported |
|
|
11:9 |
Reserved |
|
RO |
0x0 |
|
8 |
LINK_WIDTH_X4_SUPPORT |
When asserted; x4 lane link-width mode is supported (k_gen); |
RW |
1 |
|
|
|
0 |
[link_x4_no_support] x4 link width is not supported |
|
|
|
|
1 |
[link_x4_support] x4 link width is supported |
|
|
7:5 |
Reserved |
|
RO |
0x0 |
|
4 |
LINK_WIDTH_X2_SUPPORT |
When asserted; x2 lane link-width mode is supported (k_gen); |
RW |
1 |
|
|
|
0 |
[link_x2_no_support] x2 link width is not supported |
|
|
|
|
1 |
[link_x2_support] x2 link width is supported |
|
|
3:1 |
Reserved |
|
RO |
0x0 |
|
0 |
ROOT_PORT_NEP |
When asserted; the PCIE controller is in root port (k_gen); |
RW |
0 |
|
|
|
0 |
[dev_end_point] The device is in
EndPoint mode |
|
|
|
|
1 |
[dev_root_port] The device is in
RootPort mode |
|
Address offset |
0x008 |
||
Physical address |
0x0300 6008 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A008 |
pcie_top_1_PCIE_CTRL |
||
Description |
Register for clock control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:22 |
TL_CLOCK_FREQ |
The 10 bit value specifies the
frequency of transaction layer clock. It is used in Latency tolerating state
machine |
RW |
0x07F |
21:0 |
Reserved |
|
RO |
0x00 0000 |
Address offset |
0x010 |
||
Physical address |
0x0300 6010 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A010 |
pcie_top_1_PCIE_CTRL |
||
Description |
Soft Reset Logic Debug Information |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:30 |
Reserved |
|
RO |
0x0 |
29 |
RST_DBG_PIPE_RSTN |
Captures the state of signal - pipe_rstn
(input to PIPE logic) |
RO |
0 |
28 |
RST_DBG_AXI4_SLVL_RSTN |
Captures the state of signal - axi4_slvl_rstn (input to
PCIE Core) |
RO |
0 |
27 |
RST_DBG_AXI4_SLV_RSTN |
Captures the state of signal - axi4_slv_rstn (input to
PCIE Core) |
RO |
0 |
26 |
RST_DBG_AXI4_MST_RSTN |
Captures the state of signal - axi4_mst_rstn (input to
PCIE Core) |
RO |
0 |
25 |
RST_DBG_BR_RSTN |
Captures the state of signal - br_rstn
(input to PCIE Core) |
RO |
0 |
24 |
RST_DBG_TL_CRSTN |
Captures the state of signal - tl_crstn
(input to PCIE Core) |
RO |
0 |
23 |
RST_DBG_TL_RSTN |
Captures the state of signal - tl_rstn
(input to PCIE Core) |
RO |
0 |
22 |
RST_DBG_TL_NPOR |
Captures the state of signal - tl_npor
(input to PCIE Core) |
RO |
0 |
21 |
RST_DBG_PL_RSTN |
Captures the state of signal - pl_rstn
(input to PCIE Core) |
RO |
0 |
20 |
RST_DBG_PL_NPOR |
Captures the state of signal - pl_npor
(input to PCIE Core) |
RO |
0 |
19:13 |
Reserved |
|
RO |
0x00 |
12 |
RST_DBG_WAKE_REQ |
Captures the state of signal - wake_req
|
RO |
0 |
11:10 |
Reserved |
|
RO |
0x0 |
9:8 |
RST_DBG_PIPE_POWERDOWN |
Captures the state of signal - powerdown[1:0] (output
from PIPE logic) |
RO |
0x0 |
7:4 |
RST_DBG_PIPE_PHYSTATUS |
Captures the state of signal - pipe_phystatus[3:0] (output
from PIPE logic) |
RO |
0x0 |
3 |
Reserved |
|
RO |
0 |
2 |
RST_DBG_PERIPH_RESET_B |
Captures the state of signal - periph_reset_b
|
RO |
0 |
1 |
RST_DBG_MPERST_B |
Captures the state of signal - mperst_b
|
RO |
0 |
0 |
RST_DBG_CORE_UP |
Captures the state of signal - coreup
|
RO |
0 |
Address offset |
0x014 |
||
Physical address |
0x0300 6014 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A014 |
pcie_top_1_PCIE_CTRL |
||
Description |
PCIe Controller Resets |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:21 |
Reserved |
|
RO |
0x000 |
|
20 |
CFG_PCIE_CFGRESET_REL |
When de-asserted, the PCIe Controller resets (PL, TL) are
held under reset when pl_exit[2:0] conditions are detected; the reset releases are
gated by the assertion of this register bit |
RW |
1 |
|
|
|
0 |
[pcie_cfgreset_rel_disabled]
PCIe Controller held under reset upon pl_exit[2:0] |
|
|
|
|
1 |
[pcie_cfgreset_rel_enabled] PCIe
Controller is not held under reset upon pl_exit[2:0] |
|
|
19:17 |
Reserved |
|
RO |
0x0 |
|
16 |
CFG_BRGMAP_SOFTRST |
When asserted, resets the bridge internal registers. |
RW |
0 |
|
|
|
0 |
[bridge_map_soft_reset_disabled]
|
|
|
|
|
1 |
[bridge_map_soft_reset_enabled] |
|
|
15:13 |
Reserved |
|
RO |
0x0 |
|
12 |
CFG_IGNORE_INBAND_RST_EVENT_4_CTRL_RST |
When asserted, ignore the effect of DLUp|HotRst|L2Exit
events by not resetting PCIe controller |
RW |
0 |
|
|
|
0 |
[ignore_inband_rst_event_for_ctrl_disabled]
Inband reset events are not ignored (PCIe Core
resets are applied as needed) |
|
|
|
|
1 |
[ignore_inband_rst_event_for_ctrl_enabled]
Inband reset events are completely ignored (PCIe
Core resets are not applied as needed) |
|
|
11:9 |
Reserved |
|
RO |
0x0 |
|
8 |
CFG_IGNORE_MPERST |
When asserted, ignore external PERST# pin and use internal
periph_reset_b as fundamental reset |
RW |
0 |
|
|
|
0 |
[ignore_mperst_disabled] PERST#
pin as fundamental reset is completely not ignored |
|
|
|
|
1 |
[ignore_mperst_enabled] PERST#
pin as fundamental reset is completely ignored |
|
|
7:2 |
Reserved |
|
RO |
0x00 |
|
1 |
CFG_IGNORE_BRGAXI_SOFTRST_4_CTRL_RST |
When asserted, do not reset PL and TL logic when
CFG_BRGAXI_SOFTRST=1 |
RW |
1 |
|
|
|
0 |
[ignore_pl_tl_resets_disabled]
PL|TL are not in reset |
|
|
|
|
1 |
[ignore_pl_tl_resets_enabled]
PL|TL are also in reset |
|
|
0 |
CFG_BRGAXI_SOFTRST |
The register resets the Bridge and AXI layers in the PCIe
controller. Internal FSM conditionally resets PL and TL Logic (see bit1 and
bit2 settings) |
RW |
0 |
|
|
|
0 |
[bridge_axi_soft_reset_disabled]
Bridge/AXI (Conditionally PL|TL) is not in reset |
|
|
|
|
1 |
[bridge_axi_soft_reset_enabled]
Bridge/AXI (Conditionally PL|TL) is in reset |
|
Address offset |
0x020 |
||
Physical address |
0x0300 6020 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A020 |
pcie_top_1_PCIE_CTRL |
||
Description |
Indicates a single correctible error event occurred in the
RAMS |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
AXI2PCIE_RAM_SEC_ERR_CNT |
This is a 8 bit counter valuefor single-correctible error in AXI to PCIe buffer.
The counter will not roll back and will stay at its max value. |
RW |
0x00 |
23:16 |
PCIE2AXI_RAM_SEC_ERR_CNT |
This is a 8 bit counter valuefor single-correctible error in PCIe-to-AXI buffer.
The counter will not roll back and will stay at its max value. |
RW |
0x00 |
15:8 |
RX_RAM_SEC_ERR_CNT |
This is a 8 bit counter value for
single-correctible error in PCIe RX buffer. The counter will not roll back
and will stay at its max value. |
RW |
0x00 |
7:0 |
TX_RAM_SEC_ERR_CNT |
This is a 8 bit counter value for
single-correctible error in PCIe TX buffer. The counter will not roll back
and will stay at its max value. |
RW |
0x00 |
Address offset |
0x024 |
||
Physical address |
0x0300 6024 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A024 |
pcie_top_1_PCIE_CTRL |
||
Description |
Indicates a uncorrectible error
event occurred in the RAMS |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
Reserved |
|
RO |
0x0000 |
15:12 |
AXI2PCIE_RAM_DED_ERR_CNT |
This is a 4 bit counter value for
uncorrectible errors in AXI to PCIe buffer. The
counter will not roll back and will stay at its max value. |
RW |
0x0 |
11:8 |
PCIE2AXI_RAM_DED_ERR_CNT |
This is a 4 bit counter value for
uncorrectible errors in PCIe-to-AXI buffer. The
counter will not roll back and will stay at its max value. |
RW |
0x0 |
7:4 |
RX_RAM_DED_ERR_CNT |
This is a 4 bit counter value for
uncorrectible errors in PCIe RX buffer. The counter
will not roll back and will stay at its max value. |
RW |
0x0 |
3:0 |
TX_RAM_DED_ERR_CNT |
This is a 4 bit counter value for
uncorrectible errors in PCIe TX buffer. The counter
will not roll back and will stay at its max value. |
RW |
0x0 |
Address offset |
0x028 |
||
Physical address |
0x0300 6028 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A028 |
pcie_top_1_PCIE_CTRL |
||
Description |
Interrupt contributor registers for SEC Errors |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:16 |
Reserved |
|
RO |
0x0000 |
|
15:12 |
AXI2PCIE_RAM_SEC_ERR_INT |
Indicates a SEC_RAM_ERR occurred in the appropriate
AXI2PCIe Buffer |
RW |
0x0 |
|
|
|
0x0 |
[axi2pcie_sec_err_event_not_encountered] Indicates that
the SEC error is not encountered in AXI2Pcie Buffer |
|
|
|
|
0x1 |
[axi2pcie_sec_err_event_encountered] Indicates that the
SEC error is encountered in AXI2PCIe Buffer |
|
|
11:8 |
PCIE2AXI_RAM_SEC_ERR_INT |
Indicates a SEC_RAM_ERR occurred in appropriate PCIe2AXI
Buffer |
RW |
0x0 |
|
|
|
0x0 |
[pcie2axi_sec_err_event_not_encountered] Indicates that the
SEC error is not encountered in PCIe2AXI Buffer |
|
|
|
|
0x1 |
[pcie2axi_sec_err_event_encountered] Indicates that the
SEC error is encountered in PCIe2AXI Buffer |
|
|
7:4 |
RX_RAM_SEC_ERR_INT |
Indicates a SEC_RAM_ERR occurred in appropriate RX Buffer |
RW |
0x0 |
|
|
|
0x0 |
[rx_sec_err_event_not_encountered]
Indicates that the SEC error is not encountered in RX Buffer |
|
|
|
|
0x1 |
[rx_sec_err_event_encountered] Indicates
that the SEC error is encountered in RX Buffer |
|
|
3:0 |
TX_RAM_SEC_ERR_INT |
Indicates a SEC_RAM_ERR occurred in the appropriate TX
Buffer |
RW |
0x0 |
|
|
|
0x0 |
[tx_sec_err_event_not_encountered]
Indicates that the SEC error is not encountered in TX Buffer |
|
|
|
|
0x1 |
[tx_sec_err_event_encountered]
Indicates that the SEC error is encountered in TX Buffer |
|
Address offset |
0x02C |
||
Physical address |
0x0300 602C |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A02C |
pcie_top_1_PCIE_CTRL |
||
Description |
Indicates the SEC error contributors to ram_err_int |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:16 |
Reserved |
|
RO |
0x0000 |
|
15:12 |
AXI2PCIE_RAM_SEC_ERR_INT_MASK |
Indicates whether SEC error in AXI2PCIe buffer should
contribute ram_err_int signal |
RW |
0x1 |
|
|
|
0x0 |
[axi2pcie_sec_err_int_unmask] Indicates that the SEC error
in AXI2PCIe Buffer contributes to ram_err_int |
|
|
|
|
0x1 |
[axi2pcie_sec_err_int_mask] Indicates that the SEC error
in AXI2PCIe Buffer contributes to ram_err_int is
masked |
|
|
11:8 |
PCIE2AXI_RAM_SEC_ERR_INT_MASK |
Indicates whether SEC error in PCIe2AXI buffer should
contribute ram_err_int signal |
RW |
0x1 |
|
|
|
0x0 |
[pcie2axi_sec_err_int_unmask] Indicates that the SEC error
in PCIe2AXI Buffer contributes to ram_err_int |
|
|
|
|
0x1 |
[pcie2axi_sec_err_int_mask] Indicates that the SEC error
in PCIe2AXI Buffer contributes to ram_err_int is
masked |
|
|
7:4 |
RX_RAM_SEC_ERR_INT_MASK |
Indicates whether SEC error in RX buffer should contribute
ram_err_int signal |
RW |
0x1 |
|
|
|
0x0 |
[rx_sec_err_int_unmask]
Indicates that the SEC error in RX Buffer contributes to ram_err_int
|
|
|
|
|
0x1 |
[rx_sec_err_int_mask] Indicates
that the SEC error in RX Buffer contributes to ram_err_int
is masked |
|
|
3:0 |
TX_RAM_SEC_ERR_INT_MASK |
Indicates whether SEC error in TX buffer should contribute
ram_err_int signal |
RW |
0x1 |
|
|
|
0x0 |
[tx_sec_err_int_unmask]
Indicates that the SEC error in TX Buffer contributes to ram_err_int
|
|
|
|
|
0x1 |
[tx_sec_err_int_mask] Indicates
that the SEC error in TX Buffer contributes to ram_err_int
is masked |
|
Address offset |
0x030 |
||
Physical address |
0x0300 6030 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A030 |
pcie_top_1_PCIE_CTRL |
||
Description |
Interrupt contributor registers for DED Errors |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:16 |
Reserved |
|
RO |
0x0000 |
|
15:12 |
AXI2PCIE_RAM_DED_ERR_INT |
Indicates a DED_RAM_ERR occurred in AXI2PCIe Buffer |
RW |
0x0 |
|
|
|
0x0 |
[axi2pcie_ded_err_event_not_encountered] Indicates that
the DED error is not encountered in AXI2Pcie Buffer |
|
|
|
|
0x1 |
[axi2pcie_ded_err_event_encountered] Indicates that the
DED error is encountered in AXI2PCIe Buffer |
|
|
11:8 |
PCIE2AXI_RAM_DED_ERR_INT |
Indicates a SEC_RAM_ERR occurred in PCIe2AXI Buffer |
RW |
0x0 |
|
|
|
0x0 |
[pcie2axi_ded_err_event_not_encountered] Indicates that
the DED error is not encountered in PCIe2AXI Buffer |
|
|
|
|
0x1 |
[pcie2axi_ded_err_event_encountered] Indicates that the
DED error is encountered in PCIe2AXI Buffer |
|
|
7:4 |
RX_RAM_DED_ERR_INT |
Indicates a DED_RAM_ERR occurred in RX Buffer |
RW |
0x0 |
|
|
|
0x0 |
[rx_ded_err_event_not_encountered]
Indicates that the DED error is not encountered in RX Buffer |
|
|
|
|
0x1 |
[rx_ded_err_event_encountered]
Indicates that the DED error is encountered in RX Buffer |
|
|
3:0 |
TX_RAM_DED_ERR_INT |
Indicates a DED_RAM_ERR occurred in TX Buffer |
RW |
0x0 |
|
|
|
0x0 |
[tx_ded_err_event_not_encountered]
Indicates that the DED error is not encountered in TX Buffer |
|
|
|
|
0x1 |
[tx_ded_err_event_encountered]
Indicates that the DED error is encountered in TX Buffer |
|
Address offset |
0x034 |
||
Physical address |
0x0300 6034 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A034 |
pcie_top_1_PCIE_CTRL |
||
Description |
Indicates the DED error contributors to ram_err_int |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:16 |
Reserved |
|
RO |
0x0000 |
|
15:12 |
AXI2PCIE_RAM_DED_ERR_INT_MASK |
Indicates whether DED error in AXI2PCIe buffer should
contribute ram_err_int signal |
RW |
0x1 |
|
|
|
0x0 |
[axi2pcie_ded_err_int_unmask] Indicates that the DED error
in AXI2PCIe Buffer contributes to ram_err_int |
|
|
|
|
0x1 |
[axi2pcie_ded_err_int_mask] Indicates that the DED error
in AXI2PCIe Buffer contributes to ram_err_int is
masked |
|
|
11:8 |
PCIE2AXI_RAM_DED_ERR_INT_MASK |
Indicates whether DED error in PCIe2AXI buffer should
contribute ram_err_int signal |
RW |
0x1 |
|
|
|
0x0 |
[pcie2axi_ded_err_int_unmask] Indicates that the DED error
in PCIe2AXI Buffer contributes to ram_err_int |
|
|
|
|
0x1 |
[pcie2axi_ded_err_int_mask] Indicates that the DED error
in PCIe2AXI Buffer contributes to ram_err_int is
masked |
|
|
7:4 |
RX_RAM_DED_ERR_INT_MASK |
Indicates whether DED error in RX buffer should contribute
ram_err_int signal |
RW |
0x1 |
|
|
|
0x0 |
[rx_ded_err_int_unmask]
Indicates that the DED error in RX Buffer contributes to ram_err_int
|
|
|
|
|
0x1 |
[rx_ded_err_int_mask] Indicates
that the DED error in RX Buffer contributes to ram_err_int
is masked |
|
|
3:0 |
TX_RAM_DED_ERR_INT_MASK |
Indicates whether DED error in TX buffer should contribute
ram_err_int signal |
RW |
0x1 |
|
|
|
0x0 |
[tx_ded_err_int_unmask]
Indicates that the DED error in TX Buffer contributes to ram_err_int
|
|
|
|
|
0x1 |
[tx_ded_err_int_mask] Indicates
that the DED error in TX Buffer contributes to ram_err_int
is masked |
|
Address offset |
0x038 |
||
Physical address |
0x0300 6038 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A038 |
pcie_top_1_PCIE_CTRL |
||
Description |
Manually injects ECC error or bypasses ECC. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:28 |
Reserved |
|
RO |
0x0 |
|
27 |
AXI2PCIe_RAM_ECC_BYPASS |
ECC Generation and check is bypassed in AXI2PCIE RAM |
RW |
0 |
|
|
|
0 |
[axi2pcie_ram_ecc_enabled] Disables ECC error injection in
AXI2PCIe RAM |
|
|
|
|
1 |
[axi2pcie_ram_ecc_bypassed] Enables ECC error injection in
AXI2PCIe RAM |
|
|
26 |
PCIe2AXI_RAM_ECC_BYPASS |
ECC Generation and check is bypassed in PCIE2AXI RAM |
RW |
0 |
|
|
|
0 |
[pcie2axi_ram_ecc_enabled] Disables ECC error injection in
PCIe2AXI RAM |
|
|
|
|
1 |
[pcie2axi_ram_ecc_bypassed] Enables ECC error injection in
PCIe2AXI RAM |
|
|
25 |
RX_RAM_ECC_BYPASS |
ECC Generation and check is bypassed in RX RAM |
RW |
0 |
|
|
|
0 |
[rx_ram_ecc_enabled] Disables
ECC error injection in Rx RAM |
|
|
|
|
1 |
[rx_ram_ecc_bypassed] Enables
ECC error injection in Rx RAM |
|
|
24 |
TX_RAM_ECC_BYPASS |
ECC Generation and check is bypassed in TX RAM |
RW |
0 |
|
|
|
0 |
[tx_ram_ecc_enabled] Disables
ECC error injection in Tx RAM |
|
|
|
|
1 |
[tx_ram_ecc_bypassed] Enables
ECC error injection in Tx RAM |
|
|
23:16 |
Reserved |
|
RO |
0x00 |
|
15:12 |
AXI2PCIe_RAM_INJ_ERR |
Injects a ECC_RAM_ERR occurred in
AXI2PCIe Buffer |
RW |
0x0 |
|
|
|
0x0 |
[axi2pcie_ecc_err_inj_disabled] Disables ECC error
injection in AXI2PCIe Buffer |
|
|
|
|
0x1 |
[axi2pcie_ecc_err_inj_enabled] Enables ECC error injection
in AXI2PCIe Buffer |
|
|
11:8 |
PCIe2AXI_RAM_INJ_ERR |
Injects a ECC_RAM_ERR occurred in
PCIe2AXI Buffer |
RW |
0x0 |
|
|
|
0x0 |
[pcie2axi_ecc_err_inj_disabled] Disables ECC error
injection in PCIe2AXI Buffer |
|
|
|
|
0x1 |
[pcie2axi_ecc_err_inj_enabled] Enables ECC error injection
in PCIe2AXI Buffer |
|
|
7:4 |
RX_RAM_INJ_ERR |
Injects a ECC_RAM_ERR occurred in
RX Buffer |
RW |
0x0 |
|
|
|
0x0 |
[rx_ecc_err_inj_disabled]
Disables ECC error injection in Rx Buffer |
|
|
|
|
0x1 |
[rx_ecc_err_inj_enabled] Enables
ECC error injection in Rx Buffer |
|
|
3:0 |
TX_RAM_INJ_ERR |
Injects a ECC_RAM_ERR occurred in
TX Buffer |
RW |
0x0 |
|
|
|
0x0 |
[tx_ecc_err_inj_disabled]
Disables ECC error injection in Tx Buffer |
|
|
|
|
0x1 |
[tx_ecc_err_inj_enabled] Enables
ECC error injection in Tx Buffer |
|
Address offset |
0x03C |
||
Physical address |
0x0300 603C |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A03C |
pcie_top_1_PCIE_CTRL |
||
Description |
Manually injects ECC error as specified in the address and
data location. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:26 |
Reserved |
|
RO |
0x00 |
25:16 |
ENABLE_ECC_ERR_BYTE_LOC |
When a bit is '1', the error is inserted in the
corresponding byte. The error inserted is specified by the appropriate
ENABLE_ECC_ERR_BIT_LOC |
RW |
0x000 |
15:8 |
ENABLE_ECC_ERR_BIT_LOC |
Enables error on bits specified by the byte. When there is
a '1' the error is inserted in the location. |
RW |
0x00 |
7:0 |
INJECT_ECC_ERR_ADDR |
Injects ECC ERROR as specified at the adress
specified by INJECT_ECC_ERR_ADDR[7:0] |
RW |
0x00 |
Address offset |
0x040 |
||
Physical address |
0x0300 6040 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A040 |
pcie_top_1_PCIE_CTRL |
||
Description |
Registers for RAM Read Margin control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:28 |
Reserved |
|
RO |
0x0 |
27:16 |
TX_BUF_MARGIN |
Controls the read margin for the TX Buffer RAM. |
RW |
0x000 |
15:12 |
Reserved |
|
RO |
0x0 |
11:0 |
RX_BUF_MARGIN |
Controls the read margin for the RX Buffer RAM. |
RW |
0x000 |
Address offset |
0x044 |
||
Physical address |
0x0300 6044 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A044 |
pcie_top_1_PCIE_CTRL |
||
Description |
Registers for RAM Read Margin control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:28 |
Reserved |
|
RO |
0x0 |
27:16 |
A2P_BUF_MARGIN |
Controls the read margin for the AXI2PCIE Buffer RAM. |
RW |
0x000 |
15:12 |
Reserved |
|
RO |
0x0 |
11:0 |
P2A_BUF_MARGIN |
Controls the read margin for the PCIE2AXI Buffer RAM. |
RW |
0x000 |
Address offset |
0x048 |
||
Physical address |
0x0300 6048 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A048 |
pcie_top_1_PCIE_CTRL |
||
Description |
Registers for controlling power in RAMs |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:27 |
Reserved |
|
RO |
0x00 |
|
26:24 |
A2P_BUF_PWR_CTRL |
Controls the power for AXI2PCIE Buffer. |
RW |
0x0 |
|
|
|
0x0 |
[a2p_buf_pwrctrl_full_on] a2p_buf RAM is Full On |
|
|
|
|
0x1 |
[a2p_buf_pwrctrl_light_sleep] a2p_buf RAM is forced to
Light Sleep |
|
|
|
|
0x2 |
[a2p_buf_pwrctrl_deep_sleep] a2p_buf RAM is forced to Deep
Sleep |
|
|
|
|
0x4 |
[a2p_buf_pwrctrl_shutdown] a2p_buf RAM is forced to
Shutdown |
|
|
23:19 |
Reserved |
|
RO |
0x00 |
|
18:16 |
P2A_BUF_PWR_CTRL |
Controls the power for PCIE2AXI Buffer. |
RW |
0x0 |
|
|
|
0x0 |
[p2a_buf_pwrctrl_full_on] p2a_buf RAM is Full On |
|
|
|
|
0x1 |
[p2a_buf_pwrctrl_light_sleep] p2a_buf RAM is forced to
Light Sleep |
|
|
|
|
0x2 |
[p2a_buf_pwrctrl_deep_sleep] p2a_buf RAM is forced to Deep
Sleep |
|
|
|
|
0x4 |
[p2a_buf_pwrctrl_shutdown] p2a_buf RAM is forced to
Shutdown |
|
|
15:11 |
Reserved |
|
RO |
0x00 |
|
10:8 |
TX_BUF_PWR_CTRL |
Controls the power for TX Buffer. |
RW |
0x0 |
|
|
|
0x0 |
[tx_buf_pwrctrl_full_on] tx_buf RAM is Full On |
|
|
|
|
0x1 |
[tx_buf_pwrctrl_light_sleep] tx_buf RAM is forced to Light Sleep |
|
|
|
|
0x2 |
[tx_buf_pwrctrl_deep_sleep] tx_buf RAM is forced to Deep Sleep |
|
|
|
|
0x4 |
[tx_buf_pwrctrl_shutdown] tx_buf RAM is forced to Shutdown |
|
|
7:3 |
Reserved |
|
RO |
0x00 |
|
2:0 |
RX_BUF_PWR_CTRL |
Controls the power for RX Buffer. |
RW |
0x0 |
|
|
|
0x0 |
[rx_buf_pwrctrl_full_on] rx_buf RAM is Full On |
|
|
|
|
0x1 |
[rx_buf_pwrctrl_light_sleep] rx_buf RAM is forced to Light Sleep |
|
|
|
|
0x2 |
[rx_buf_pwrctrl_deep_sleep] rx_buf RAM is forced to Deep Sleep |
|
|
|
|
0x4 |
[rx_buf_pwrctrl_shutdown] rx_buf RAM is forced to Shutdown |
|
Address offset |
0x050 |
||
Physical address |
0x0300 6050 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A050 |
pcie_top_1_PCIE_CTRL |
||
Description |
PCIe Controller fab_debug[31:0] select |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
Reserved |
|
RO |
0x00 0000 |
7:0 |
FAB_DEBUG_SEL |
Controls debug select mux logic |
RW |
0x00 |
Address offset |
0x05C |
||
Physical address |
0x0300 605C |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A05C |
pcie_top_1_PCIE_CTRL |
||
Description |
Captures the LTSSM state fromPCIE
core |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:5 |
Reserved |
|
RO |
0x000 0000 |
4:0 |
PL_LTSSM_OUT |
Captures the LTSSM state Detect.Quiet= 5’h0 Detect.Active= 5’h1 Polling.Active= 5’h2 Polling.Compliance= 5’h3 Polling.Configuration= 5’h4 Configuration.Linkwidth.Start= 5’h5 Configuration.Linkwidth.Accept= 5’h6 Configuration.Lanenum.Wait= 5’h7 Configuration.Lanenum.Accept= 5’h8 Configuration.Complete= 5’h9 Configuration.Idle= 5’hA Recovery.RcvrLock= 5’hB Recovery.Equalization= 5’hC Recovery.Speed= 5’hD Recovery.RcvrCfg= 5’hE Recovery.Idle= 5’hF L0= 5’h10 L0s= 5’h11 L1.Entry= 5’h12 L1.Idle= 5’h13 L2.Idle= 5’h14 L2.TransmitWake= 5’h15 Disabled= 5’h16 Loopback.Entry= 5’h17 Loopback.Active= 5’h18 Loopback.Exit= 5’h19 Hot Reset= 5’h1A |
RO |
0x00 |
Address offset |
0x060 |
||
Physical address |
0x0300 6060 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A060 |
pcie_top_1_PCIE_CTRL |
||
Description |
Captures the state pf PCIE PHY signal which are common to al lanes |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:14 |
Reserved |
|
RO |
0x0 0000 |
13 |
PL_TXDEMPH |
Captures the TX demphasis |
RO |
0 |
12 |
PL_TXSWING |
Captures the TX swing |
RO |
0 |
11 |
Reserved |
|
RO |
0 |
10:8 |
PL_TXMARGIN |
Captures the TX margin |
RO |
0x0 |
7:6 |
Reserved |
|
RO |
0x0 |
5:4 |
PL_RATE |
Captures the link signaling rate |
RO |
0x0 |
3:2 |
Reserved |
|
RO |
0x0 |
1:0 |
PL_POWERDOWN |
Determines the power state (L0,L1,L2..)
|
RO |
0x0 |
Address offset |
0x064 |
||
Physical address |
0x0300 6064 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A064 |
pcie_top_1_PCIE_CTRL |
||
Description |
Captures the per-lane interface signals between the PCIE
and Pipe |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:12 |
Reserved |
|
RO |
0x0 0000 |
11:8 |
PL_TXCOMPLAINCE |
Captures the state of TX compliance per lane |
RO |
0x0 |
7:4 |
PL_TXELECIDLE |
Captures the state of Tx ElecIdle
per lane |
RO |
0x0 |
3:0 |
PL_TXDETRX |
Captures the state of TX Detect RX per lane |
RO |
0x0 |
Address offset |
0x068 |
||
Physical address |
0x0300 6068 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A068 |
pcie_top_1_PCIE_CTRL |
||
Description |
Captures the per-lane interface signals between the PCIe
and Pipe |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:28 |
Reserved |
|
RO |
0x0 |
27:24 |
PL_RXVALID |
Captures the state of RxValid
per lane |
RO |
0x0 |
23:12 |
PL_RXSTATUS |
Captures the three bit RX status
per lane |
RO |
0x000 |
11:8 |
PL_RXELECIDLE |
Captures the state of Rx Elec Idle per lane |
RO |
0x0 |
7:4 |
PL_PHYSTATUS |
Captures the state of phystatus[3:0] per lane |
RO |
0x0 |
3:0 |
PL_RXPOL |
Captures the state of RX Polarity per lane |
RO |
0x0 |
Address offset |
0x06C |
||
Physical address |
0x0300 606C |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A06C |
pcie_top_1_PCIE_CTRL |
||
Description |
Captures the state of Wake Management |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:4 |
Reserved |
|
RO |
0x000 0000 |
|
3 |
PL_WAKE_OVERRIDE |
Overrides the value of WAKE_IN input |
RW |
0 |
|
|
|
0 |
[pl_wake_override_false] |
|
|
|
|
1 |
[pl_wake_override_true] When 0x1 ;Overrides the value of WAKE# input |
|
|
2 |
Reserved |
|
RO |
0 |
|
1 |
PL_WAKEIN |
Captures the state of WAKE_IN |
RO |
0 |
|
|
|
Read 0 |
[pl_wakein_false] Determines the
state of pl_wake_in |
|
|
|
|
Read 1 |
[pl_wakein_true] |
|
|
0 |
PL_WAKEOEN |
Captures the state of Wake_OEN |
RO |
0 |
|
|
|
Read 0 |
[pl_wakeoen_false] Determines
the state of pl_wake_oen |
|
|
|
|
Read 1 |
[pl_wakeoen_true] |
|
Address offset |
0x080 |
||
Physical address |
0x0300 6080 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A080 |
pcie_top_1_PCIE_CTRL |
||
Description |
PCI Configuration Override Enable |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:1 |
Reserved |
|
RO |
0x0000 0000 |
|
0 |
PCICONF_OVERRIDE_EN |
PC BIT override enable for PCIE Bridge Config registers
0x98, 0x9C, 0xA0 |
RW |
0 |
|
|
|
0 |
[pciconf_override_en_false] When
0x0; PCIE Bridge Config registers are accessed through AXI Lite Interface |
|
|
|
|
1 |
[pciconf_override_en_true] When
0x1; PCIE Bridge Config registers are overwritten by below PCIE_PCI_IDS_*
registers |
|
Address offset |
0x084 |
||
Physical address |
0x0300 6084 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A084 |
pcie_top_1_PCIE_CTRL |
||
Description |
PCIe PCI Standard Configuration Identification Settings 31
to 0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
PCI_DEVICE_ID |
PC BIT override value for PCIE Bridge Config register
PCIE_PCI_IDS offset 0x98, bit field Device ID |
RW |
0x0000 |
15:0 |
PCI_VENDOR_ID |
PC BIT override value for PCIE Bridge Config register PCIE_PCI_IDS
offset 0x98, bit field Vendor ID |
RW |
0x0000 |
Address offset |
0x088 |
||
Physical address |
0x0300 6088 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A088 |
pcie_top_1_PCIE_CTRL |
||
Description |
PCIe PCI Standard Configuration Identification Settings 63
to 32 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
PCI_CLASS_CODE |
PC BIT override value for PCIE Bridge Config register
PCIE_PCI_IDS offset 0x9C, bit field Class Code |
RW |
0x00 0000 |
7:0 |
PCI_REVISION_ID |
PC BIT override value for PCIE Bridge Config register
PCIE_PCI_IDS offset 0x9C, bit field Revision ID |
RW |
0x00 |
Address offset |
0x08C |
||
Physical address |
0x0300 608C |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A08C |
pcie_top_1_PCIE_CTRL |
||
Description |
PCIe PCI Standard Configuration Identification Settings 95
to 64 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
PCI_SUBSYSTEM_DEVICE_ID |
PC BIT override value for PCIE Bridge Config register
PCIE_PCI_IDS offset 0xA0, bit field Sub-system Device ID |
RW |
0x0000 |
15:0 |
PCI_SUBSYSTEM_VENDOR_ID |
PC BIT override value for PCIE Bridge Config register
PCIE_PCI_IDS offset 0xA0, bit field Sub-system Vendor ID |
RW |
0x0000 |
Address offset |
0x0A0 |
||
Physical address |
0x0300 60A0 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A0A0 |
pcie_top_1_PCIE_CTRL |
||
Description |
PCie Device,
Link and Specific2 Capabilities Settings Override |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:27 |
Reserved |
|
RO |
0x00 |
|
26:24 |
L1_ACC_LATENCY |
PC BIT override value for PCIE Bridge Config register
PCIE_PEX_DEV offset 0xC0, bit field ASPM L1 exit latency (Max of
1us/2us/4us/8us/16us/32us/64us/noLimit) |
RW |
0x0 |
|
23:21 |
L1_EXIT_DELAY |
PC BIT override value for PCIE Bridge Config register
PCIE_PEX_LINK offset 0xC8, bit field ASPM L1 exit latency |
RW |
0x0 |
|
20:16 |
L1_ENTRY_DELAY |
PC BIT override value for PCIE Bridge Config register
PCIE_PEX_SPC2 offset 0xD8, bit field ASPM L1 entry delay (in steps of 256ns) |
RW |
0x00 |
|
15 |
Reserved |
|
RO |
0 |
|
14:12 |
L0S_ACC_LATENCY |
PC BIT override value for PCIE Bridge Config register PCIE_PEX_DEV
offset 0xC0, bit field ASPM L0s acceptable latency (Max of
64ns/128ns/256ns/512ns/1us/2us/4us/noLimit) |
RW |
0x0 |
|
11:9 |
L0S_EXIT_DELAY |
PC BIT override value for PCIE Bridge Config register
PCIE_PEX_LINK offset 0xC8, bit field ASPM L0s exit latency |
RW |
0x1 |
|
8:4 |
L0S_ENTRY_DELAY |
PC BIT override value for PCIE Bridge Config register
PCIE_PEX_SPC2 offset 0xD8, bit field ASPM L0s entry delay (in steps of 256ns)
|
RW |
0x00 |
|
3:1 |
Reserved |
|
RO |
0x0 |
|
0 |
PEX_DEV_LINK_SPC2_OVERRIDE_EN |
PC BIT override enable for PCIE Bridge Config registers
0xC0, 0xC8 and 0xD8 (bit fields related to L0s, L1 Entry/Exit Delays and
Acceptable Latencies) |
RW |
0 |
|
|
|
0 |
[pex_dev_link_spc2_override_en_false] When 0x0; PCIE Bridge
Config registers are accessed through AXI Lite Interface |
|
|
|
|
1 |
[pex_dev_link_spc2_override_en_true] When 0x1; PCIE Bridge
Config registers are overwritten by below L0s and L1 Entry/Exit Delays and
Acceptable Latencies |
|
Address offset |
0x0A4 |
||
Physical address |
0x0300 60A4 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A0A4 |
pcie_top_1_PCIE_CTRL |
||
Description |
PCIe Specific Cababilities Settings
Override |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:9 |
Reserved |
|
RO |
0x00 0000 |
|
8 |
PCIE_DE_EMPH_LVL |
PC BIT override value for PCIE Bridge Config register
PCIE_PEX_SPC offset 0xD4, bit field Link Selectable De-emphasis |
RW |
0 |
|
7:5 |
Reserved |
|
RO |
0x0 |
|
4 |
PCIE_SLOT_CLK_CONF |
PC BIT override value for PCIE Bridge Config register
PCIE_PEX_SPC offset 0xD4, bit field Slot Clock Configuration |
RW |
0 |
|
3:1 |
Reserved |
|
RO |
0x0 |
|
0 |
PEX_SPC_OVERRIDE_EN |
PC BIT override enable for PCIE Bridge Config registers 0xD4,
bit fields Slot Clock, Link Selectable De-emphasis |
RW |
0 |
|
|
|
0 |
[pex_spc_override_en_false] When
0x0; PCIE Bridge Config registers are accessed through AXI Lite Interface |
|
|
|
|
1 |
[pex_spc_override_en_true] When
0x1; PCIE Bridge Config registers are overwritten by below Slot Clock and
Link De-emphasis bits |
|
Address offset |
0x100 |
||
Physical address |
0x0300 6100 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A100 |
pcie_top_1_PCIE_CTRL |
||
Description |
PCIe Address to AXI Master Address Translation Override
Config0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:12 |
PCIE_AXI_MASTER_ATR_TRSL_ADDR_L |
PC BIT override value for PCIE Bridge Config register
0x608, bit field TRSL_ADDR[31:12] |
RW |
0x0 0000 |
|
11:10 |
Reserved |
|
RO |
0x0 |
|
9:4 |
PCIE_AXI_MASTER_ATR_SIZE |
PC BIT override value for PCIE Bridge Config register
0x600, bit field ATR_SIZE |
RW |
0x00 |
|
3:2 |
Reserved |
|
RO |
0x0 |
|
1 |
PCIE_AXI_MASTER_ATR_IMPL |
PC BIT override value for PCIE Bridge Config register
0x600, bit field ATR_IMPL |
RW |
0 |
|
0 |
PCIE_AXI_MASTER_ATR_OVERRIDE_EN |
PC BIT override enable for PCIE Bridge Config registers
0x0600 to 0x0610 - ATR Config |
RW |
0 |
|
|
|
0 |
[pcie_axi_master_atr_override_en_false]
When 0x0; PCIE Bridge Config registers are accessed through AXI Lite
Interface |
|
|
|
|
1 |
[pcie_axi_master_atr_override_en_true]
When 0x1; PCIE Bridge Config registers are overwritten by below PCIe to AXI
Master TRSL_ADDR[63:12] |
|
Address offset |
0x104 |
||
Physical address |
0x0300 6104 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A104 |
pcie_top_1_PCIE_CTRL |
||
Description |
PCIe Address to AXI Master Address Translation Override
Config1 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
PCIE_AXI_MASTER_ATR_TRSL_ADDR_U |
PC BIT override value for PCIE Bridge Config register
0x60c, bit field TRSL_ADDR[63:32] |
RW |
0x0000 0000 |
Address offset |
0x108 |
||
Physical address |
0x0300 6108 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A108 |
pcie_top_1_PCIE_CTRL |
||
Description |
PCIe Address to AXI Master Address Translation Override
Config2 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
Reserved |
|
RO |
0x0000 |
15:4 |
PCIE_AXI_MASTER_ATR_TRSF_PARAM |
PC BIT override value for PCIE Bridge Config register
0x610, bit field TRSF_PARAM |
RW |
0x000 |
3:0 |
PCIE_AXI_MASTER_ATR_TRSL_ID |
PC BIT override value for PCIE Bridge Config register
0x610, bit field TRSL_ID |
RW |
0x0 |
Address offset |
0x120 |
||
Physical address |
0x0300 6120 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A120 |
pcie_top_1_PCIE_CTRL |
||
Description |
AXI Slave Address to PCIe Address Translation Override
Config0 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:12 |
AXI_SLAVE_PCIE_ATR_TRSL_ADDR_L |
PC BIT override value for PCIE Bridge Config register
0x808, bit field TRSL_ADDR[31:12] |
RW |
0x0 0000 |
|
11:10 |
Reserved |
|
RO |
0x0 |
|
9:4 |
AXI_SLAVE_PCIE_ATR_SIZE |
PC BIT override value for PCIE Bridge Config register
0x800, bit field ATR_SIZE |
RW |
0x00 |
|
3:2 |
Reserved |
|
RO |
0x0 |
|
1 |
AXI_SLAVE_PCIE_ATR_IMPL |
PC BIT override value for PCIE Bridge Config register
0x800, bit field ATR_IMPL |
RW |
0 |
|
0 |
AXI_SLAVE_PCIE_ATR_OVERRIDE_EN |
PC BIT override enable for PCIE Bridge Config registers
0x0800 to 0x810 - ATR Config |
RW |
0 |
|
|
|
0 |
[axi_slave_pcie_atr_override_en_false]
When 0x0; PCIE Bridge Config registers are accessed through AXI Lite
Interface |
|
|
|
|
1 |
[axi_slave_pcie_atr_override_en_true]
When 0x1; PCIE Bridge Config registers are overwritten by below AXI Slave to
PCIe TRSL_ADDR[63:12] |
|
Address offset |
0x124 |
||
Physical address |
0x0300 6124 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A124 |
pcie_top_1_PCIE_CTRL |
||
Description |
AXI Slave Address to PCIe Address Translation Override
Config1 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
AXI_SLAVE_PCIE_ATR_TRSL_ADDR_U |
PC BIT override value for PCIE Bridge Config register
0x80c, bit field TRSL_ADDR[63:32] |
RW |
0x0000 0000 |
Address offset |
0x128 |
||
Physical address |
0x0300 6128 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A128 |
pcie_top_1_PCIE_CTRL |
||
Description |
AXI Slave Address to PCIe Address Translation Override
Config2 |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
Reserved |
|
RO |
0x0000 |
15:4 |
AXI_SLAVE_PCIE_ATR_TRSF_PARAM |
PC BIT override value for PCIE Bridge Config register
0x810, bit field TRSF_PARAM |
RW |
0x000 |
3:0 |
AXI_SLAVE_PCIE_ATR_TRSL_ID |
PC BIT override value for PCIE Bridge Config register
0x810, bit field TRSL_ID |
RW |
0x0 |
Address offset |
0x140 |
||
Physical address |
0x0300 6140 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A140 |
pcie_top_1_PCIE_CTRL |
||
Description |
PCIe BAR 0 and 1 Settings Override |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:25 |
Reserved |
|
RO |
0x00 |
|
24:20 |
PEX_BAR1_SIZE |
BAR 1 Size |
RW |
0x00 |
|
19:16 |
PEX_BAR1_CTRL |
BAR 1 Control |
RW |
0x0 |
|
15:13 |
Reserved |
|
RO |
0x0 |
|
12:8 |
PEX_BAR0_SIZE |
BAR 0 Size |
RW |
0x00 |
|
7:4 |
PEX_BAR0_CTRL |
BAR 0 Control |
RW |
0x0 |
|
3:1 |
Reserved |
|
RO |
0x0 |
|
0 |
PEX_BAR01_OVERRIDE_EN |
PC BIT override enable for PCIE Bridge Config registers
0xE4, 0xE8 BAR 0/1 Settings |
RW |
0 |
|
|
|
0 |
[pex_bar01_override_en_false] When 0x0; PCIE Bridge Config
registers are accessed through AXI Lite Interface |
|
|
|
|
1 |
[pex_bar01_override_en_true] When 0x1; PCIE Bridge Config
registers are overwritten by below BAR 0/1 Ctrl, Size |
|
Address offset |
0x144 |
||
Physical address |
0x0300 6144 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A144 |
pcie_top_1_PCIE_CTRL |
||
Description |
PCIe BAR 2 and 3 Settings Override |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:25 |
Reserved |
|
RO |
0x00 |
|
24:20 |
PEX_BAR3_SIZE |
BAR 3 Size |
RW |
0x00 |
|
19:16 |
PEX_BAR3_CTRL |
BAR 3 Control |
RW |
0x0 |
|
15:13 |
Reserved |
|
RO |
0x0 |
|
12:8 |
PEX_BAR2_SIZE |
BAR 2 Size |
RW |
0x00 |
|
7:4 |
PEX_BAR2_CTRL |
BAR 2 Control |
RW |
0x0 |
|
3:1 |
Reserved |
|
RO |
0x0 |
|
0 |
PEX_BAR23_OVERRIDE_EN |
PC BIT override enable for PCIE Bridge Config registers
0xEC, 0xF0 BAR 2/3 Settings |
RW |
0 |
|
|
|
0 |
[pex_bar23_override_en_false] When 0x0; PCIE Bridge Config
registers are accessed through AXI Lite Interface |
|
|
|
|
1 |
[pex_bar23_override_en_true] When 0x1; PCIE Bridge Config
registers are overwritten by below BAR 2/3 Ctrl, Size |
|
Address offset |
0x148 |
||
Physical address |
0x0300 6148 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A148 |
pcie_top_1_PCIE_CTRL |
||
Description |
PCIe BAR 4 and 5 Settings Override |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:25 |
Reserved |
|
RO |
0x00 |
|
24:20 |
PEX_BAR5_SIZE |
BAR 5 Size |
RW |
0x00 |
|
19:16 |
PEX_BAR5_CTRL |
BAR 5 Control |
RW |
0x0 |
|
15:13 |
Reserved |
|
RO |
0x0 |
|
12:8 |
PEX_BAR4_SIZE |
BAR 4 Size |
RW |
0x00 |
|
7:4 |
PEX_BAR4_CTRL |
BAR 4 Control |
RW |
0x0 |
|
3:1 |
Reserved |
|
RO |
0x0 |
|
0 |
PEX_BAR45_OVERRIDE_EN |
PC BIT override enable for PCIE Bridge Config registers
0xF4, 0xF8 BAR 4/5 Settings |
RW |
0 |
|
|
|
0 |
[pex_bar45_override_en_false] When 0x0; PCIE Bridge Config
registers are accessed through AXI Lite Interface |
|
|
|
|
1 |
[pex_bar45_override_en_true] When 0x1; PCIE Bridge Config
registers are overwritten by below BAR 4/5 Ctrl, Size |
|
Address offset |
0x14C |
||
Physical address |
0x0300 614C |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A14C |
pcie_top_1_PCIE_CTRL |
||
Description |
L2 Exit, Hot reset exit and DLUp
exit interrupt |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:19 |
Reserved |
|
RO |
0x0000 |
|
18 |
DLUP_EXIT_INT_MASK |
Indicates whether Dlup exit from
PCIe should contribute to pcie interrupt or not |
RW |
0 |
|
|
|
0 |
[dlup_exit_int_unmask] Indicates
that the dlup exit event contributes to pcie_interrupt |
|
|
|
|
1 |
[dlup_exit_int_mask] Indicates
that the dlup exit event contribution to pcie_interrupt is masked |
|
|
17 |
HOTRST_EXIT_INT_MASK |
Indicates whether Hot reset exit from PCIe should
contribute to pcie interrupt or not |
RW |
0 |
|
|
|
0 |
[hotrst_exit_int_unmask]
Indicates that the hot reset exit event contributes to pcie_interrupt
|
|
|
|
|
1 |
[hotrst_exit_int_mask] Indicates
that the hot reset exit event contribution to pcie_interrupt
is masked |
|
|
16 |
L2_EXIT_INT_MASK |
Indicates whether L2 exit from PCIe should contribute to pcie interrupt or not |
RW |
0 |
|
|
|
0 |
[l2_exit_int_unmask] Indicates that the l2 exit event
contributes to pcie_interrupt |
|
|
|
|
1 |
[l2_exit_int_mask] Indicates that the l2 exit event
contribution to pcie_interrupt is masked |
|
|
15:3 |
Reserved |
|
RO |
0x0000 |
|
2 |
DLUP_EXIT_INT |
Indicates Dlup exit event
occurred |
RW |
0 |
|
|
|
0 |
[dlup_exit_event_not_encountered]
Indicates that the Dlup exit event is not
encountered in PCIe |
|
|
|
|
1 |
[dlup_exit_event_encountered]
Indicates that the Dlup exit event is encountered
in PCIe |
|
|
1 |
HOTRST_EXIT_INT |
Indicates Hot Reset exit event occurred |
RW |
0 |
|
|
|
0 |
[hotrst_exit_event_not_encountered]
Indicates that the Hot Reset exit event is not encountered in PCIe |
|
|
|
|
1 |
[hotrst_exit_event_encountered]
Indicates that the Hot Reset exit event is encountered in PCIe |
|
|
0 |
L2_EXIT_INT |
Indicates L2 exit event occurred |
RW |
0 |
|
|
|
0 |
[l2_exit_event_not_encountered] Indicates that the L2 exit
event is not encountered in PCIe |
|
|
|
|
1 |
[l2_exit_event_encountered] Indicates that the L2 exit
event is encountered in PCIe |
|
Address offset |
0x150 |
||
Physical address |
0x0300 6150 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A150 |
pcie_top_1_PCIE_CTRL |
||
Description |
Spare register for scratch-pad
and repair purposes |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
SPARE_CTRL |
Spare Control for future Use |
RW |
0x00 0000 |
7:0 |
SCRATCHPAD |
Scratch-pad within
PCIE ctrl register space Bit-0 Dynamic control of PERSTn
port. Bit-0 of these registers drives PERSTn
and it's reset/default value will be ‘1’ in this
case. Root port RTL passes all APB transactions to PCIe controller through
link interface with respect to PERSTN |
RW |
0x00 |
Address offset |
0x180 |
||
Physical address |
0x0300 6180 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 A180 |
pcie_top_1_PCIE_CTRL |
||
Description |
PCIe Rootport Windows Settings
Override |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:8 |
Reserved |
|
RO |
0x00 0000 |
|
7:4 |
PEX_BAR_WIN_CTRL |
BAR Window Control |
RW |
0x0 |
|
3:1 |
Reserved |
|
RO |
0x0 |
|
0 |
PEX_BAR_WIN_OVERRIDE_EN |
PC BIT override enable for PCIE Bridge Config registers
0xFC BAR Win Settings |
RW |
0 |
|
|
|
0 |
[pex_bar_win_override_en_false] When
0x0; PCIE Bridge Config registers are accessed through AXI Lite Interface |
|
|
|
|
1 |
[pex_bar_win_override_en_true]
When 0x1; PCIE Bridge Config registers are overwritten by below BAR Ctrl |
|
Address offset |
0xC80 |
||
Physical address |
0x0300 6C80 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 AC80 |
pcie_top_1_PCIE_CTRL |
||
Description |
Controls the test_bus_in (31:0)
of PCIE core |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:22 |
Reserved |
|
RO |
0x000 |
21 |
TEST_BUS_IN_BIT21_DISABLE_SKP_PARITY |
test_in[21] = Disable
SKP Parity in Scrambler block |
RW |
0 |
20 |
TEST_BUS_IN_BIT20_CHECK_DCBALANCE |
test_in[20] = This
is a simulation only feature to check DC Balance in RX Mode; This is not in
PCIE Doc; but found in pcie3_coreconfig_h.v |
RW |
0 |
19 |
TEST_BUS_IN_BIT19_EXT_SIM_MODE |
test_in[19] =
Extended simulation mode (see Section 14.2 of PCIE PCIe
Ref Manual) |
RW |
0 |
18 |
TEST_BUS_IN_BIT18_NULLIFIED_WRTX |
test_in[18] = Do
not write nullified TLP to TX Buffer when value is 0; This is not in PCIE
Doc; but found in pcie3_coreconfig_h.v |
RW |
0 |
17:15 |
Reserved |
|
RO |
0x0 |
14 |
TEST_BUS_IN_BIT14_DIS_PHY_STATUS_TO |
test_in[14] =
Disable PHY status timeout |
RW |
0 |
13:11 |
Reserved |
|
RO |
0x0 |
10 |
TEST_BUS_IN_BIT10_FORCE_PLL_CMPL_ENTRY |
test_in[10] =
Force entry in Polling.Compliance from Polling.active |
RW |
0 |
9 |
TEST_BUS_IN_BIT9_DIS_POLL_CMPL_ENTRY |
test_in[9] =
Disable entry in Polling.Compliance from Polling.active (does not apply if the compliance receive
bit is set). |
RW |
0 |
8 |
TEST_BUS_IN_BIT8_TS2_DEEMPH_BIT_SEL |
test_in[8] = Set
selectable deemphasis bit in transmitted TS2 ordered set (upstream devices
only) |
RW |
0 |
7 |
TEST_BUS_IN_BIT7_CMPL_RCV_BIT |
test_in[7] = Set compliance
receive bit in transmitted TS1 ordered set |
RW |
0 |
6 |
TEST_BUS_IN_BIT6_DIS_SCRAMBLING |
test_in[6] =
Disable scrambling (Gen1/Gen2 modes only). |
RW |
0 |
5 |
Reserved |
|
RO |
0 |
4 |
TEST_BUS_IN_BIT4_EN_INFO_ASSERT |
test_in[4] =
Enable information assertions |
RW |
0 |
3 |
TEST_BUS_IN_BIT3_EN_WARN_ASSERT |
test_in[3] =
Enable warning assertions |
RW |
0 |
2 |
TEST_BUS_IN_BIT2_LBACK_MST |
test_in[2] =
Loopback Master: This signal must be set to 1 to direct the Link to loopbak (in Master mode) |
RW |
0 |
1 |
TEST_BUS_IN_BIT1_DIS_LPWR_STATE_NEG |
test_in[1] =
Disable Low Power State Negotiation: When asserted, this signal disables all
low power state negotiation |
RW |
0 |
0 |
TEST_BUS_IN_BIT0_SIM_MODE |
test_in[0] =
Simulation Mode: This signal must be set to 1 to set simulation mode (see
Section 14.2 in PCIE PCIe Ref Manual) |
RW |
0 |
Address offset |
0xC84 |
||
Physical address |
0x0300 6C84 |
Instance |
pcie_top_0_PCIE_CTRL |
0x0300 AC84 |
pcie_top_1_PCIE_CTRL |
||
Description |
Controls the test_bus_in (63:32)
of PCIE core |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TEST_BUS_IN_BF_63_32 |
Please refer to PCIE spec on controls for test_bus_in. |
RW |
0x0000 0000 |
PCIE_CTRL has no
common memories.