Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0205 0000

OVRLY

RW

32

0x0000 0101

0x004

0x0205 0004

MAJOR

RW

32

0x0000 000B

0x008

0x0205 0008

INT_PIPE_CLK_CTRL

RW

32

0x0000 0000

0x00C

0x0205 000C

EXT_PIPE_CLK_CTRL

RW

32

0x0000 0000

0x010

0x0205 0010

CLK_CTRL

RW

32

0x0000 0000

0x014

0x0205 0014

QMUX_R0

RW

32

0x0007 0031

0x018

0x0205 0018

DLL_CTRL0

RW

32

0x8800 000F

0x100

0x0205 0100

DLL_CTRL1

RW

32

0x0000 0000

0x104

0x0205 0104

DLL_STAT0

RW

32

0x0000 1801

0x108

0x0205 0108

DLL_STAT1

RO

32

0x0000 0000

0x10C

0x0205 010C

DLL_STAT2

RO

32

0x0000 0000

0x110

0x0205 0110

TEST_DLL

RW

32

0x0000 0000

0x118

0x0205 0118

SPARE

RW

32

0x0000 0000

0x190

0x0205 0190

Address offset

0x000

Physical address

0x0205 0000

Instance

PCIESS_MAIN

Description

Compulsory register for all SCB slaves, facilitating global soft reset.

Type

RW

31:16

BLOCKID

This returns the block type and chip location. The form of BLOCKID = {4'h0, SLVTYPE, CHIPID, SUBID}. SLVTYPE=4'h2 for PCIESS MAIN. CHIPID=4'h0 for PCIESS. SUBID=4'h4 for the MAIN page.

RO

0x0000

Read 0x0000

[block_address_PCIESS_MAIN] Indicates the Block chip location.

15:9

Reserved

RO
Rreturns0s

0x00

8

PERIPH

This asserts functional reset of the peripheral block. It is asserted and left asserted at power-up.

WO

0

Write 0

[scb_periph_not_in_soft_reset_PCIESS_MAIN] Reset not asserted.

Write 1

[scb_periph_reset_PCIESS_MAIN] SCB registers reset pulsed.

7:2

Reserved

RO
Rreturns0s

0x00

1

V_MAP

Resets all the volatile register bits.

WO

0

Write 0

[scb_v_regs_not_in_soft_reset_PCIESS_MAIN] Reset not asserted.

Write 1

[scb_v_regs_reset_PCIESS_MAIN] SCB Volatile reset (i.e. RW-X registers are reset)

0

NV_MAP

Resets all the non-volatile register bits (e.g. RW-P bits).

WO

0

Write 0

[scb_nv_regs_not_in_soft_reset_PCIESS_MAIN] Reset not asserted.

Write 1

[scb_nv_regs_reset_PCIESS_MAIN] SCB Non-Volatile reset (i.e. RW-P registers are reset.

Address offset

0x004

Physical address

0x0205 0004

Instance

PCIESS_MAIN

Description

Controls Identity of Fabric Pin Functions

Type

RW

31:10

Reserved

RO
Rreturns0s

0x00 0000

9:8

AXI1_IFC_MODE

Sets overlaid AXI1 pins to a gated-off state, assume their AXI functions, or assume their PCS lane 2 and 3 functions.

RW

0x1

0x0

[overlaid_axi1_pins_are_gated_off] Overlaid AXI0 pins are neither AXI, nor PCS.

0x1

[overlaid_axi1_pins_are_axi] Overlaid AXI0 pins assume their AXI functonality.

0x2

[overlaid_axi1_pins_are_pcs_0_1] Overlaid AXI0 pins assume their PCS lane 0 and 1 functionality.

7:2

Reserved

RO
Rreturns0s

0x00

1:0

AXI0_IFC_MODE

Sets overlaid AXI0 pins to a gated-off state, assume their AXI functions, or assume their PCS lane 0 and 1 functions.

RW

0x1

0x0

[overlaid_axi0_pins_are_gated_off] Overlaid AXI0 pins are neither AXI, nor PCS.

0x1

[overlaid_axi0_pins_are_axi] Overlaid AXI0 pins assume their AXI functonality.

0x2

[overlaid_axi0_pins_are_pcs_0_1] Overlaid AXI0 pins assume their PCS lane 0 and 1 functionality.

Address offset

0x008

Physical address

0x0205 0008

Instance

PCIESS_MAIN

Description

Controls how PCIe Controllers bind to PCS/PMA lanes.

Type

RW

31:4

Reserved

RO
Rreturns0s

0x000 0000

3:0

PCIE_USAGE_MODE

Determines the major mode of operation for the PCIESS block.

RW

0xB

0x2

[pcie0_ext23_pcie1_unused] PCIe Controller 0 is allocated PCS/PMA lanes 2 and 3 of the South-adjacent GPSS block. Lane 2 is really wired to the controller's lane 0 input and lane 3 is wired to the controller's lane 1 input.
PCIe Controller 1 is not allocated any lanes.

0x3

[pcie0_ext23_pcie1_int4] PCIe Controller 0 is allocated PCS/PMA lanes 2 and 3 of the South-adjacent GPSS block.
PCIe Controller 1 is allocated all four PCS/PMA lanes of the PCIESS.

0x4

[pcie0_int01_pcie1_int23] PCIe Controller 0 is allocated PCS/PMA lanes 0 and 1 of the PCIESS quad.
PCIe Controller 1 is allocated PCS/PMA lanes 2 and 3 of the PCIESS quad.

0x6

[pcie0_int01_pcie1_unused] PCIe Controller 0 is allocated PCS/PMA lanes 0 and 1 of the PCIESS quad.
PCIe Controller 1 is not allocated any lanes.

0x8

[pcie0_unused_pcie1_int23] PCIe Controller 0 is not allocated any lanes.
PCIe Controller 1 is allocated PCS/PMA lanes 2 and 3 of the PCIESS block.

0xA

[pcie0_unused_pcie1_unused] PCIe Controller 0 is not allocated any PCS/PMA lanes.
PCIe Controller 1 is not allocated any PCS/PMA lanes.

0xB

[pcie0_unused_pcie1_int4] PCIe Controller 0 is not allocated any lanes.
PCIe Controller 1 is allocated all four PCS/PMA lanes of the PCIESS block.

0xE

[pcie0_ext4_pcie1_unused] PCIe Controller 0 is allocated all four PCS/PMA lanes of the South-adjacent GPSS block.
PCIe Controller 1 is not allocated any lanes.

0xF

[pcie0_ext4_pcie1_int4] PCIe Controller 0 is allocated all four PCS/PMA lanes of the South-adjacent GPSS block.
PCIe Controller 1 is allocated all four PCS/PMA lanes of the PCIESS.

Address offset

0x00C

Physical address

0x0205 000C

Instance

PCIESS_MAIN

Description

Controls quad-level clocking.

Type

RW

31:26

Reserved

RO
Rreturns0s

0x00

25

PCLK_INT_LN3_SEL

Selects source of internal lane 3 PIPE input clock.

RW

0

0

[int_lane3_pipe_clock_same_as_pcie_1]

1

[int_lane3_pipe_clock_off]

24

PCLK_INT_LN2_SEL

Selects source of internal lane 2 PIPE input clock.

RW

0

0

[int_lane2_pipe_clock_same_as_pcie_1]

1

[int_lane2_pipe_clock_off]

23:20

Reserved

RO
Rreturns0s

0x0

19:18

PCLK_INT_LN1_SEL

Selects source of internal lane 1 PIPE input clock.

RW

0x0

0x0

[int_lane1_pipe_clock_same_as_pcie_0]

0x1

[int_lane1_pipe_clock_same_as_pcie_1]

0x2

[int_lane1_pipe_clock_off]

17:16

PCLK_INT_LN0_SEL

Selects source of internal lane 0 PIPE input clock.

RW

0x0

0x0

[int_lane0_pipe_clock_same_as_pcie_0]

0x1

[int_lane0_pipe_clock_same_as_pcie_1]

0x2

[int_lane0_pipe_clock_off]

15:11

Reserved

RO
Rreturns0s

0x00

10:8

PCIE_1_PCLK_SEL

Selects source of PCIe Controller 1's PIPE clock.

RW

0x0

0x0

[pcie1_clock_from_int_pipe_lane_0]

0x1

[pcie1_clock_from_int_pipe_lane_1]

0x2

[pcie1_clock_from_int_pipe_lane_2]

0x3

[pcie1_clock_from_int_pipe_lane_3]

0x4

[pcie1_clock_off]

7:3

Reserved

RO
Rreturns0s

0x00

2:0

PCIE_0_PCLK_SEL

Selects source of PCIe Controller 0's PIPE clock.

RW

0x0

0x0

[pcie0_clock_from_int_pipe_lane_0]

0x1

[pcie0_clock_from_int_pipe_lane_1]

0x2

[pcie0_clock_from_ext_pipe_lane_0]

0x3

[pcie0_clock_from_ext_pipe_lane_1]

0x4

[pcie0_clock_from_ext_pipe_lane_2]

0x5

[pcie0_clock_from_ext_pipe_lane_3]

0x6

[pcie0_clock_off]

Address offset

0x010

Physical address

0x0205 0010

Instance

PCIESS_MAIN

Description

Type

RW

31:4

Reserved

RO
Rreturns0s

0x000 0000

3

PCLK_EXT_LN3_SEL

Selects source of external lane 3 PIPE input clock.

RW

0

0

[ext_lane3_pipe_clock_same_as_pcie_0]

1

[ext_lane3_pipe_clock_off]

2

PCLK_EXT_LN2_SEL

Selects source of external lane 2 PIPE input clock.

RW

0

0

[ext_lane2_pipe_clock_same_as_pcie_0]

1

[ext_lane2_pipe_clock_off]

1

PCLK_EXT_LN1_SEL

Selects source of external lane 1 PIPE input clock.

RW

0

0

[ext_lane1_pipe_clock_same_as_pcie_0]

1

[ext_lane1_pipe_clock_off]

0

PCLK_EXT_LN0_SEL

Selects source of external lane 0 PIPE input clock.

RW

0

0

[ext_lane0_pipe_clock_same_as_pcie_0]

1

[ext_lane0_pipe_clock_off]

Address offset

0x014

Physical address

0x0205 0014

Instance

PCIESS_MAIN

Description

Controls AXI clocking.

Type

RW

31:9

Reserved

RO
Rreturns0s

0x00 0000

8

AXI1_CLKENA

AXI1 clock enable.

RW

0

0

[axi_clk_ctrl_axi1_clock_disabled] Forces AXI clock to PCI-Express controller 1 to stop toggling.

1

[axi_clk_crtl_axi1_clock_enabled] Allows AXI clock to PCI-Express controller 1 to toggle.

7:1

Reserved

RO
Rreturns0s

0x00

0

AXI0_CLKENA

AXI0 clock enable.

RW

0

0

[axi_clk_ctrl_axi0_clock_disabled] Forces AXI clock to PCI-Express controller 0 to stop toggling.

1

[axi_clk_crtl_axi0_clock_enabled] Allows AXI clock to PCI-Express controller 0 to toggle.

Address offset

0x018

Physical address

0x0205 0018

Instance

PCIESS_MAIN

Description

Output Mux Settings

Type

RW

31:19

Reserved

RO
Rreturns0s

0x0000

18:16

PCIE_DBG_SEL

Selects fab_pcie_debug fabric debug output bus from the two PCIe controller 32-bit debug output port bits.

RW

0x7

0x0

[pcie_dbg_all_from_c0] fab_pcie_debug entirely sourced from PCIe controller 0.

0x1

[pcie_dbg_all_from_c1] fab_pcie_debug entirely sourced from PCIe controller 1.

0x2

[pcie_dbg_c0lh_c1lh] fab_pcie_debug[15:0] from PCIe controller 0 debug bits [15:0]; fab_pcie_debug[31:16] from PCIe controller 1 debug bits [15:0].

0x3

[pcie_dbg_c0uh_c1uh] fab_pcie_debug[15:0] from PCIe controller 0 debug bits [31:16]; fab_pcie_debug[31:16] from PCIe controller 1 debug bits [31:16].

0x4

[pcie_dbg_c0lh_c1uh] fab_pcie_debug[15:0] from PCIe controller 0 debug bits [15:0]; fab_pcie_debug[31:16] from PCIe controller 1 debug bits [31:16].

0x5

[pcie_dbg_c0uh_c1lh] fab_pcie_debug[15:0] from PCIe controller 0 debug bits [31:16]; fab_pcie_debug[31:16] from PCIe controller 1 debug bits [15:0].

0x7

[pcie_dbg_off] All zeroes output on fab_pcie_debug.

15

Reserved

RO
Rreturns0s

0

14:12

QRST3_SRC

Selects source of h2f_quad_reset_1_b

RW

0x0

0x0

[qrst3_is_c0_axi] h2f_quad_reset_3_b is driven by reset of controller 0's AXI4 domain

0x1

[qrst3_is_c0_tl] h2f_quad_reset_3_b is driven by reset of controller 0's TL domain

0x2

[qrst3_is_c0_bridge] h2f_quad_reset_3_b is driven by reset of controller 0's bridge domain

0x3

[qrst3_is_c1_axi] h2f_quad_reset_3_b is driven by reset of controller 1's AXI4 domain

0x4

[qrst3_is_c1_tl] h2f_quad_reset_3_b is driven by reset of controller 1's TL domain

0x5

[qrst3_is_c1_bridge] h2f_quad_reset_3_b is driven by reset of controller 1's bridge domain

0x6

[qrst3_is_pcs_rst_1] h2f_quad_reset_3_b is driven by G5_PCSPMA quad_reset_1_b

11

Reserved

RO
Rreturns0s

0

10:8

QRST2_SRC

Selects source of h2f_quad_reset_0_b

RW

0x0

0x0

[qrst2_is_c0_axi] h2f_quad_reset_2_b is driven by reset of controller 0's AXI4 domain

0x1

[qrst2_is_c0_tl] h2f_quad_reset_2_b is driven by reset of controller 0's TL domain

0x2

[qrst2_is_c0_bridge] h2f_quad_reset_2_b is driven by reset of controller 0's bridge domain

0x3

[qrst2_is_c1_axi] h2f_quad_reset_2_b is driven by reset of controller 1's AXI4 domain

0x4

[qrst2_is_c1_tl] h2f_quad_reset_2_b is driven by reset of controller 1's TL domain

0x5

[qrst2_is_c1_bridge] h2f_quad_reset_2_b is driven by reset of controller 1's bridge domain

0x6

[qrst2_is_pcs_rst_0] h2f_quad_reset_2_b is driven by G5_PCSPMA quad_reset_0_b

7

Reserved

RO
Rreturns0s

0

6:4

QRST1_SRC

Selects source of h2f_quad_reset_1_b

RW

0x3

0x0

[qrst1_is_c0_axi] h2f_quad_reset_1_b is driven by reset of controller 0's AXI4 domain

0x1

[qrst1_is_c0_tl] h2f_quad_reset_1_b is driven by reset of controller 0's TL domain

0x2

[qrst1_is_c0_bridge] h2f_quad_reset_1_b is driven by reset of controller 0's bridge domain

0x3

[qrst1_is_c1_axi] h2f_quad_reset_1_b is driven by reset of controller 1's AXI4 domain

0x4

[qrst1_is_c1_tl] h2f_quad_reset_1_b is driven by reset of controller 1's TL domain

0x5

[qrst1_is_c1_bridge] h2f_quad_reset_1_b is driven by reset of controller 1's bridge domain

0x6

[qrst1_is_pcs_rst_1] h2f_quad_reset_1_b is driven by G5_PCSPMA quad_reset_1_b

3

Reserved

RO
Rreturns0s

0

2:0

QRST0_SRC

Selects source of h2f_quad_reset_0_b

RW

0x1

0x0

[qrst0_is_c0_axi] h2f_quad_reset_0_b is driven by reset of controller 0's AXI4 domain

0x1

[qrst0_is_c0_tl] h2f_quad_reset_0_b is driven by reset of controller 0's TL domain

0x2

[qrst0_is_c0_bridge] h2f_quad_reset_0_b is driven by reset of controller 0's bridge domain

0x3

[qrst0_is_c1_axi] h2f_quad_reset_0_b is driven by reset of controller 1's AXI4 domain

0x4

[qrst0_is_c1_tl] h2f_quad_reset_0_b is driven by reset of controller 1's TL domain

0x5

[qrst0_is_c1_bridge] h2f_quad_reset_0_b is driven by reset of controller 1's bridge domain

0x6

[qrst0_is_pcs_rst_0] h2f_quad_reset_0_b is driven by G5_PCSPMA quad_reset_0_b

Address offset

0x100

Physical address

0x0205 0100

Instance

PCIESS_MAIN

Description

DLL control register 0

Type

RW

31:28

LOCK_LOW

accumulating 3~15 cycles of phase detector lock low, 00xx=3 cycles

RW

0x8

27:24

LOCK_HIGH

accumulating 3~15 cycles of phase detector lock high, 00xx=3 cycles

RW

0x8

23:22

Reserved

RO

0x0

21:20

LOCK_FLT

Phase lock tolerance: 00 (Default) +/- 50~130ps, 01 +/- 110~270ps, 10 +/- 200~470ps, 11 +/- 280~680ps

RW

0x0

19

LOCK_FRC

force lock high for debugging purpose

RW

0

18:16

Reserved

RO

0x0

15:14

ALU_UPD

00=ALU update after 16 accumulated cycles of add or subtract; 01=8 cycles; 10=32 cycles; 11=4 cycles

RW

0x0

13:11

Reserved

RO

0x0

10

DIV_SEL

divided feedback clock select in clock injection removal mode: 0=M4/M5 selects 0/1; 1=M4/M5 selects 2/3

RW

0

9

FB_SEL

feedback clock selection: 0=direct feedback or through dummy delay to match divider on reference; 1=2*pi shift for clock phase reference mode or feedback through dummy delay inversion

RW

0

8

REF_SEL

reference clock selection: 0=/1 or /2 0 shift; 1=pi shift for delay match mode or /4 0 shift

RW

0

7:6

SEL_S

secondary clock output selection: 00=normal; 01=/2; 10=/4; 11=duty 50 when ref_sel=0 and fb_sel=1 for clock phase reference mode (reg_div_sel=0)

RW

0x0

5:4

SEL_P

primary clock output selection: 00=normal; 01=normal through dummy delay to match divider on clko_s; 10=duty 50 when ref_sel=0 and fb_sel=1 for clock phase reference mode (reg_div_sel=0); 11=duty 50 inversion

RW

0x0

3:2

PHASE_S

secondary clock phase selection: 00=pi/2 shift; 01=pi shift; 10=3*pi/2 shift; 11=2*pi shift

RW

0x3

1:0

PHASE_P

primary clock phase selection: 00=0 shift; 01=pi/2 shift; 10=pi shift; 11=2*pi shift

RW

0x3

Address offset

0x104

Physical address

0x0205 0104

Instance

PCIESS_MAIN

Description

DLL control register 1

Type

RW

31

Reserved

RO

0

30

RELOCK_FAST

 At unlock, keep locking without counting down to 0 first in clock injection removal mode

RW

0

29:24

INIT_CODE

 force ALU to count to the minimum initial delay in each delay cell from 0 (00000) to 63 (11111) taps

RW

0x00

23

TEST_RING

 enable ring oscillator test mode

RW

0

22:16

Reserved

RO

0x00

15

TEST_S

 select clko_s to drive ring oscillator in test mode

RW

0

14:8

ADJ_DEL4

 adjust fine phase shift in DEL4, when MSB=1, subtract reg_adj_del4[5:0]; otherwise add reg_adj_del4[5:0]

RW

0x00

7:0

SET_ALU

 when reg_set_alu[7]=1, manual set ALU to reg_set_alu[6:0]

RW

0x00

Address offset

0x108

Physical address

0x0205 0108

Instance

PCIESS_MAIN

Description

DLL status register 0

Type

RW

31:24

Reserved

RO

0x00

23:16

Reserved

RO

0x00

15:14

Reserved

RO

0x0

13

Reserved

RO

0

12

PHASE_MOVE_CLK

 fine phase shifting on clko_s when going high, has to go low before the next shifting

RW

1

11

UNLOCK_INT

 unlock interrupt

RW
W1toClr

1

10

LOCK_INT

 lock interrupt

RW
W1toClr

0

9

UNLOCK_INT_EN

 enable unlock interrupt

RW

0

8

LOCK_INT_EN

 enable lock interrupt

RW

0

7:5

Reserved

RO

0x0

4

Reserved

RO

0

3

Reserved

RO

0

2

Reserved

RO

0

1

Reserved

RO

0

0

RESET

 active high reset of DLL

RW

1

Address offset

0x10C

Physical address

0x0205 010C

Instance

PCIESS_MAIN

Description

DLL status register 1

Type

RO

31:30

Reserved

RO

0x0

29:28

Reserved

RO

0x0

27:26

Reserved

RO

0x0

25

Reserved

RO

0

24:16

SRO_ALU_CNT

 ALU counter value, upper 7-bits are DEL0 setting

RO

0x000

15:8

Reserved

RO

0x00

7

Reserved

RO

0

6:0

SRO_DEL4

 same as delay_code output

RO

0x00

Address offset

0x110

Physical address

0x0205 0110

Instance

PCIESS_MAIN

Description

DLL status register 2

Type

RO

31:24

Reserved

RO

0x00

23:16

Reserved

RO

0x00

15:7

Reserved

RO

0x000

6

Reserved

RO

0

5

Reserved

RO

0

4

Reserved

RO

0

3

Reserved

RO

0

2

SRO_LOCK

 same as lock output

RO

0

1

Reserved

RO

0

0

Reserved

RO

0

Address offset

0x118

Physical address

0x0205 0118

Instance

PCIESS_MAIN

Description

MSCC Silicon Test for DLL

Type

RW

31:2

Reserved

RO
Rreturns0s

0x0000 0000

1

REF_ENABLE

During silicon testing the reference clock is suppressible such that the delay chain may be fully initialized to full-rail voltages.

RW

0

0

[test_dll_ref_enable_false] Suppress reference clock during ring-oscillator DLL test.

1

[test_dll_ref_enable_true] Allow reference clock toggling during ring-oscillator DLL test.

0

RING_OSC_ENABLE

For silicon testing of the clock-injection cancellation DLL used for fab_axi4_clk. This is a non-functional test mode.

RW

0

0

[test_dll_ring_osc_enable_false] Disable ring-oscillator mode for misson mode.

1

[test_dll_ring_osc_enable_true] Enable the ring-oscillator mode for silicon test.

Address offset

0x190

Physical address

0x0205 0190

Instance

PCIESS_MAIN

Description

Spare reg for scratch-pad and repair purposes.

Type

RW

31:8

SPARE_CTRL

Spare control for future use.

RW

0x00 0000

7:0

SCRATCHPAD

Scratch-pad within PCIESS address space.

RW

0x00