Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

SOFT_RESET

RW

32

0x0000 0000

0x000

GSSCLK_CTRL

RW

32

0x0000 0000

0x004

QRST_R0

RW

32

0x0000 0000

0x008

QDBG_R0

RW

32

0x0000 1000

0x00C

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0005 0000

GSSCLK_CTRL

RW

32

0x0000 0000

0x004

0x0005 0004

QRST_R0

RW

32

0x0000 0000

0x008

0x0005 0008

QDBG_R0

RW

32

0x0000 1000

0x00C

0x0005 000C

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0009 0000

GSSCLK_CTRL

RW

32

0x0000 0000

0x004

0x0009 0004

QRST_R0

RW

32

0x0000 0000

0x008

0x0009 0008

QDBG_R0

RW

32

0x0000 1000

0x00C

0x0009 000C

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0011 0000

GSSCLK_CTRL

RW

32

0x0000 0000

0x004

0x0011 0004

QRST_R0

RW

32

0x0000 0000

0x008

0x0011 0008

QDBG_R0

RW

32

0x0000 1000

0x00C

0x0011 000C

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0021 0000

GSSCLK_CTRL

RW

32

0x0000 0000

0x004

0x0021 0004

QRST_R0

RW

32

0x0000 0000

0x008

0x0021 0008

QDBG_R0

RW

32

0x0000 1000

0x00C

0x0021 000C

Address offset

0x000

Physical address

0x0005 0000

Instance

serdes_0_pcs_cmn

0x0009 0000

serdes_1_pcs_cmn

0x0011 0000

serdes_2_pcs_cmn

0x0021 0000

serdes_3_pcs_cmn

Description

Compulsory register for all SCB slaves, facilitating global soft reset.

Type

RW

31:16

BLOCKID

This returns the block type and chip location. The value of BLOCKID depends on the block type and instance of Serial block containing this page and upon the page (lane) instance number as follows: {4'h0, SLVTYPE, CHIPID, SUBID}. The SLVTPE value is 4'h0 for PCS. The CHIPID is determined by integration via constant applied to tieoff_chipid[3:0] . The SUBID is 4'h4 for the common page.

RO

0x0000

Read 0x0000

[block_address_PCSCMN] Indicates the Block chip location.

15:9

Reserved

RO
Rreturns0s

0x00

8

PERIPH

This asserts functional reset of the peripheral block. It is asserted and left asserted at power-up.

WO

0

Write 0

[scb_periph_not_in_soft_reset_PCSCMN] Reset not asserted.

Write 1

[scb_periph_reset_PCSCMN] SCB registers reset pulsed.

7:2

Reserved

RO
Rreturns0s

0x00

1

V_MAP

Resets all the volatile register bits.

WO

0

Write 0

[scb_v_regs_not_in_soft_reset_PCSCMN] Reset not asserted.

Write 1

[scb_v_regs_reset_PCSCMN] SCB Volatile reset (i.e. RW-X registers are reset)

0

NV_MAP

Resets all the non-volatile register bits (e.g. RW-P bits).

WO

0

Write 0

[scb_nv_regs_not_in_soft_reset_PCSCMN] Reset not asserted.

Write 1

[scb_nv_regs_reset_PCSCMN] SCB Non-Volatile reset (i.e. RW-P registers are reset.

Address offset

0x004

Physical address

0x0005 0004

Instance

serdes_0_pcs_cmn

0x0009 0004

serdes_1_pcs_cmn

0x0011 0004

serdes_2_pcs_cmn

0x0021 0004

serdes_3_pcs_cmn

Description

Selection of global clock outputs.

Type

RW

31:21

Reserved

RO
Rreturns0s

0x000

20:16

MCLK_GSSCLK_2_SEL

Selects source of global clock 2 output.

RW

0x00

0x00

[gssclk_2_is_constant_zero]

0x01

[gssclk_2_is_constant_one]

0x02

[gssclk_2_is_dualclk0]

0x03

[gssclk_2_is_dualclk1]

0x04

[gssclk_2_is_auxdivclk]

0x05

[gssclk_2_is_dll_clock]

0x06

[gssclk_2_is_cascade_in]

0x07

[gssclk_2_is_pma_tx_clk10_lane0]

0x08

[gssclk_2_is_pma_tx_clk20_lane0]

0x09

[gssclk_2_is_pma_tx_clk40_lane0]

0x0A

[gssclk_2_is_pma_rx_clk10_lane0]

0x0B

[gssclk_2_is_pma_rx_clk20_lane0]

0x0C

[gssclk_2_is_pma_rx_clk40_lane0]

0x0D

[gssclk_2_is_pma_tx_clk10_lane1]

0x0E

[gssclk_2_is_pma_tx_clk20_lane1]

0x0F

[gssclk_2_is_pma_tx_clk40_lane1]

0x10

[gssclk_2_is_pma_rx_clk10_lane1]

0x11

[gssclk_2_is_pma_rx_clk20_lane1]

0x12

[gssclk_2_is_pma_rx_clk40_lane1]

0x13

[gssclk_2_is_pma_tx_clk10_lane2]

0x14

[gssclk_2_is_pma_tx_clk20_lane2]

0x15

[gssclk_2_is_pma_tx_clk40_lane2]

0x16

[gssclk_2_is_pma_rx_clk10_lane2]

0x17

[gssclk_2_is_pma_rx_clk20_lane2]

0x18

[gssclk_2_is_pma_rx_clk40_lane2]

0x19

[gssclk_2_is_pma_tx_clk10_lane3]

0x1A

[gssclk_2_is_pma_tx_clk20_lane3]

0x1B

[gssclk_2_is_pma_tx_clk40_lane3]

0x1C

[gssclk_2_is_pma_rx_clk10_lane3]

0x1D

[gssclk_2_is_pma_rx_clk20_lane3]

0x1E

[gssclk_2_is_pma_rx_clk40_lane3]

15:13

Reserved

RO
Rreturns0s

0x0

12:8

MCLK_GSSCLK_1_SEL

Selects source of global clock 1 output.

RW

0x00

0x00

[gssclk_1_is_constant_zero]

0x01

[gssclk_1_is_constant_one]

0x02

[gssclk_1_is_dualclk0]

0x03

[gssclk_1_is_dualclk1]

0x04

[gssclk_1_is_auxdivclk]

0x05

[gssclk_1_is_dll_clock]

0x06

[gssclk_1_is_cascade_in]

0x07

[gssclk_1_is_pma_tx_clk10_lane0]

0x08

[gssclk_1_is_pma_tx_clk20_lane0]

0x09

[gssclk_1_is_pma_tx_clk40_lane0]

0x0A

[gssclk_1_is_pma_rx_clk10_lane0]

0x0B

[gssclk_1_is_pma_rx_clk20_lane0]

0x0C

[gssclk_1_is_pma_rx_clk40_lane0]

0x0D

[gssclk_1_is_pma_tx_clk10_lane1]

0x0E

[gssclk_1_is_pma_tx_clk20_lane1]

0x0F

[gssclk_1_is_pma_tx_clk40_lane1]

0x10

[gssclk_1_is_pma_rx_clk10_lane1]

0x11

[gssclk_1_is_pma_rx_clk20_lane1]

0x12

[gssclk_1_is_pma_rx_clk40_lane1]

0x13

[gssclk_1_is_pma_tx_clk10_lane2]

0x14

[gssclk_1_is_pma_tx_clk20_lane2]

0x15

[gssclk_1_is_pma_tx_clk40_lane2]

0x16

[gssclk_1_is_pma_rx_clk10_lane2]

0x17

[gssclk_1_is_pma_rx_clk20_lane2]

0x18

[gssclk_1_is_pma_rx_clk40_lane2]

0x19

[gssclk_1_is_pma_tx_clk10_lane3]

0x1A

[gssclk_1_is_pma_tx_clk20_lane3]

0x1B

[gssclk_1_is_pma_tx_clk40_lane3]

0x1C

[gssclk_1_is_pma_rx_clk10_lane3]

0x1D

[gssclk_1_is_pma_rx_clk20_lane3]

0x1E

[gssclk_1_is_pma_rx_clk40_lane3]

7:5

Reserved

RO
Rreturns0s

0x0

4:0

MCLK_GSSCLK_0_SEL

Selects source of global clock 0 output.

RW

0x00

0x00

[gssclk_0_is_constant_zero]

0x01

[gssclk_0_is_constant_one]

0x02

[gssclk_0_is_dualclk0]

0x03

[gssclk_0_is_dualclk1]

0x04

[gssclk_0_is_auxdivclk]

0x05

[gssclk_0_is_dll_clock]

0x06

[gssclk_0_is_cascade_in]

0x07

[gssclk_0_is_pma_tx_clk10_lane0]

0x08

[gssclk_0_is_pma_tx_clk20_lane0]

0x09

[gssclk_0_is_pma_tx_clk40_lane0]

0x0A

[gssclk_0_is_pma_rx_clk10_lane0]

0x0B

[gssclk_0_is_pma_rx_clk20_lane0]

0x0C

[gssclk_0_is_pma_rx_clk40_lane0]

0x0D

[gssclk_0_is_pma_tx_clk10_lane1]

0x0E

[gssclk_0_is_pma_tx_clk20_lane1]

0x0F

[gssclk_0_is_pma_tx_clk40_lane1]

0x10

[gssclk_0_is_pma_rx_clk10_lane1]

0x11

[gssclk_0_is_pma_rx_clk20_lane1]

0x12

[gssclk_0_is_pma_rx_clk40_lane1]

0x13

[gssclk_0_is_pma_tx_clk10_lane2]

0x14

[gssclk_0_is_pma_tx_clk20_lane2]

0x15

[gssclk_0_is_pma_tx_clk40_lane2]

0x16

[gssclk_0_is_pma_rx_clk10_lane2]

0x17

[gssclk_0_is_pma_rx_clk20_lane2]

0x18

[gssclk_0_is_pma_rx_clk40_lane2]

0x19

[gssclk_0_is_pma_tx_clk10_lane3]

0x1A

[gssclk_0_is_pma_tx_clk20_lane3]

0x1B

[gssclk_0_is_pma_tx_clk40_lane3]

0x1C

[gssclk_0_is_pma_rx_clk10_lane3]

0x1D

[gssclk_0_is_pma_rx_clk20_lane3]

0x1E

[gssclk_0_is_pma_rx_clk40_lane3]

Address offset

0x008

Physical address

0x0005 0008

Instance

serdes_0_pcs_cmn

0x0009 0008

serdes_1_pcs_cmn

0x0011 0008

serdes_2_pcs_cmn

0x0021 0008

serdes_3_pcs_cmn

Description

Define quad_reset_0_b and quad_reset_1_b outputs of G5_PCSPMA.

Type

RW

31:16

Reserved

RO
Rreturns0s

0x0000

15:12

QRST1_RST_SEL

Selects source within selected lane for quad_reset_1_b.

RW

0x0

0x0

[quad_reset_1_from_pipe_pma] PIPE pma-side reset domain.

0x1

[quad_reset_1_from_pipe] PIPE reset domain.

0x2

[quad_reset_1_from_pipe_rx] PIPE receiver reset domain.

0x3

[quad_reset_1_from_64b6xb_tx] 64b6xb transmitter reset domain.

0x4

[quad_reset_1_from_64b6xb_rx] 64b6xb receiver reset domain.

0x5

[quad_reset_1_from_8b10b_tx] 8b10b transmitter reset domain.

0x6

[quad_reset_1_from_8b10b_rx] 8b10b receiver reset domain.

0x7

[quad_reset_1_from_native_tx] native transmitter reset domain.

0x8

[quad_reset_1_from_native_rx] native receiver reset domain.

0x9

[quad_reset_1_from_tx_fwf] transmit Fly-Wheel FIFO reset domain.

0xA

[quad_reset_1_from_rx_fwf] receiver Fly-Wheel FIFO reset domain.

0xB

[quad_reset_1_off] logic one

11:10

Reserved

RO
Rreturns0s

0x0

9:8

QRST1_LANE

Selects lane driving quad_reset_1_b output of g5_pcspma.

RW

0x0

0x0

[quad_reset_1_from_lane_0] Source quad_reset_1_b from lane 0.

0x1

[quad_reset_1_from_lane_1] Source quad_reset_1_b from lane 1.

0x2

[quad_reset_1_from_lane_2] Source quad_reset_1_b from lane 2.

0x3

[quad_reset_1_from_lane_3] Source quad_reset_1_b from lane 3.

7:4

QRST0_RST_SEL

Selects source within selected lane for quad_reset_0_b.

RW

0x0

0x0

[quad_reset_0_from_pipe_pma] PIPE pma-side reset domain.

0x1

[quad_reset_0_from_pipe] PIPE reset domain.

0x2

[quad_reset_0_from_pipe_rx] PIPE receiver reset domain.

0x3

[quad_reset_0_from_64b6xb_tx] 64b6xb transmitter reset domain.

0x4

[quad_reset_0_from_64b6xb_rx] 64b6xb receiver reset domain.

0x5

[quad_reset_0_from_8b10b_tx] 8b10b transmitter reset domain.

0x6

[quad_reset_0_from_8b10b_rx] 8b10b receiver reset domain.

0x7

[quad_reset_0_from_native_tx] native transmitter reset domain.

0x8

[quad_reset_0_from_native_rx] native receiver reset domain.

0x9

[quad_reset_0_from_tx_fwf] transmit Fly-Wheel FIFO reset domain.

0xA

[quad_reset_0_from_rx_fwf] receiver Fly-Wheel FIFO reset domain.

0xB

[quad_reset_0_off] logic one

3:2

Reserved

RO
Rreturns0s

0x0

1:0

QRST0_LANE

Selects lane driving quad_reset_0_b output of g5_pcspma.

RW

0x0

0x0

[quad_reset_0_from_lane_0] Source quad_reset_0_b from lane 0.

0x1

[quad_reset_0_from_lane_1] Source quad_reset_0_b from lane 1.

0x2

[quad_reset_0_from_lane_2] Source quad_reset_0_b from lane 2.

0x3

[quad_reset_0_from_lane_3] Source quad_reset_0_b from lane 3.

Address offset

0x00C

Physical address

0x0005 000C

Instance

serdes_0_pcs_cmn

0x0009 000C

serdes_1_pcs_cmn

0x0011 000C

serdes_2_pcs_cmn

0x0021 000C

serdes_3_pcs_cmn

Description

Define fab_pcs_debug[19:0] output bus from G5_PCSPMA.

Type

RW

31:14

Reserved

RO
Rreturns0s

0x0 0000

13:12

PCS_DBG_LANE_Y

Selects identity of source lane, X, used in PCS_DBG_MODE.

RW

0x1

0x0

[lane_y_is_lane_0]

0x1

[lane_y_is_lane_1]

0x2

[lane_y_is_lane_2]

0x3

[lane_y_is_lane_3]

11:10

Reserved

RO
Rreturns0s

0x0

9:8

PCS_DBG_LANE_X

Selects identity of source lane, X, used in PCS_DBG_MODE.

RW

0x0

0x0

[lane_x_is_lane_0]

0x1

[lane_x_is_lane_1]

0x2

[lane_x_is_lane_2]

0x3

[lane_x_is_lane_3]

7:3

Reserved

RO
Rreturns0s

0x00

2:0

PCS_DBG_MODE

Selects PCS debug output mode. This sets up the output bus to hold either two lanes or four lanes of debug content. Also, selects which signal group is brought out per lane.

RW

0x0

0x0

[pcs_dbg_mode_0] The fab_pcs_debug[9:0] and fab_pcs_debug[19:10] fabric output port slices come from lane X and lane Y, respectively. They are both defined as the bits {pipe_comalgn_rxaligned, pipe_comalgn_sawcomma, pma_rxdetect_done, pma_pddone, pma_rxelecidle, pma_txelecidle, pipelogic_state[3:0]}.
Lanes X and Y are defined by QDBG_R0/PCS_DBG_LANE_X[1:0] and QDBG_R0/PCS_DBG_LANE_Y[1:0].

0x1

[pcs_dbg_mode_1] The fab_pcs_debug[9:0] and fab_pcs_debug[19:10] fabric output port slices come from lane X and lane Y, respectively. They are both defined as the bits {pipe_comalgn_rxaligned, pipe_comalgn_sawcomma, pma_tx_oob_idle, pma_tx_oob_burst, comwake_detect, comreset/init_detect, pipe_elasbuf_ptrdiff[3:0]}.
Lanes X and Y are defined by QDBG_R0/PCS_DBG_LANE_X[1:0] and QDBG_R0/PCS_DBG_LANE_Y[1:0].

0x2

[pcs_dbg_mode_2] The fab_pcs_debug[9:0] and fab_pcs_debug[19:10] fabric output port slices come from lane X and lane Y, respectively. They are both defined as the bits {TxDetectRx/Loopback, PowerDown[1:0], RxElecIdle, TxElecIdle, PhyStatus, pipelogic_state[3:0]}. Lanes X and Y are defined by QDBG_R0/PCS_DBG_LANE_X[1:0] and QDBG_R0/PCS_DBG_LANE_Y[1:0].

0x3

[pcs_dbg_mode_3] The fab_pcs_debug[4:0], fab_pcs_debug[9:5], fab_pcs_debug[14:10] and fab_pcs_debug[19:15] fabric output port slices come from lanes 0-3, respectively. These output slices are defined as the bits {PhyStatus, pipelogic_state[3:0]}.

0x4

[pcs_dbg_mode_4] The fab_pcs_debug[4:0], fab_pcs_debug[9:5], fab_pcs_debug[14:10] and fab_pcs_debug[19:15] fabric output port slices come from lanes 0-3, respectively. These output slices are defined as the bits {Rate[0], PowerDown[1:0], RxElecIdle, TxElecIdle}.

0x5

[pcs_dbg_mode_5] The fab_pcs_debug output bus is driven with all-zeroes.