Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0100

0x000

0x0701 0000

DLL_CTRL0

RW

32

0x8800 000F

0x004

0x0701 0004

DLL_CTRL1

RW

32

0x0000 0000

0x008

0x0701 0008

DLL_STAT0

RW

32

0x0000 1801

0x00C

0x0701 000C

DLL_STAT1

RO

32

0x0000 0000

0x010

0x0701 0010

DLL_STAT2

RO

32

0x0000 0000

0x014

0x0701 0014

DLL_TEST

RW

32

0x0000 0000

0x018

0x0701 0018

CONTROL_USER

RW

32

0x0000 0006

0x040

0x0701 0040

CONTROL_PFC

RW

32

0x0000 0000

0x044

0x0701 0044

STATUS

RO

32

0x0000 0000

0x048

0x0701 0048

INTERRUPT_ENABLE

RW

32

0x0000 0000

0x04C

0x0701 004C

MARGIN

RW

32

0x0000 0000

0x060

0x0701 0060

Address offset

0x000

Physical address

0x0701 0000

Instance

PF_US_CRYPTO_TOP

Description

System Reset Register.

Type

RW

31:16

BLOCKID

This returns the block type and chip location.

RO

0x0000

Read 0x0000

[block_address_PF_US_CRYPTO_TOP] Indicates the Block chip location.

15:9

Reserved

RO
Rreturns0s

0x00

8

PERIPH

This asserts the functional reset of the block. It is asserted at power up. When written is stays asserted until written to 0.

WO

1

Write 0

[scb_periph_not_in_soft_reset_PF_US_CRYPTO_TOP] Resets not asserted

Write 1

[scb_periph_reset_PF_US_CRYPTO_TOP] SCB registers reset pulsed

7:2

Reserved

RO
Rreturns0s

0x00

1

V_MAP

This when asserted resets all the register bits apart from the non-volatile registers, the bit self clears i.e. is similar to a W1P bit

WO

0

Write 0

[scb_v_regs_not_in_soft_reset_PF_US_CRYPTO_TOP] Resets not asserted

Write 1

[scb_v_regs_reset_PF_US_CRYPTO_TOP] SCB Volitile reset i.e RW-P registers are reset

0

NV_MAP

This when asserted resets all the non-volatile register bits e.g. RW-P bits, the bit self clears i.e. is similar to a W1P bit

WO

0

Write 0

[scb_nv_regs_not_in_soft_reset_PF_US_CRYPTO_TOP] Resets not asserted

Write 1

[scb_nv_regs_reset_PF_US_CRYPTO_TOP] SCB Non-Volitile reset i.e RW-X registers are reset

Address offset

0x004

Physical address

0x0701 0004

Instance

PF_US_CRYPTO_TOP

Description

DLL control register 0

Type

RW

31:28

lock_low

RW

0x8

27:24

lock_high

RW

0x8

23:22

Reserved

RO

0x0

21:20

lock_flt

RW

0x0

19

lock_frc

RW

0

18:16

Reserved

RO

0x0

15:14

alu_upd

RW

0x0

13:11

Reserved

RO

0x0

10

div_sel

RW

0

9

fb_sel

RW

0

8

ref_sel

RW

0

7:6

sel_s

RW

0x0

5:4

sel_p

RW

0x0

3:2

phase_s

RW

0x3

1:0

phase_p

All thes eregisters follow the standard allocation for DLL blocks used in G5. Please refer to the DLL SAC specification for details of register functions.

RW

0x3

Address offset

0x008

Physical address

0x0701 0008

Instance

PF_US_CRYPTO_TOP

Description

DLL control register 1

Type

RW

31

Reserved

RO

0

30

relock_fast

RW

0

29:24

init_code

RW

0x00

23

test_ring

RW

0

22:16

Reserved

RO

0x00

15

test_s

RW

0

14:8

adj_del4

RW

0x00

7:0

set_alu

RW

0x00

Address offset

0x00C

Physical address

0x0701 000C

Instance

PF_US_CRYPTO_TOP

Description

DLL status register 0

Type

RW

31:24

Reserved

RO

0x00

23:16

Reserved

RO

0x00

15:14

Reserved

RO

0x0

13

Reserved

RO

0

12

phase_move_clk

RW

1

11

unlock_int

RW
W1toClr

1

10

lock_int

RW
W1toClr

0

9

unlock_int_en

RW

0

8

lock_int_en

RW

0

7:5

Reserved

RO

0x0

4

Reserved

RO

0

3

Reserved

RO

0

2

Reserved

RO

0

1

Reserved

RO

0

0

reset

RW

1

Address offset

0x010

Physical address

0x0701 0010

Instance

PF_US_CRYPTO_TOP

Description

DLL status register 1

Type

RO

31:30

Reserved

RO

0x0

29:28

Reserved

RO

0x0

27:26

Reserved

RO

0x0

25

Reserved

RO

0

24:16

sro_alu_cnt

RO

0x000

15:8

Reserved

RO

0x00

7

Reserved

RO

0

6:0

sro_del4

RO

0x00

Address offset

0x014

Physical address

0x0701 0014

Instance

PF_US_CRYPTO_TOP

Description

DLL status register 2

Type

RO

31:24

Reserved

RO

0x00

23:16

Reserved

RO

0x00

15:7

Reserved

RO

0x000

6

Reserved

RO

0

5

Reserved

RO

0

4

Reserved

RO

0

3

Reserved

RO

0

2

sro_lock

RO

0

1

Reserved

RO

0

0

Reserved

RO

0

Address offset

0x018

Physical address

0x0701 0018

Instance

PF_US_CRYPTO_TOP

Description

Enables test modes on the DLL

Type

RW

31:4

Reserved

RO
Rreturns0s

0x000 0000

3

reserved

To aid synthesis - reads as zero

RO

0

2

ref_select

When '1' the sb clock input is fed to the DLL reference

RW

0

1

cfm_select

Feeds the MBIST clock rather than DLL clock to the CFM block

RW

0

0

cfm_enable

When set enables the DLL output to the frequency meter inside the PF-Controller for test use

RW

0

Address offset

0x040

Physical address

0x0701 0040

Instance

PF_US_CRYPTO_TOP

Description

User Accessible Register for controlling Athena core via SCB bus

Type

RW

31:10

Reserved

RO
Rreturns0s

0x00 0000

9

go

When '1' sets the Athena GO input

RW

0

8

purge

When '1' sets the Athena PURGE input

RW

0

7

ring_osc_on

Enables the internal Athena ring oscillators. When '0' the oscillators are stopped lowering power consumption. Must be '1' for the Athena core to operate

RW

0

6

dll_on

Enables the DLL. When '0' the DLL internal activity is stopped lowering power consumption.

RW

0

5

rams_on

Enable the internal RAMS. When '0' the RAMS are powered down lowering power consumption.

RW

0

4:3

clock_select

Selects the Athena clcok source
00: No clock selected
01:Fabric clock with DLL enabled
10: SCB clock
11: Chip 160MHz Oscillator

RW

0x0

2

clock_enable

When '1' the clock to the Athena core is enabled.

RW

1

1

reset

When '1' hold the Athena core in reset

RW

1

0

scb_control

When '1' this register directly controls the Athena GO and PURGE bits.
When '0' the Athena Go and PURGE pins are under fabric control.
Note the Sysyem Controller can override this register

RW

0

Address offset

0x044

Physical address

0x0701 0044

Instance

PF_US_CRYPTO_TOP

Description

Registers only accesible to PF-Control for it to override the the user and gain control of the Athena core.
PFC control does not have access to the internals of the Athena core, but can initiate purge cycles.

Type

RW

31:14

Reserved

RO
Rreturns0s

0x0 0000

13

dllevent

Enable SCB interrupt on a DLL event

RW

0

12

buserror

Enables SCB interrupt on bus error

RW

0

11

alarm

Enable SCB interrupt on alarm

RW

0

10

complete

Enable SCB interrupt on complete

RW

0

9

go

RW

0

8

purge

RW

0

7

ring_osc_on

RW

0

6

dll_on

RW

0

5

rams_on

RW

0

4:3

clock_select

RW

0x0

2

clock_enable

RW

0

1

reset

RW

0

0

override

When override is set inthis register conrols all the Athena non AHB inputs as well as clock selection and various power downs.

RW

0

Address offset

0x048

Physical address

0x0701 0048

Instance

PF_US_CRYPTO_TOP

Description

Athena Status

Type

RO

31:4

Reserved

RO
Rreturns0s

0x000 0000

3

busy

Read off Athena BUSY output

RO

0

2

buserror

Set when a HRESP response is detected by the Athena AHB master.
Once set a reset is required to clear.

RO

0

1

alarm

Read off Athena ALARM output

RO

0

0

complete

Read off Athena COMPLETE output

RO

0

Address offset

0x04C

Physical address

0x0701 004C

Instance

PF_US_CRYPTO_TOP

Description

Enables Interrupt events to Fabric

Type

RW

31:3

Reserved

RO
Rreturns0s

0x0000 0000

2

buserror

Enables interrupt to fabric

RW

0

1

alarm

Enables interrupt to fabric

RW

0

0

complete

Enables interrtpt to fabric

RW

0

Address offset

0x060

Physical address

0x0701 0060

Instance

PF_US_CRYPTO_TOP

Description

Allows RAM access speed to be tuned for different operating voltages.

Type

RW

31:6

Reserved

RO
Rreturns0s

0x000 0000

5:3

rom

RW

0x0

2:0

ram

Provided direct control of RAM/ROM margining inputs. Should be set to 3'b000 for normal opearting conditions. Should not be documented for customer and should be forced non-dynamic by Libero

RW

0x0