PFSOC_CONTROL_SCB

This section provides information on the PFSOC_CONTROL_SCB Module Instance. Each of the module registers is described below.

Register Lock Bits can prevent the XCVR configuration registers from being overwritten by hosts that have access to these registers. The lock bits can be managed using the Configure Register Lock Bits utility in the Libero SoC. The following registers can be locked.

·         PFSOC_CONTROL_SCB_SOFT_RESET 
·         PFSOC_CONTROL_SCB_TVS_CONTROL 
·         PFSOC_CONTROL_SCB_TVS_TRIGGER 
·         PFSOC_CONTROL_SCB_VDETECTOR

 

Return to mpfs_ioscb_memmap_dri

PFSOC_CONTROL_SCB Register Mapping Summary

PFSOC_CONTROL_SCB Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0710 0100

0x00

0x0702 0000

VDETECTOR

RW

32

0x0000 0007

0x04

0x0702 0004

TVS_CONTROL

RW

32

0x0000 0000

0x08

0x0702 0008

TVS_TEMP_A

RW

32

0x0000 0000

0x0C

0x0702 000C

TVS_TEMP_B

RW

32

0x0000 0000

0x10

0x0702 0010

TVS_TEMP_C

RW

32

0x0000 0000

0x14

0x0702 0014

TVS_VOLT_A

RO

32

0x0000 0000

0x18

0x0702 0018

TVS_VOLT_B

RW

32

0x0000 0000

0x1C

0x0702 001C

TVS_VOLT_C

RW

32

0x0000 0000

0x20

0x0702 0020

TVS_OUTPUT0

RO

32

0x0000 0000

0x24

0x0702 0024

TVS_OUTPUT1

RO

32

0x0000 0000

0x28

0x0702 0028

TVS_TRIGGER

RW

32

0x0000 0000

0x2C

0x0702 002C

TRIM_VDET1P05

RW

32

0x0000 4040

0x30

0x0702 0030

TRIM_VDET1P8

RW

32

0x0000 0D10

0x34

0x0702 0034

TRIM_VDET2P5

RW

32

0x0000 1010

0x38

0x0702 0038

TRIM_TVS

RW

32

0x0000 0010

0x3C

0x0702 003C

TRIM_GDET1P05

RW

32

0x0000 0000

0x40

0x0702 0040

SERVICES_CR

RW

32

0x0000 0000

0x50

0x0702 0050

SERVICES_SR

RO

32

0x0000 0000

0x54

0x0702 0054

USER_DETECTOR_SR

RW

32

0x0000 0000

0x58

0x0702 0058

USER_DETECTOR_CR

RW

32

0x0000 0000

0x5C

0x0702 005C

MSS_SPI_CR

RW

32

0x0000 0000

0x60

0x0702 0060

 

PFSOC_CONTROL_SCB Register Descriptions

PFSOC_CONTROL_SCB : SOFT_RESET

Address offset

0x00

Physical address

0x0702 0000

Instance

PFSOC_CONTROL_SCB

Description

System Reset Register.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

BLOCKID

This returns the block type and chip location.
(IO SCB bus only)

RO

0x0710

 

 

Read 0x0000

[block_address_PFSOC_CONTROL_SCB] Indicates the Block chip location.

 

15:9

Reserved

 

RO
Rreturns0s

0x00

8

PERIPH

This asserts the functional reset of the block. It is asserted and left asserted at power up.

WO

1

 

 

Write 0

[scb_periph_not_in_soft_reset_PFSOC_CONTROL_SCB] Resets not asserted

 

 

 

Write 1

[scb_periph_reset_PFSOC_CONTROL_SCB] SCB registers reset pulsed

 

7:2

Reserved

 

RO
Rreturns0s

0x00

1

V_MAP

This when asserted resets all the register bits apart from the non-volatile registers

WO

0

 

 

Write 0

[scb_v_regs_not_in_soft_reset_PFSOC_CONTROL_SCB] Resets not asserted

 

 

 

Write 1

[scb_v_regs_reset_PFSOC_CONTROL_SCB] SCB Volitile reset i.e RW-P registers are reset

 

0

NV_MAP

This when asserted resets all the non-volatile register bits e.g. RW-P bits

WO

0

 

 

Write 0

[scb_nv_regs_not_in_soft_reset_PFSOC_CONTROL_SCB] Resets not asserted

 

 

 

Write 1

[scb_nv_regs_reset_PFSOC_CONTROL_SCB] SCB Non-Volitile reset i.e RW-X registers are reset

 

 

PFSOC_CONTROL_SCB : VDETECTOR

Address offset

0x04

Physical address

0x0702 0004

Instance

PFSOC_CONTROL_SCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2

enable_2p5

 

RW

1

1

enable_1p8

 

RW

1

0

enable_1p05

 

RW

1

 

PFSOC_CONTROL_SCB : TVS_CONTROL

Address offset

0x08

Physical address

0x0702 0008

Instance

PFSOC_CONTROL_SCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:22

Reserved

 

RO
Rreturns0s

0x000

21

over_temp

Indicates temperature is below the set value

RO

0

20

under_temp

Indicates temperature is over the set value

RO

0

19:16

valid

Indicates Channel value is valid, once set will stay set until channel is disabled.

RO

0x0

15:8

rate

Time to wait once all enabled channels converted
time=value*32us
255= Do single set of transfers when scoverride set

RW

0x00

7

Reserved

 

RO
Rreturns0s

0

6

running

FSM is doing a conversion

RO

0

5

poweroff

Between conversions power the TVS down, adds 50us to the overall conversion rate

RW

0

4

abort

Abort operation, and restart if enables are nonzero

RW
W1P

0

3:0

enable

Enables each of the channels.
0=1p05, 1=1p8, 2=2p5, 3=Temp

RW

0x0

 

PFSOC_CONTROL_SCB : TVS_TEMP_A

Address offset

0x0C

Physical address

0x0702 000C

Instance

PFSOC_CONTROL_SCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

sign

Sets the y=ax2+bx+c Temperature correction

RW

0

30:20

integ

Sets the y=ax2+bx+c Temperature correction

RW

0x000

19:0

fract

Sets the y=ax2+bx+c Temperature correction

RW

0x0 0000

 

PFSOC_CONTROL_SCB : TVS_TEMP_B

Address offset

0x10

Physical address

0x0702 0010

Instance

PFSOC_CONTROL_SCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

sign

Sets the y=ax2+bx+c Temperature correction

RW

0

30:20

integ

Sets the y=ax2+bx+c Temperature correction

RW

0x000

19:0

fract

Sets the y=ax2+bx+c Temperature correction

RW

0x0 0000

 

PFSOC_CONTROL_SCB : TVS_TEMP_C

Address offset

0x14

Physical address

0x0702 0014

Instance

PFSOC_CONTROL_SCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

sign

Sets the y=ax2+bx+c Temperature correction, only applies to 1.05 conversion

RW

0

30:20

integ

Sets the y=ax2+bx+c Temperature correction, only applies to 1.05 conversion

RW

0x000

19:15

fract

Sets the y=ax2+bx+c Temperature correction, only applies to 1.05 conversion

RW

0x00

14:0

Reserved

Sets the y=ax2+bx+c Temperature correction, only applies to 1.05 conversion

RO

0x0000

 

PFSOC_CONTROL_SCB : TVS_VOLT_A

Address offset

0x18

Physical address

0x0702 0018

Instance

PFSOC_CONTROL_SCB

Description

Type

RO

 

Bits

Field Name

Description

Type

Reset

31

sign

Sets the y=ax2+bx+c Voltage correction

RO

0

30:20

integ

Sets the y=ax2+bx+c Voltage correction

RO

0x000

19:0

fract

Sets the y=ax2+bx+c Voltage correction

RO

0x0 0000

 

PFSOC_CONTROL_SCB : TVS_VOLT_B

Address offset

0x1C

Physical address

0x0702 001C

Instance

PFSOC_CONTROL_SCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

sign

Sets the y=ax2+bx+c Voltage correction

RW

0

30:20

integ

Sets the y=ax2+bx+c Voltage correction

RW

0x000

19:0

fract

Sets the y=ax2+bx+c Voltage correction

RW

0x0 0000

 

PFSOC_CONTROL_SCB : TVS_VOLT_C

Address offset

0x20

Physical address

0x0702 0020

Instance

PFSOC_CONTROL_SCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

sign

Sets the y=ax2+bx+c Voltage correction

RW

0

30:20

integ

Sets the y=ax2+bx+c Voltage correction

RW

0x000

19:15

fract

Sets the y=ax2+bx+c Voltage correction

RW

0x00

14:0

Reserved

Sets the y=ax2+bx+c Voltage correction

RO

0x0000

 

PFSOC_CONTROL_SCB : TVS_OUTPUT0

Address offset

0x24

Physical address

0x0702 0024

Instance

PFSOC_CONTROL_SCB

Description

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:16

volt1p8

 

RO

0x0000

15:0

volt1p05

 

RO

0x0000

 

PFSOC_CONTROL_SCB : TVS_OUTPUT1

Address offset

0x28

Physical address

0x0702 0028

Instance

PFSOC_CONTROL_SCB

Description

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:16

temp

 

RO

0x0000

15:0

volt2p5

 

RO

0x0000

 

PFSOC_CONTROL_SCB : TVS_TRIGGER

Address offset

0x2C

Physical address

0x0702 002C

Instance

PFSOC_CONTROL_SCB

Description

temperature trigger levels

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

HIGH

 

RW

0x0000

15:0

LOW

 

RW

0x0000

 

PFSOC_CONTROL_SCB : TRIM_VDET1P05

Address offset

0x30

Physical address

0x0702 0030

Instance

PFSOC_CONTROL_SCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:15

Reserved

 

RO
Rreturns0s

0x0 0000

14:8

progl

 

RW

0x40

7

Reserved

 

RO
Rreturns0s

0

6:0

progh

 

RW

0x40

 

PFSOC_CONTROL_SCB : TRIM_VDET1P8

Address offset

0x34

Physical address

0x0702 0034

Instance

PFSOC_CONTROL_SCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:13

Reserved

 

RO
Rreturns0s

0x0 0000

12:8

progl

 

RW

0x0D

7:5

Reserved

 

RO
Rreturns0s

0x0

4:0

progh

 

RW

0x10

 

PFSOC_CONTROL_SCB : TRIM_VDET2P5

Address offset

0x38

Physical address

0x0702 0038

Instance

PFSOC_CONTROL_SCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:13

Reserved

 

RO
Rreturns0s

0x0 0000

12:8

progl

 

RW

0x10

7:5

Reserved

 

RO
Rreturns0s

0x0

4:0

progh

 

RW

0x10

 

PFSOC_CONTROL_SCB : TRIM_TVS

Address offset

0x3C

Physical address

0x0702 003C

Instance

PFSOC_CONTROL_SCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:5

Reserved

 

RO
Rreturns0s

0x000 0000

4

deltavbe

 

RW

1

3:0

caltrim

 

RW

0x0

 

PFSOC_CONTROL_SCB : TRIM_GDET1P05

Address offset

0x40

Physical address

0x0702 0040

Instance

PFSOC_CONTROL_SCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:10

Reserved

 

RO
Rreturns0s

0x00 0000

9:8

rate

 

RW

0x0

7:6

width

 

RW

0x0

5:4

threshold

 

RW

0x0

3:2

negtrim

 

RW

0x0

1:0

postrim

 

RW

0x0

 

PFSOC_CONTROL_SCB : SERVICES_CR

Address offset

0x50

Physical address

0x0702 0050

Instance

PFSOC_CONTROL_SCB

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

command

The 16-bit command value

RW

0x0000

15:4

Reserved

 

RO
Rreturns0s

0x000

3

notify

Tells G5C to notify the MSS via a MSS interrupt when complete

RW

0

2

abort

When written to '1' requests a system service is aborted.

RW

0

1

busy

Is set whist a the system service is being processed

RO

0

0

request

When written to '1' requests a system servide as specified in the command field. Will stay set until G5C starts processing the command

RW

0

 

PFSOC_CONTROL_SCB : SERVICES_SR

Address offset

0x54

Physical address

0x0702 0054

Instance

PFSOC_CONTROL_SCB

Description

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:16

status

returned services status, is valid when BUSY=0;

RO

0x0000

15:4

Reserved

 

RO
Rreturns0s

0x000

3

notify

read of services control register

RO

0

2

abort

read of services control register

RO

0

1

busy

read of services control register

RO

0

0

request

read of services control register

RO

0

 

PFSOC_CONTROL_SCB : USER_DETECTOR_SR

Address offset

0x58

Physical address

0x0702 0058

Instance

PFSOC_CONTROL_SCB

Description

Indicates that an alarm condition has happened. Register is intended for MSS use. Is cleared by writing a '1'

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:10

Reserved

 

RO
Rreturns0s

0x00 0000

9

temp_low_fall

Latched value from TVS block, writing 1 clears

RW
W1toClr

0

8

temp_low_rise

Latched value from TVS block, writing 1 clears

RW
W1toClr

0

7

temp_high_fall

Latched value from TVS block, writing 1 clears

RW
W1toClr

0

6

temp_high_rise

Latched value from TVS block, writing 1 clears

RW
W1toClr

0

5

high_p5

Latched value from user detector, writing 1 clears

RW
W1toClr

0

4

low_p5

Latched value from user detector, writing 1 clears

RW
W1toClr

0

3

high_p8

Latched value from user detector, writing 1 clears

RW
W1toClr

0

2

low_p8

Latched value from user detector, writing 1 clears

RW
W1toClr

0

1

high_p05

Latched value from user detector, writing 1 clears

RW
W1toClr

0

0

low_p05

Latched value from user detector, writing 1 clears

RW
W1toClr

0

 

PFSOC_CONTROL_SCB : USER_DETECTOR_CR

Address offset

0x5C

Physical address

0x0702 005C

Instance

PFSOC_CONTROL_SCB

Description

Enables the detector to set the MSS alarm signal routed from G5C to the MSS.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:10

Reserved

 

RO
Rreturns0s

0x00 0000

9

temp_low_fall

Enables the generation of the MSS user alarm on this event

RW

0

8

temp_low_rise

Enables the generation of the MSS user alarm on this event

RW

0

7

temp_high_fall

Enables the generation of the MSS user alarm on this event

RW

0

6

temp_high_rise

Enables the generation of the MSS user alarm on this event

RW

0

5

high_p5

Enables the generation of the MSS user alarm on this event

RW

0

4

low_p5

Enables the generation of the MSS user alarm on this event

RW

0

3

high_p8

Enables the generation of the MSS user alarm on this event

RW

0

2

low_p8

Enables the generation of the MSS user alarm on this event

RW

0

1

high_p05

Enables the generation of the MSS user alarm on this event

RW

0

0

low_p05

Enables the generation of the MSS user alarm on this event

RW

0

 

PFSOC_CONTROL_SCB : MSS_SPI_CR

Address offset

0x60

Physical address

0x0702 0060

Instance

PFSOC_CONTROL_SCB

Description

Reset Controls for the MSS SPI Core

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1

mask_auto_reset

When asserted prevents the MSS reset request from resetting the MSS SCB SPI Core

RW

0

0

reset

When asserted holds the MSS SCB SPI Core in reset.

RW

0

 

PFSOC_CONTROL_SCB has no common memories.