PMA_CMN

This section provides information on the PMA_CMN Module Instance. Each of the module registers is described below.

Register Lock Bits can prevent the XCVR configuration registers from being overwritten by hosts that have access to these registers. The lock bits can be managed using the Configure Register Lock Bits utility in the Libero SoC. The following registers can be locked.

·         PMA_CMN_SOFT_RESET

·         PMA_CMN_TXPLL_CLK_SEL

·         PMA_CMN_TXPLL_CLKBUF

·         PMA_CMN_TXPLL_CTRL

·         PMA_CMN_TXPLL_DIV_1

·         PMA_CMN_TXPLL_DIV_2

 

Return to mpfs_ioscb_memmap_dri

PMA_CMN Register Mapping Summary

PMA_CMN Common Register Mapping Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

SOFT_RESET

RW

32

0x0000 0000

0x000

TXPLL_CLKBUF

RW

32

0x0000 0000

0x004

TXPLL_CTRL

RW

32

0x00E6 0010

0x008

TXPLL_CLK_SEL

RW

32

0x3F3F 1C00

0x00C

TXPLL_DIV_1

RW

32

0x0019 0019

0x010

TXPLL_DIV_2

RW

32

0x0100 0001

0x014

TXPLL_JA_1

RW

32

0x0064 0064

0x018

TXPLL_JA_2

RW

32

0x0000 0064

0x01C

TXPLL_JA_3

RW

32

0x0064 0064

0x020

TXPLL_JA_4

RW

32

0x0101 0001

0x024

TXPLL_JA_5

RW

32

0x0101 0101

0x028

TXPLL_JA_6

RW

32

0x0101 0101

0x02C

TXPLL_JA_7

RW

32

0x0700 0001

0x030

TXPLL_JA_8

RW

32

0x0000 0000

0x034

TXPLL_JA_9

RW

32

0x0018 0014

0x038

TXPLL_JA_10

RO

32

0x0000 0000

0x03C

TXPLL_JA_RST

RW

32

0x0000 0055

0x040

SERDES_SSMOD

RW

32

0x007F 0102

0x044

SERDES_RTERM

RW

32

0x000D 0703

0x050

SERDES_RTT

RW

32

0x0000 0000

0x054

PMA_CMN Instances Mapping Summary

PMA_CMN : serdes_0_PMA_CMN Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0105 0000

TXPLL_CLKBUF

RW

32

0x0000 0000

0x004

0x0105 0004

TXPLL_CTRL

RW

32

0x00E6 0010

0x008

0x0105 0008

TXPLL_CLK_SEL

RW

32

0x3F3F 1C00

0x00C

0x0105 000C

TXPLL_DIV_1

RW

32

0x0019 0019

0x010

0x0105 0010

TXPLL_DIV_2

RW

32

0x0100 0001

0x014

0x0105 0014

TXPLL_JA_1

RW

32

0x0064 0064

0x018

0x0105 0018

TXPLL_JA_2

RW

32

0x0000 0064

0x01C

0x0105 001C

TXPLL_JA_3

RW

32

0x0064 0064

0x020

0x0105 0020

TXPLL_JA_4

RW

32

0x0101 0001

0x024

0x0105 0024

TXPLL_JA_5

RW

32

0x0101 0101

0x028

0x0105 0028

TXPLL_JA_6

RW

32

0x0101 0101

0x02C

0x0105 002C

TXPLL_JA_7

RW

32

0x0700 0001

0x030

0x0105 0030

TXPLL_JA_8

RW

32

0x0000 0000

0x034

0x0105 0034

TXPLL_JA_9

RW

32

0x0018 0014

0x038

0x0105 0038

TXPLL_JA_10

RO

32

0x0000 0000

0x03C

0x0105 003C

TXPLL_JA_RST

RW

32

0x0000 0055

0x040

0x0105 0040

SERDES_SSMOD

RW

32

0x007F 0102

0x044

0x0105 0044

SERDES_RTERM

RW

32

0x000D 0703

0x050

0x0105 0050

SERDES_RTT

RW

32

0x0000 0000

0x054

0x0105 0054

 

PMA_CMN : serdes_1_PMA_CMN Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0109 0000

TXPLL_CLKBUF

RW

32

0x0000 0000

0x004

0x0109 0004

TXPLL_CTRL

RW

32

0x00E6 0010

0x008

0x0109 0008

TXPLL_CLK_SEL

RW

32

0x3F3F 1C00

0x00C

0x0109 000C

TXPLL_DIV_1

RW

32

0x0019 0019

0x010

0x0109 0010

TXPLL_DIV_2

RW

32

0x0100 0001

0x014

0x0109 0014

TXPLL_JA_1

RW

32

0x0064 0064

0x018

0x0109 0018

TXPLL_JA_2

RW

32

0x0000 0064

0x01C

0x0109 001C

TXPLL_JA_3

RW

32

0x0064 0064

0x020

0x0109 0020

TXPLL_JA_4

RW

32

0x0101 0001

0x024

0x0109 0024

TXPLL_JA_5

RW

32

0x0101 0101

0x028

0x0109 0028

TXPLL_JA_6

RW

32

0x0101 0101

0x02C

0x0109 002C

TXPLL_JA_7

RW

32

0x0700 0001

0x030

0x0109 0030

TXPLL_JA_8

RW

32

0x0000 0000

0x034

0x0109 0034

TXPLL_JA_9

RW

32

0x0018 0014

0x038

0x0109 0038

TXPLL_JA_10

RO

32

0x0000 0000

0x03C

0x0109 003C

TXPLL_JA_RST

RW

32

0x0000 0055

0x040

0x0109 0040

SERDES_SSMOD

RW

32

0x007F 0102

0x044

0x0109 0044

SERDES_RTERM

RW

32

0x000D 0703

0x050

0x0109 0050

SERDES_RTT

RW

32

0x0000 0000

0x054

0x0109 0054

 

PMA_CMN : serdes_2_PMA_CMN Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0111 0000

TXPLL_CLKBUF

RW

32

0x0000 0000

0x004

0x0111 0004

TXPLL_CTRL

RW

32

0x00E6 0010

0x008

0x0111 0008

TXPLL_CLK_SEL

RW

32

0x3F3F 1C00

0x00C

0x0111 000C

TXPLL_DIV_1

RW

32

0x0019 0019

0x010

0x0111 0010

TXPLL_DIV_2

RW

32

0x0100 0001

0x014

0x0111 0014

TXPLL_JA_1

RW

32

0x0064 0064

0x018

0x0111 0018

TXPLL_JA_2

RW

32

0x0000 0064

0x01C

0x0111 001C

TXPLL_JA_3

RW

32

0x0064 0064

0x020

0x0111 0020

TXPLL_JA_4

RW

32

0x0101 0001

0x024

0x0111 0024

TXPLL_JA_5

RW

32

0x0101 0101

0x028

0x0111 0028

TXPLL_JA_6

RW

32

0x0101 0101

0x02C

0x0111 002C

TXPLL_JA_7

RW

32

0x0700 0001

0x030

0x0111 0030

TXPLL_JA_8

RW

32

0x0000 0000

0x034

0x0111 0034

TXPLL_JA_9

RW

32

0x0018 0014

0x038

0x0111 0038

TXPLL_JA_10

RO

32

0x0000 0000

0x03C

0x0111 003C

TXPLL_JA_RST

RW

32

0x0000 0055

0x040

0x0111 0040

SERDES_SSMOD

RW

32

0x007F 0102

0x044

0x0111 0044

SERDES_RTERM

RW

32

0x000D 0703

0x050

0x0111 0050

SERDES_RTT

RW

32

0x0000 0000

0x054

0x0111 0054

 

PMA_CMN : serdes_3_PMA_CMN Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET

RW

32

0x0000 0000

0x000

0x0121 0000

TXPLL_CLKBUF

RW

32

0x0000 0000

0x004

0x0121 0004

TXPLL_CTRL

RW

32

0x00E6 0010

0x008

0x0121 0008

TXPLL_CLK_SEL

RW

32

0x3F3F 1C00

0x00C

0x0121 000C

TXPLL_DIV_1

RW

32

0x0019 0019

0x010

0x0121 0010

TXPLL_DIV_2

RW

32

0x0100 0001

0x014

0x0121 0014

TXPLL_JA_1

RW

32

0x0064 0064

0x018

0x0121 0018

TXPLL_JA_2

RW

32

0x0000 0064

0x01C

0x0121 001C

TXPLL_JA_3

RW

32

0x0064 0064

0x020

0x0121 0020

TXPLL_JA_4

RW

32

0x0101 0001

0x024

0x0121 0024

TXPLL_JA_5

RW

32

0x0101 0101

0x028

0x0121 0028

TXPLL_JA_6

RW

32

0x0101 0101

0x02C

0x0121 002C

TXPLL_JA_7

RW

32

0x0700 0001

0x030

0x0121 0030

TXPLL_JA_8

RW

32

0x0000 0000

0x034

0x0121 0034

TXPLL_JA_9

RW

32

0x0018 0014

0x038

0x0121 0038

TXPLL_JA_10

RO

32

0x0000 0000

0x03C

0x0121 003C

TXPLL_JA_RST

RW

32

0x0000 0055

0x040

0x0121 0040

SERDES_SSMOD

RW

32

0x007F 0102

0x044

0x0121 0044

SERDES_RTERM

RW

32

0x000D 0703

0x050

0x0121 0050

SERDES_RTT

RW

32

0x0000 0000

0x054

0x0121 0054

 

PMA_CMN Register Descriptions

PMA_CMN : SOFT_RESET

Address offset

0x000

Physical address

0x0105 0000

Instance

serdes_0_PMA_CMN

0x0109 0000

serdes_1_PMA_CMN

0x0121 0000

serdes_3_PMA_CMN

0x0111 0000

serdes_2_PMA_CMN

Description

Compulsory register for all SCB slaves, facilitating global soft reset.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

BLOCKID

This returns the block type and chip location.

RO

0x0000

 

 

Read 0x0000

[block_address_PMA_CMN] Indicates the Block chip location.

 

15:9

Reserved

 

RO
Rreturns0s

0x00

8

PERIPH

This asserts functional reset of the peripheral block. It is asserted and left asserted at power-up.

WO

0

 

 

Write 0

[scb_periph_not_in_soft_reset_PMA_CMN] Reset not asserted.

 

 

 

Write 1

[scb_periph_reset_PMA_CMN] SCB registers reset pulsed.

 

7:2

Reserved

 

RO
Rreturns0s

0x00

1

V_MAP

Resets all the volatile register bits.

WO

0

 

 

Write 0

[scb_v_regs_not_in_soft_reset_PMA_CMN] Reset not asserted.

 

 

 

Write 1

[scb_v_regs_reset_PMA_CMN] SCB Volatile reset (i.e. RW-X registers are reset)

 

0

NV_MAP

Resets all the non-volatile register bits (e.g. RW-P bits).

WO

0

 

 

Write 0

[scb_nv_regs_not_in_soft_reset_PMA_CMN] Reset not asserted.

 

 

 

Write 1

[scb_nv_regs_reset_PMA_CMN] SCB Non-Volatile reset (i.e. RW-P registers are reset.

 

 

PMA_CMN : TXPLL_CLKBUF

Address offset

0x004

Physical address

0x0105 0004

Instance

serdes_0_PMA_CMN

0x0109 0004

serdes_1_PMA_CMN

0x0121 0004

serdes_3_PMA_CMN

0x0111 0004

serdes_2_PMA_CMN

Description

TXPLL Clock Buffer Control

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:17

Reserved

 

RO
Rreturns0s

0x0000

16

TXPLL_CLKBUF_EN_APAD

This register is NOT for customers. Please mark this register as RESERVED.
Allow DUALCLK1 input to be used as an analog output

NOTE: The following settings must also be set when en_apad = 1
DUALCLK1_MODE = 2'b00
DUALCLK1_ENTERM = 2'b00
CLKBUF_EN_RDIFF = 1'b0
All TXATESTOUT# and RXATESTOUT# are connected to the APAD input to the clock buffer
TXATESTEN# and RXATESTEN# should be set such that only 1 analog output is driven at a time.
See TXATESTSEL# and RXATESTSEL# for possible output signals

RW

0

 

 

0

[txpll_dualclk1_analog_output_disabled] Disables allowing TX PLL Dual Clock 1 input to be used as an analoog output

 

 

 

1

[txpll_dualclk1_analog_output_enabled] enableds allowing TX PLL Dual Clock 1 input to be used as an analoog output

 

15:14

Reserved

 

RO
Rreturns0s

0x0

13

TXPLL_CLKBUF_EN_PULLUP

 

RW

0

12

TXPLL_CLKBUF_EN_UDRIVE_N

Enable Underdrive capability on CMOS receiver

RW

0

 

 

0

[txpll_clkbuf1_underdrive_disabled] Disables TX PLL LVCMOS Clock 1 Underdrive

 

 

 

1

[txpll_clkbuf1_underdrive_enabled] Enables TX PLL LVCMOS Clock 1 Underdrive

 

11

TXPLL_CLKBUF_EN_UDRIVE_P

Enable Underdrive capability on CMOS receiver

RW

0

 

 

0

[txpll_clkbuf0_underdrive_disabled] Disables TX PLL LVCMOS Clock 0 Underdrive

 

 

 

1

[txpll_clkbuf0_underdrive_enabled] Enables TX PLL LVCMOS Clock 0 Underdrive

 

10

TXPLL_CLKBUF_EN_RDIFF

enabled 100 Ohm Differential Termination (P to N)

RW

0

 

 

0

[txpll_dualclk_100ohm_differential_term_disabled] Disables 100 Ohms Differential Termination (P to N) of TX PLL Dual Clock buffer

 

 

 

1

[txpll_dualclk_100ohm_differential_term_enabled] enableds 100 Ohms Differential Termination (P to N) of TX PLL Dual Clock buffer

 

9

TXPLL_DUALCLK0_EN_HYST

enabled Hysteresis for DUALCLK0

RW

0

 

 

0

[txpll_dualclk0_hysteresis_disabled] Disables Hysteresis for TX PLL Dual Clock 0

 

 

 

1

[txpll_dualclk0_hysteresis_enabled] enableds Hysteresis for TX PLL Dual Clock 0

 

8

TXPLL_DUALCLK1_EN_HYST

enabled Hysteresis for DUALCLK1

RW

0

 

 

0

[txpll_dualclk1_hysteresis_disabled] Disables Hysteresis for TX PLL Dual Clock 1

 

 

 

1

[txpll_dualclk1_hysteresis_enabled] enableds Hysteresis for TX PLL Dual Clock 1

 

7:6

TXPLL_DUALCLK0_ENTERM

Determines Single Ended Termination for DUALCLK0

RW

0x0

 

 

0x0

[txpll_dualclk0_single_end_term_hz_sel] Select infinite resistance for Dual Clock 0 single ended termination.

 

 

 

0x1

[txpll_dualclk0_single_end_term_75ohms_sel] Select 75 ohms for Dual Clock 0 single ended termination.

 

 

 

0x2

[txpll_dualclk0_single_end_term_150ohms_sel] Select 150 ohms for Dual Clock 0 single ended termination.

 

 

 

0x3

[txpll_dualclk0_single_end_term_50ohms_sel] Select 50 ohms for Dual Clock 0 single ended termination.

 

5:4

TXPLL_DUALCLK0_MODE

Determines mode/negative input for DUALCLK0

RW

0x0

 

 

0x0

[txpll_dualclk0_mode_buf_off_sel] Select clock buffer powerdown mode. TX PLL Dual Clock 0 (P) buffer off. The output of the buffer pulled high

 

 

 

0x1

[txpll_dualclk0_mode_cmos_rcvr_act_sel] Select CMOS Clock receiver mode. TX PLL Dual Clock 0 (P) buffer sets to CMOS receiver active mode.

 

 

 

0x2

[txpll_dualclk0_mode_diff_rcvr_act_vref_sel] Select differential clock receive mode with VREF pin. TX PLL Dual Clock 0 (P) buffer sets to differential receiver active mode with VREF pin.

 

 

 

0x3

[txpll_dualclk0_mode_diff_rcvr_act_diff_in_sel] Select differential clock receive mode with differenctial input. TX PLL Dual Clock 0 (P) buffer sets to differential receiver active mode with Dual Clock 1 (N) pin.

 

3:2

TXPLL_DUALCLK1_ENTERM

Determines Single Ended Termination for DUALCLK1

RW

0x0

 

 

0x0

[txpll_dualclk1_single_end_term_hz_sel] Select infinite resistance for Dual Clock 1 single ended termination.

 

 

 

0x1

[txpll_dualclk1_single_end_term_75ohms_sel] Select 75 ohms for Dual Clock 1 single ended termination.

 

 

 

0x2

[txpll_dualclk1_single_end_term_150ohms_sel] Select 150 ohms for Dual Clock 1 single ended termination.

 

 

 

0x3

[txpll_dualclk1_single_end_term_50ohms_sel] Select 50 ohms for Dual Clock 1 single ended termination.

 

1:0

TXPLL_DUALCLK1_MODE

Determines mode/negative input for DUALCLK1

RW

0x0

 

 

0x0

[txpll_dualclk1_mode_buf_off_sel] Select clock buffer powerdown mode. TX PLL Dual Clock1 (N) buffer off. The output of the buffer pulled high

 

 

 

0x1

[txpll_dualclk1_mode_cmos_rcvr_act_sel] Select CMOS Clock receiver mode. TX PLL Dual Clock1 (N) buffer sets to CMOS receiver active mode.

 

 

 

0x2

[txpll_dualclk1_mode_diff_rcvr_act_vref_sel] Select differential clock receive mode with VREF pin. TX PLL Dual Clock1 (N) buffer sets to differential receiver active mode with VREF pin.

 

 

 

0x3

[txpll_dualclk1_mode_diff_rcvr_act_diff_in_sel] Select differential clock receive mode with differenctial input. TX PLL Dual Clock1 (N) buffer sets to differential receiver active mode with Dual Clock0 (P) pin.

 

 

PMA_CMN : TXPLL_CTRL

Address offset

0x008

Physical address

0x0105 0008

Instance

serdes_0_PMA_CMN

0x0109 0008

serdes_1_PMA_CMN

0x0121 0008

serdes_3_PMA_CMN

0x0111 0008

serdes_2_PMA_CMN

Description

TXPLL Control

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:25

Reserved

 

RO
Rreturns0s

0x00

24

TXPLL_LOCK

Transmit PLL lock output

RO

0

23

TXPLL_FOUTAUXDIV2_SEL

Select divided by 2 of auxilary clock output

RW

1

 

 

0

[txpll_auxdiv2_disable] Select Auxilary clock output

 

 

 

1

[txpll_auxdiv_enable] Select divided by 2 of auxilary clock output

 

22

RESET_RTL

Reset all RTL (overrides all RESET_RTL signals)

RW

1

 

 

0

[rtl_reset_all_deasserted] Reset all RTL is deasserted

 

 

 

1

[rtl_reset_all_asserted] Reset all RTL is asserted

 

21

RESET_RTL_TXPLL

Reset all RTL for the TXPLL

RW

1

 

 

0

[txpll_rtl_reset_deasserted] TX PLL RTL reset is deasserted

 

 

 

1

[txpll_rtl_reset_asserted] TX PLL RTL reset is asserted

 

20

TXPLL_CLKRESET

Reset signal synchronized and sent to serializers
Stop Serializer clock for 4 VCO periods when TXPLL_CLKRESET
transitions from 0 to 1.

RW

0

 

 

0

[txpll_clock_reset_deasserted] TX PLL clock reset is deasserted

 

 

 

1

[txpll_clock_reset_asserted] TX PLL clock reset is asserted

 

19

TXPLL_CLKRESETEN

enabled for TXPLL_CLKRESET logic

RW

0

 

 

0

[txpll_clock_reset_disabled] Disables TX PLL clock reset logic

 

 

 

1

[txpll_clock_reset_enabled] enableds TX PLL clock reset logic

 

18

TXPLL_AUXDIVPD

Active High powerdown for auxilary clock output from TXPLL
Auxilary divider is used for jitter attenuator

RW

1

 

 

0

[txpll_auxdiv_powerdown_off] Auxilary clock output from TX PLL is in power up

 

 

 

1

[txpll_auxdiv_powerdown_on] Auxilary clock output from TX PLL is in power down

 

17

TXPLL_PD

Transmit PLL Power Down Control

RW

1

 

 

0

[txpll_powerdown_off] TX PLL is in power up

 

 

 

1

[txpll_powerdown_on] TX PLL is in power down

 

16

TXPLL_STEP_PHASE

Step PLL Phase for one PFD period
Step on every TXPLL_STEP_PHASE transition

RW

0

15:8

TXPLL_PHASESTEPAMOUNT

Signed fractional step for phase stepping (+/- 1/2 integer bit)

RW

0x00

7:5

Reserved

 

RO
Rreturns0s

0x0

4

TXPLL_DSMPD

Transmit PLL fractional modulator PD

The PLL should be in integer mode (DSMPD=1)
for lowest jitter

RW

1

 

 

0

[txpll_fractional_mode_sel] Sets TX PLL in fractional mode

 

 

 

1

[txpll_integer_mode_sel] Sets TX PLL in integer mode

 

3:2

TXPLL_FBDIV_SEL

TXPLL feedback divide control select
Selects modulation for TXPLL

RW

0x0

 

 

0x0

[txpll_feedback_div_from_txpll_fbdiv_frac_sel] Select TXPLL_FBDIV and TXPLL_FRAC register values for TXPLL_FBDIV and TXPLL_FRAC

 

 

 

0x1

[txpll_feedback_div_from_ssmod_fbdiv_frac_sel] Select Spread Spectrum Modulator FBDIV and Spread Spectrum Modulator FRAC for TXPLL_FBDIV and TXPLL_FRAC

 

 

 

0x2

[txpll_feedback_div_from_ja_int_frac_sel] Select Jitter Attenuator INT and Jitter Attenuator FRAC for TXPLL_FBDIV and TXPLL_FRAC

 

 

 

0x3

[txpll_feedback_div_from_ja_int_frac_sel2] Select Jitter Attenuator INT and Jitter Attenuator FRAC for TXPLL_FBDIV and TXPLL_FRAC

 

1

TXPLL_VBGREF_SEL

Select VBG Reference for PLL voltage regulator

RW

0

 

 

0

[txpll_vbgref_vdda_txpll_voltreg_sel] Select VDDA for VBG Reference for TX PLL voltage regulator

 

 

 

1

[txpll_vbgref_1p1v_txpll_voltreg_sel] Select 1.1V for VBG Reference for TX PLL voltage regulator

 

0

TXPLL_BWSEL

Transmit PLL Bandwidth Control

RW

0

 

 

0

[txpll_low_bandwidth_sel] Select low bandwidth for TX PLL bandwidth

 

 

 

1

[txpll_high_bandwidth_sel] Select high bandwidth for TX PLL bandwdith

 

 

PMA_CMN : TXPLL_CLK_SEL

Address offset

0x00C

Physical address

0x0105 000C

Instance

serdes_0_PMA_CMN

0x0109 000C

serdes_1_PMA_CMN

0x0121 000C

serdes_3_PMA_CMN

0x0111 000C

serdes_2_PMA_CMN

Description

TXPLL Clock Select

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:30

Reserved

 

RO
Rreturns0s

0x0

29:27

CDRCLK_OUT_DN_SEL

Select CDRCLK to send out of SERDES Quad
Goes to South External PLL

RW

0x7

 

 

0x0

[cdrclk_out_down_rxcdrclk10_ln1_sel] Select Lane 1 CDR clock10

 

 

 

0x1

[cdrclk_out_down_rxcdrclk10_ln1_sel2] Select Lane 1 CDR clock10

 

 

 

0x2

[cdrclk_out_down_rxcdrclk20_ln1_sel] Select Lane 1 CDR clock20

 

 

 

0x3

[cdrclk_out_down_rxcdrclk40_ln1_sel] Select Lane 1 CDR clock40

 

 

 

0x4

[cdrclk_out_down_rxcdrclk10_ln0_sel] Select Lane 0 CDR clock10

 

 

 

0x5

[cdrclk_out_down_rxcdrclk10_ln0_sel2] Select Lane 0 CDR clock10

 

 

 

0x6

[cdrclk_out_down_rxcdrclk20_ln0_sel] Select Lane 0 CDR clock20

 

 

 

0x7

[cdrclk_out_down_rxcdrclk40_ln0_sel] Select Lane 0 CDR clock40

 

26:24

CDRCLK_OUT_UP_SEL

Select CDRCLK to send UP out of the quad
Goes to North External PLL

RW

0x7

 

 

0x0

[cdrclk_out_up_rxcdrclk10_ln3_sel] Select Lane 3 CDR clock10

 

 

 

0x1

[cdrclk_out_up_rxcdrclk10_ln3_sel2] Select Lane 3 CDR clock10

 

 

 

0x2

[cdrclk_out_up_rxcdrclk20_ln3_sel] Select Lane 3 CDR clock20

 

 

 

0x3

[cdrclk_out_up_rxcdrclk40_ln3_sel] Select Lane 3 CDR clock40

 

 

 

0x4

[cdrclk_out_up_rxcdrclk10_ln2_sel] Select Lane 2 CDR clock10

 

 

 

0x5

[cdrclk_out_up_rxcdrclk10_ln2_sel2] Select Lane 2 CDR clock10

 

 

 

0x6

[cdrclk_out_up_rxcdrclk20_ln2_sel] Select Lane 2 CDR clock20

 

 

 

0x7

[cdrclk_out_up_rxcdrclk40_ln2_sel] Select Lane 2 CDR clock40

 

23:22

Reserved

 

RO
Rreturns0s

0x0

21:19

CDRCLK_LN23_INT_SEL

Select CDRCLK to send to TXPLL Mux
See TXPLL_REFCLK_SEL_SM Logic for selection of this clock

RW

0x7

 

 

0x0

[cdrclk_ln23_int_rxcdrclk10_ln3_sel] Select Lane 3 CDR clock10

 

 

 

0x1

[cdrclk_ln23_int_rxcdrclk10_ln3_sel2] Select Lane 3 CDR clock10

 

 

 

0x2

[cdrclk_ln23_int_rxcdrclk20_ln3_sel] Select Lane 3 CDR clock20

 

 

 

0x3

[cdrclk_ln23_int_rxcdrclk40_ln3_sel] Select Lane 3 CDR clock40

 

 

 

0x4

[cdrclk_ln23_int_rxcdrclk10_ln2_sel] Select Lane 2 CDR clock10

 

 

 

0x5

[cdrclk_ln23_int_rxcdrclk10_ln2_sel2] Select Lane 2 CDR clock10

 

 

 

0x6

[cdrclk_ln23_int_rxcdrclk20_ln2_sel] Select Lane 2 CDR clock20

 

 

 

0x7

[cdrclk_ln23_int_rxcdrclk40_ln2_sel] Select Lane 2 CDR clock40

 

18:16

CDRCLK_LN01_INT_SEL

Select CDRCLK to send to TXPLL Mux
See TXPLL_REFCLK_SEL_SM Logic for selection of this clock

RW

0x7

 

 

0x0

[cdrclk_ln01_int_rxcdrclk10_ln1_sel] Select Lane 1 CDR clock10

 

 

 

0x1

[cdrclk_ln01_int_rxcdrclk10_ln1_sel2] Select Lane 1 CDR clock10

 

 

 

0x2

[cdrclk_ln01_int_rxcdrclk20_ln1_sel] Select Lane 1 CDR clock20

 

 

 

0x3

[cdrclk_ln01_int_rxcdrclk40_ln1_sel] Select Lane 1 CDR clock40

 

 

 

0x4

[cdrclk_ln01_int_rxcdrclk10_ln0_sel] Select Lane 0 CDR clock10

 

 

 

0x5

[cdrclk_ln01_int_rxcdrclk10_ln0_sel2] Select Lane 0 CDR clock10

 

 

 

0x6

[cdrclk_ln01_int_rxcdrclk20_ln0_sel] Select Lane 0 CDR clock20

 

 

 

0x7

[cdrclk_ln01_int_rxcdrclk40_ln0_sel] Select Lane 0 CDR clock40

 

15:13

TXPLL_JA_FREF_SEL

Select Jitter Attenuator Input Reference

RW

0x0

 

 

0x0

[txpll_ja_fref_txpll_refclk_in_sel] Select TXPLL Reference Clock input for TXPLL Jitter Attenuator input clock

 

 

 

0x1

[txpll_ja_fref_txpll_cascade_clk_in_sm_sel] Select cascaded clock soft macro input for TXPLL Jitter Attenuator input clock

 

 

 

0x2

[txpll_ja_fref_txpll_dualclk0_in_sel] Select TX PLL Dual Reference Clock 0 input for TXPLL Jitter Attenuator input clock

 

 

 

0x3

[txpll_ja_fref_txpll_dualclk1_in_sel] Select TX PLL Dual Reference Clock 1 input for TXPLL Jitter Attenuator input clock

 

 

 

0x4

[txpll_ja_fref_cdrclk_ln23_out_sel] Select CDR Clock Lane 2 and 3 mux output for TXPLL Jitter Attenuator input clock

 

 

 

0x5

[txpll_ja_fref_cdrclk_ln01_out_sel] Select CDR Clock Lane 0 and 1 mux output for TXPLL Jitter Attenuator input clock

 

 

 

0x6

[txpll_ja_fref_logic0_sel] Select Logic 0 for TXPLL Jitter Attenuator input clock

 

 

 

0x7

[txpll_ja_fref_atpg_testclk_sel] Select ATPG test clock for TXPLL Jitter Attenuator input clock

 

12:10

CASCADE_CLK_SEL_SM

For SerDes Quad Transmit PLL
RTL Cascade clock select

RW

0x7

 

 

0x0

[txpll_cascade_clk_sm_txpll_dualclk0_in_sel] Select TX PLL Dual Reference Clock 0 input for TX PLL cascade soft macro mux input

 

 

 

0x1

[txpll_cascade_clk_sm_txpll_dualclk1_in_sel] Select TX PLL Dual Reference Clock 1 input for TX PLL cascade soft macro mux input

 

 

 

0x2

[txpll_cascade_clk_sm_txpll_foutauxdiv_sel] Select TX PLL AUX DIV clock for TX PLL cascade soft macro mux input

 

 

 

0x3

[txpll_cascade_clk_sm_txpll_clksscg_sel] Select TX PLL SSCG clock for TX PLL cascade soft macro mux input

 

 

 

0x4

[txpll_cascade_clk_sm_txpll_lock_sel] Select TX PLL lock signal for TX PLL cascade soft macro mux input

 

 

 

0x5

[txpll_cascade_clk_sm_logic0_sel] Select logic 0 for TX PLL cascade soft macro mux input

 

 

 

0x6

[txpll_cascade_clk_sm_txpll_cascade_clk_in_sm_sel] Select TX PLL cascade soft macro mux input for TX PLL cascade soft macro mux input

 

 

 

0x7

[txpll_cascade_clk_sm_txpll_cascade_clk_in_sm_sel2] Select TX PLL cascade soft macro mux input for TX PLL cascade soft macro mux input

 

9:8

CASCADE_CLK_SEL_HM

For SerDes Quad Transmit PLL
Hard Macro Cascade Clock Select

RW

0x0

 

 

0x0

[txpll_cascade_clk_hm_txpll_dualclk0_in_sel] Select TX PLL Dual Reference Clock 0 input for TX PLL cascade hard macro clock input

 

 

 

0x1

[txpll_cascade_clk_hm_txpll_dualclk1_in_sel] Select TX PLL Dual Reference Clock 1 input for TX PLL cascade hard macro clock input

 

 

 

0x2

[txpll_cascade_clk_hm_txpll_cascade_clk_in_hm_sel] Select TX PLL Cascade hard macro clock input from the external PLL above for TX PLL cascade hard macro clock input

 

 

 

0x3

[txpll_cascade_clk_hm_txpll_cascade_clk_in_hm_sel2] Select TX PLL Cascade hard macro clock input from the external PLL above for TX PLL cascade hard macro clock input

 

7:5

Reserved

 

RO
Rreturns0s

0x0

4:2

TXPLL_REFCLK_SEL_SM

Select clock to TX PLL Soft Macro Reference Clock input

RW

0x0

 

 

0x0

[txpll_refclk_sm_txpll_refclk_in_sel] Select TXPLL Reference Clock input for TXPLL soft macro reference clock input

 

 

 

0x1

[txpll_refclk_sm_txpll_cascade_clk_in_sm_sel] Select cascaded clock soft macro input for TXPLL soft macro reference clock input

 

 

 

0x2

[txpll_refclk_sm_txpll_dualclk0_in_sel] Select TX PLL Dual Reference Clock 0 input for TXPLL soft macro reference clock input

 

 

 

0x3

[txpll_refclk_sm_txpll_dualclk1_in_sel] Select TX PLL Dual Reference Clock 1 input for TXPLL soft macro reference clock input

 

 

 

0x4

[txpll_refclk_sm_cdrclk_ln23_out_sel] Select CDR Clock Lane 2 and 3 mux output for TXPLL soft macro reference clock input

 

 

 

0x5

[txpll_refclk_sm_cdrclk_ln01_out_sel] Select CDR Clock Lane 0 and 1 mux output for TXPLL soft macro reference clock input

 

 

 

0x6

[txpll_refclk_sm_txpll_refclk_in_sel2] Select TXPLL Reference Clock input for TXPLL soft macro reference clock input

 

 

 

0x7

[txpll_refclk_sm_logic0_sel] Select Logic 0 for TXPLL soft macro reference clock input

 

1:0

TXPLL_REFCLK_SEL_HM

TXPLL Reference Clock Mux

RW

0x0

 

 

0x0

[txpll_refclk_hm_txpll_dualclk0_in_sel] Select TX PLL Dual-Reference clock 0 for TX PLL hard macro reference clock input

 

 

 

0x1

[txpll_refclk_hm_txpll_cascade_clk_in_hm_sel] Select hard macro cascade clock input for TX PLL hard macro reference clock input

 

 

 

0x2

[txpll_refclk_hm_txpll_refclk_hm_sm_out_sel] Select TXPLL_REFCLK_SEL_SM mux output clock for TX PLL hard macro reference clock input

 

 

 

0x3

[txpll_refclk_hm_txpll_refclk_hm_sm_out_sel2] Select TXPLL_REFCLK_SEL_SM mux output clock for TX PLL hard macro reference clock input

 

 

PMA_CMN : TXPLL_DIV_1

Address offset

0x010

Physical address

0x0105 0010

Instance

serdes_0_PMA_CMN

0x0109 0010

serdes_1_PMA_CMN

0x0121 0010

serdes_3_PMA_CMN

0x0111 0010

serdes_2_PMA_CMN

Description

TXPLL Dividers

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:28

Reserved

 

RO
Rreturns0s

0x0

27:16

TXPLL_FBDIV

Transmit PLL feedback divide value from (16 in integer mode
Supports any divide value of 8,9,10,12,13,15,16,...
Must be at least 19 in fractional-N mode
The VCO frequency is given by (f_ref * FBDIV / REFDIV / POSTDIV),
where f_ref is the reference frequency
The bit rate is given by (2 * f_ref * FBDIV / REFDIV / POSTDIV)
See TXPOSTDIV# for post-divider settings
The VCO frequency should be programmed to half the bit rate
Example : for 10Gb/s, the VCO should be programmed to 5GHz

RW

0x019

15:12

Reserved

 

RO
Rreturns0s

0x0

11:0

TXPLL_AUXDIV

Transmit PLL auxilary clock output
FOUTAUXDIV= VCO Frequency / TXPLL_AUXDIV
Supports any divide value of 8,9,10,12,13,15,16,...
FOUTAUXDIV connected to Jitter Attenuator FFB port
Auxilary divider is used for jitter attenuator

RW

0x019

 

PMA_CMN : TXPLL_DIV_2

Address offset

0x014

Physical address

0x0105 0014

Instance

serdes_0_PMA_CMN

0x0109 0014

serdes_1_PMA_CMN

0x0121 0014

serdes_3_PMA_CMN

0x0111 0014

serdes_2_PMA_CMN

Description

TXPLL Dividers

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:30

Reserved

 

RO
Rreturns0s

0x0

29:24

TXPLL_REFDIV

Transmit PLL reference divide value (1 to 63)
For PLL programming, see FBDIV notes

RW

0x01

23:0

TXPLL_FRAC

PLL fractional part of feedback divide value

RW

0x00 0001

 

PMA_CMN : TXPLL_JA_1

Address offset

0x018

Physical address

0x0105 0018

Instance

serdes_0_PMA_CMN

0x0109 0018

serdes_1_PMA_CMN

0x0121 0018

serdes_3_PMA_CMN

0x0111 0018

serdes_2_PMA_CMN

Description

TXPLL JA Control

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

TXPLL_JA_DIVFFB

Jitter Attenuator PLL
Integer divider for FFB

RW

0x0064

15:0

TXPLL_JA_DIVFIN

Jitter Attenuator PLL
Integer divider for FIN

RW

0x0064

 

PMA_CMN : TXPLL_JA_2

Address offset

0x01C

Physical address

0x0105 001C

Instance

serdes_0_PMA_CMN

0x0109 001C

serdes_1_PMA_CMN

0x0121 001C

serdes_3_PMA_CMN

0x0111 001C

serdes_2_PMA_CMN

Description

TXPLL JA Control

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

TXPLL_JA_SYNCCNTMAX

Jitter Attenuator PLL
FIN pulses will be counted for SYNCCNTMAX pulses to determine frequency match

RW

0x0000 0064

 

PMA_CMN : TXPLL_JA_3

Address offset

0x020

Physical address

0x0105 0020

Instance

serdes_0_PMA_CMN

0x0109 0020

serdes_1_PMA_CMN

0x0121 0020

serdes_3_PMA_CMN

0x0111 0020

serdes_2_PMA_CMN

Description

TXPLL JA Control

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

TXPLL_JA_TARGETCNT

Jitter Attenuator PLL
If number of pulse counts between FIN and FFB is less than TARGETCNT the frequency comparator will declare frequencies match (Set FLOCK=1'b1)

RW

0x0064

15:0

TXPLL_JA_CNTOFFSET

Jitter Attenuator PLL
Allows for frequency multiplication in the frequency control loop. By setting CNTOFFSET to SYNCCNTMAX / K, where K is the multiplication ratio, the frequency detector will output a zero frequency error when CNTOFFSET pulses have been counted from the reference and SYNCCNTMAX pulses have been counted from the feedback.

RW

0x0064

 

PMA_CMN : TXPLL_JA_4

Address offset

0x024

Physical address

0x0105 0024

Instance

serdes_0_PMA_CMN

0x0109 0024

serdes_1_PMA_CMN

0x0121 0024

serdes_3_PMA_CMN

0x0111 0024

serdes_2_PMA_CMN

Description

TXPLL JA Control

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:29

Reserved

 

RO
Rreturns0s

0x0

28:24

TXPLL_JA_FKI

Jitter Attenuator PLL
K Gain for integral frequency comparison loop
Gain=$M\times 2^K$

RW

0x01

23:16

TXPLL_JA_FMI

Jitter Attenuator PLL
M gain for integral frequency comparison loop
Gain=$M\times 2^K$

RW

0x01

15:0

TXPLL_JA_OTDLY

Jitter Attenuator PLL
Delay in FFB pulses from when FLOCK=1'b1 to when the ADPLL transfers control from the frequency comparison loop to the phase comparison loop -- allows additional settling and avoids glitches in FLOCK output

RW

0x0001

 

PMA_CMN : TXPLL_JA_5

Address offset

0x028

Physical address

0x0105 0028

Instance

serdes_0_PMA_CMN

0x0109 0028

serdes_1_PMA_CMN

0x0121 0028

serdes_3_PMA_CMN

0x0111 0028

serdes_2_PMA_CMN

Description

TXPLL JA Control

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:24

TXPLL_JA_PMI2

Jitter Attenuator PLL
Fine settling M gain for integral phase comparison loop
Gain=$M\times 2^K$

RW

0x01

23:16

TXPLL_JA_PMI1

Jitter Attenuator PLL
Course settling M gain for integral phase comparison loop
Gain=$M\times 2^K$

RW

0x01

15:8

TXPLL_JA_PMP2

Jitter Attenuator PLL
Fine settling M gain for proportional phase comparison loop
Gain=$M\times 2^K$

RW

0x01

7:0

TXPLL_JA_PMP1

Jitter Attenuator PLL
Course settling M gain for proportional phase comparison loop
Gain=$M\times 2^K$

RW

0x01

 

PMA_CMN : TXPLL_JA_6

Address offset

0x02C

Physical address

0x0105 002C

Instance

serdes_0_PMA_CMN

0x0109 002C

serdes_1_PMA_CMN

0x0121 002C

serdes_3_PMA_CMN

0x0111 002C

serdes_2_PMA_CMN

Description

TXPLL JA Control

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:29

Reserved

 

RO
Rreturns0s

0x0

28:24

TXPLL_JA_PKI2

Jitter Attenuator PLL
2s Complement Fine settling K gain for integral phase comparison loop
Gain=$M\times 2^K$

RW

0x01

23:21

Reserved

 

RO
Rreturns0s

0x0

20:16

TXPLL_JA_PKI1

Jitter Attenuator PLL
2s Copmplement Course settling K gain for integral phase comparison loop
Gain=$M\times 2^K$

RW

0x01

15:13

Reserved

 

RO
Rreturns0s

0x0

12:8

TXPLL_JA_PKP2

Jitter Attenuator PLL
2s Complement Fine settling K gain for proportional phase comparison loop
Gain=$M\times 2^K$

RW

0x01

7:5

Reserved

 

RO
Rreturns0s

0x0

4:0

TXPLL_JA_PKP1

Jitter Attenuator PLL
2s Complement Course settling K gain for proportional phase comparison loop
Gain=$M\times 2^K$

RW

0x01

 

PMA_CMN : TXPLL_JA_7

Address offset

0x030

Physical address

0x0105 0030

Instance

serdes_0_PMA_CMN

0x0109 0030

serdes_1_PMA_CMN

0x0121 0030

serdes_3_PMA_CMN

0x0111 0030

serdes_2_PMA_CMN

Description

TXPLL JA Control

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:27

Reserved

 

RO
Rreturns0s

0x00

26

TXPLL_JA_PROGRAM

Jitter Attenuator PLL
Diagnostic Control Signal

RW

1

 

 

0

[txpll_ja_program_diagnostic_mode_sel] Select dignostic mode

 

 

 

1

[txpll_ja_program_normal_mode_sel] Select normal mode

 

25

TXPLL_JA_ONTARGETOV

Jitter Attenuator PLL
Diagnostic Control Signal

RW

1

 

 

0

[txpll_ja_ontargetov_diagnostic_mode_sel] Select dignostic mode

 

 

 

1

[txpll_ja_ontargetov_normal_mode_sel] Select normal mode

 

24

TXPLL_JA_FDONLY

Jitter Attenuator PLL
Force Frequency Control

RW

1

 

 

0

[txpll_ja_frequency_phase_control_sel] Select Frequency and Phase control for TX PLL Jitter Attenuator.

 

 

 

1

[txpll_ja_frequency_only_control_sel] Select Frequency only control for TX PLL Jitter Attenuator.

 

23:0

TXPLL_JA_DELAYK

Jitter Attenuator PLL
Phase comparison loop will settle initially using PKP1 and PKI1 (course settling) parameters, and switch over to PKP2 and PKI2 (fine settling) parameters DELAYK FFB pulses after phase comparison loop takes over (OTDLY + DELAYK FFB pulses after initial frequency lock)

RW

0x00 0001

 

PMA_CMN : TXPLL_JA_8

Address offset

0x034

Physical address

0x0105 0034

Instance

serdes_0_PMA_CMN

0x0109 0034

serdes_1_PMA_CMN

0x0121 0034

serdes_3_PMA_CMN

0x0111 0034

serdes_2_PMA_CMN

Description

TXPLL JA Control

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:26

Reserved

 

RO
Rreturns0s

0x00

25

TXPLL_JA_HOLD

Jitter Attenuator PLL
Hold output state of the DPLL.

RW

0

 

 

0

[txpll_ja_hold_output_disabled] Normal operational mode.

 

 

 

1

[txpll_ja_hold_output_enabled] enableds holding output state of the DPLL. The DPLL will not phase lock in this state.

 

24

TXPLL_JA_PRESET_EN

Jitter Attenuator PLL
Load Preset INT and FRAC values into DPLL

RW

0

 

 

0

[txpll_ja_preset_disabled] Diables loading preset INT and FRAC values into DPLL

 

 

 

1

[txpll_ja_preset_enabled] enableds loading preset INT and FRAC values into DPLL

 

23:0

TXPLL_JA_FRAC_PRESET

Jitter Attenuator PLL
Preset FRAC output, if PRESET_EN --> 1'b1, output is set to this value

RW

0x00 0000

 

PMA_CMN : TXPLL_JA_9

Address offset

0x038

Physical address

0x0105 0038

Instance

serdes_0_PMA_CMN

0x0109 0038

serdes_1_PMA_CMN

0x0121 0038

serdes_3_PMA_CMN

0x0111 0038

serdes_2_PMA_CMN

Description

TXPLL JA Control

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:28

Reserved

 

RO
Rreturns0s

0x0

27:16

TXPLL_JA_INT_PD_OUT

Jitter Attenuator PLL
Integer bits of Phase Detector Integrator Output

RO

0x018

15:12

Reserved

 

RO
Rreturns0s

0x0

11:0

TXPLL_JA_INT_PRESET

Jitter Attenuator PLL
Preset INT output, if PRESET_EN --> 1'b1, output is set to this value

RW

0x014

 

PMA_CMN : TXPLL_JA_10

Address offset

0x03C

Physical address

0x0105 003C

Instance

serdes_0_PMA_CMN

0x0109 003C

serdes_1_PMA_CMN

0x0121 003C

serdes_3_PMA_CMN

0x0111 003C

serdes_2_PMA_CMN

Description

TXPLL JA Control

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:26

Reserved

 

RO
Rreturns0s

0x00

25

TXPLL_JA_PHASE_LOCK

Jitter Attenuator PLL
Indicates the DPLL is in fine tune phase tracking mode
1'b1 -- The PLL is in fine tune phase tracking mode
1'b0 -- The PLL is either in coarse tune tracking mode or (if FLOCK=1'b0) not frequency locked

RO

0

24

TXPLL_JA_FLOCK

Jitter Attenuator PLL
Indicates the DPLL has achieved frequency lock
1'b1 -- Frequencies have maintained lock within TARGETCNT for OTDLY FFB pulses
1'b0 -- Frequency comparator has detected a mismatch in FIN and FFB pulse counts

RO

0

23:0

TXPLL_JA_FRAC_PD_OUT

Jitter Attenuator PLL
Fractional bits of Phase Detector Integrator Output

RO

0x00 0000

 

PMA_CMN : TXPLL_JA_RST

Address offset

0x040

Physical address

0x0105 0040

Instance

serdes_0_PMA_CMN

0x0109 0040

serdes_1_PMA_CMN

0x0121 0040

serdes_3_PMA_CMN

0x0111 0040

serdes_2_PMA_CMN

Description

TXPLL JA RESETs

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

Reserved

 

RO
Rreturns0s

0x000 0000

6

TXPLL_JA_RESET_CLKS_EXT

Jitter Attenuator PLL
RESET for PLL Sync Clock Domain when RESET_CLKS_OVERRIDE=1'b1

RW

1

 

 

0

[txpll_jareset_clks_ext_deasserted] TX PLL Jitter Attenuator reset for PLL Sync clock domain is deasserted ( Active when TXPLL_JA_RESET_CLKS_OVERRIDE = 1'b1)

 

 

 

1

[txpll_jareset_clks_ext_asserted] TX PLL Jitter Attenuator reset for PLL Sync clock domain is asserted. ( Active when TXPLL_JA_RESET_CLKS_OVERRIDE = 1'b1)

 

5

TXPLL_JA_RESET_CLKS_OVERRIDE

Jitter Attenuator PLL
Override Signal for PLL Sync Clock Domain Reset Signal

RW

0

 

 

0

[txpll_ja_reset_clks_override_disabled] Disables TX PLL Jitter Attenuator override signal for PLL Sync clock domain reset signal.

 

 

 

1

[txpll_ja_reset_clks_override_enabled] enableds TX PLL Jitter Attenuator override signal for PLL Sync clock domain reset signal.

 

4

TXPLL_JA_RESET_FIN_EXT

Jitter Attenuator PLL
RESET for Input Clock Domain when RESET_FIN_OVERRIDE=1'b1

RW

1

 

 

0

[txpll_jareset_fin_ext_deasserted] TX PLL Jitter Attenuator reset for input clock domain is deasserted ( Active when TXPLL_JA_RESET_FIN_OVERRIDE = 1'b1)

 

 

 

1

[txpll_jareset_fin_ext_asserted] TX PLL Jitter Attenuator reset for input clock domain is asserted. ( Active when TXPLL_JA_RESET_FIN_OVERRIDE = 1'b1)

 

3

TXPLL_JA_RESET_FIN_OVERRIDE

Jitter Attenuator PLL
Override Signal for Input Clock Domain Reset Signal

RW

0

 

 

0

[txpll_ja_reset_fin_override_disabled] Disables TX PLL Jitter Attenuator override signal for input clock domain reset signal.

 

 

 

1

[txpll_ja_reset_fin_override_enabled] enableds TX PLL Jitter Attenuator override signal for input clock domain reset signal.

 

2

TXPLL_JA_RESET_FFB_EXT

Jitter Attenuator PLL
RESET for Feedback Clock Domain when RESET_FFB_OVERRIDE=1'b1

RW

1

 

 

0

[txpll_jareset_ffb_ext_deasserted] TX PLL Jitter Attenuator reset for feedback clock domain is deasserted ( Active when TXPLL_JA_RESET_FFB_OVERRIDE = 1'b1)

 

 

 

1

[txpll_jareset_ffb_ext_asserted] TX PLL Jitter Attenuator reset for feedback clock domain is asserted. ( Active when TXPLL_JA_RESET_FFB_OVERRIDE = 1'b1)

 

1

TXPLL_JA_RESET_FFB_OVERRIDE

Jitter Attenuator PLL
Override Signal for Feedback Clock Domain Reset Signal

RW

0

 

 

0

[txpll_ja_reset_ffb_override_disabled] Disables TX PLL Jitter Attenuator override signal for feedback clock domain reset signal.

 

 

 

1

[txpll_ja_reset_ffb_override_enabled] enableds TX PLL Jitter Attenuator override signal for feedback clock domain reset signal.

 

0

TXPLL_JA_RESET

Jitter Attenuator PLL
Resets all internal counters and registers to their default state
INITINT, INITFRAC and INITDPLLSTATE are ignored

RW

1

 

 

0

[txpll_ja_reset_deasserted] TX PLL Jitter Attenuator reset is deasserted

 

 

 

1

[txpll_ja_reset_asserted] TX PLL Jitter Attenuator reset is asserted

 

 

PMA_CMN : SERDES_SSMOD

Address offset

0x044

Physical address

0x0105 0044

Instance

serdes_0_PMA_CMN

0x0109 0044

serdes_1_PMA_CMN

0x0121 0044

serdes_3_PMA_CMN

0x0111 0044

serdes_2_PMA_CMN

Description

SERDES QUAD Spread Spectrum

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:29

Reserved

 

RO
Rreturns0s

0x0

28

RN_FILTER

enableds High-Pass filtering of noise source

RW

0

 

 

0

[ssmod_rn_filter_disabled] Disables High-Pass filtering of noise source

 

 

 

1

[ssmod_rn_filter_enabled] enableds High-Pass filtering of noise source

 

27:26

RN_SEL

Selects between 3 different noise patterns.

RW

0x0

 

 

0x0

[ssmod_noise_pattern0_sel] Select noise pattern 0

 

 

 

0x1

[ssmod_noise_pattern1_sel] Select noise pattern 1

 

 

 

0x2

[ssmod_noise_pattern2_sel] Select noise pattern 2

 

 

 

0x3

[ssmod_noise_pattern2_sel2] Select noise pattern 2

 

25:24

SSMOD_SEL_EXTWAVE

Select between EXTWAVEVAL data input, Pseudo-random Noise, and internal lookup table

RW

0x0

 

 

0x0

[ssmod_internal_lookup_table_sel] Select internal 128 point triangular wave table

 

 

 

0x1

[ssmod_external_wave_table_sel] Select external wave table

 

 

 

0x2

[ssmod_pseudo_random_noise_sel] Select Pseudo-random Noise

 

 

 

0x3

[ssmod_pseudo_random_noise_sel2] Select Pseudo-random Noise

 

23:16

SSMOD_EXT_MAXADDR

Spread-Spectrum Modulator
External wave table maximum address value input

RW

0x7F

15:14

Reserved

 

RO
Rreturns0s

0x0

13:8

SSMOD_DIVVAL

Spread-Spectrum Modulator
Divider required to set the modulation frequency

RW

0x01

7

Reserved

 

RO
Rreturns0s

0

6:2

SSMOD_SPREAD

Spread-Spectrum Modulator
Sets modulation depth
Modulation Depth = SPREAD * 0.1%
ie. SPREAD=5'b5 = Modulation Depth of 0.5%

RW

0x00

1

SSMOD_DISABLE_SSCG

Spread-Spectrum Modulator
Bypass the modulator

RW

1

 

 

0

[ssmod_bypass_disabled] Disable Spread Spectrum Modulator Bypass function

 

 

 

1

[ssmod_bypass_enabled] enabled Spread Spectrum Modulator Bypass function

 

0

SSMOD_DOWNSPREAD

Spread-Spectrum Modulator
Selects center spread or downspread

RW

0

 

 

0

[ssmod_center_spread_sel] Select center spread for Spread Spectrum Modulator

 

 

 

1

[ssmod_down_spread_sel] Select down spread for Spread Spectrum Modulator

 

 

PMA_CMN : SERDES_RTERM

Address offset

0x050

Physical address

0x0105 0050

Instance

serdes_0_PMA_CMN

0x0109 0050

serdes_1_PMA_CMN

0x0121 0050

serdes_3_PMA_CMN

0x0111 0050

serdes_2_PMA_CMN

Description

SERDES Resistor Termination Calibration
(ATE TRIM)

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:20

Reserved

 

RO
Rreturns0s

0x000

19:16

RTERMCAL150

150 Ohms Termination Resistor Values

RW

0xD

15:12

Reserved

 

RO
Rreturns0s

0x0

11:8

RTERMCAL100

100 Ohms Termination Resistor Values

RW

0x7

7:4

Reserved

 

RO
Rreturns0s

0x0

3:0

RTERMCAL85

85 Ohms Termination Resistor Values

RW

0x3

 

PMA_CMN : SERDES_RTT

Address offset

0x054

Physical address

0x0105 0054

Instance

serdes_0_PMA_CMN

0x0109 0054

serdes_1_PMA_CMN

0x0121 0054

serdes_3_PMA_CMN

0x0111 0054

serdes_2_PMA_CMN

Description

SERDES Resistor Termination Calibration

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:17

Reserved

 

RO
Rreturns0s

0x0000

16

RTT_NCOMP

Resistor Termination Calibration comparator output

RO

0

15:10

Reserved

 

RO
Rreturns0s

0x00

9:8

RTT_CURRENT_PROG

Current Trim for RTT Comparison

RW

0x0

7:4

Reserved

 

RO
Rreturns0s

0x0

3:0

RTT_CAL_TERM

Resistor Termination Calibration Resistance Selection

RW

0x0

 

PMA_CMN has no common memories.