This section
provides information on the PMA_LANE Module Instance. Each of the module
registers is described below.
Register
Lock Bits can prevent the XCVR configuration registers from being overwritten
by hosts that have access to these registers. The lock bits can be managed
using the Configure Register Lock Bits utility in the Libero SoC. The following registers can be locked.
· DES_CLK_CTRL
· DES_DFEEM_CTRL_3
· DES_DFE_CTRL_2
· DES_EM_CTRL_2
· DES_IN_TERM
· DES_PKDET
· DES_RTL_LOCK_CTRL
· DES_RXPLL_DIV
· DES_TEST_BUS
· SERDES_RTL_CTRL
· SER_CLK_CTRL
· SER_CTRL
· SER_DRV_BYP
· SER_DRV_CTRL
· SER_DRV_CTRL_SEL
· SER_DRV_DATA_CTRL
· SER_RXDET_CTRL
· SER_TERM_CTRL
· SER_TEST_BUS
· SOFT_RESET
Return to mpfs_ioscb_memmap_dri
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
RW |
32 |
0x0000 0000 |
0x000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
|
RW |
32 |
0x0000 0015 |
0x008 |
|
RW |
32 |
0x0000 0000 |
0x00C |
|
RW |
32 |
0x0000 0015 |
0x010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
|
RW |
32 |
0x0000 0000 |
0x020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
|
RW |
32 |
0x0000 00A7 |
0x030 |
|
RW |
32 |
0x0000 00AC |
0x034 |
|
RW |
32 |
0x0000 00C8 |
0x038 |
|
RW |
32 |
0x0000 0008 |
0x03C |
|
RW |
32 |
0x0000 2219 |
0x040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
|
RW |
32 |
0x0000 003C |
0x048 |
|
RW |
32 |
0x0000 002F |
0x04C |
|
RW |
32 |
0x0000 0000 |
0x050 |
|
RW |
32 |
0x0232 2219 |
0x054 |
|
RW |
32 |
0x2218 4418 |
0x058 |
|
RW |
32 |
0x0000 0230 |
0x05C |
|
RW |
32 |
0x0000 0000 |
0x070 |
|
RW |
32 |
0x0000 0070 |
0x074 |
|
RW |
32 |
0x0000 0006 |
0x078 |
|
RW |
32 |
0x0000 0000 |
0x07C |
|
RW |
32 |
0x0000 8A10 |
0x080 |
|
RO |
32 |
0x0000 0000 |
0x084 |
|
RW |
32 |
0x0000 0000 |
0x088 |
|
RW |
32 |
0x0000 0000 |
0x08C |
|
RW |
32 |
0x0000 7200 |
0x090 |
|
RW |
32 |
0xE000 0000 |
0x094 |
|
RW |
32 |
0x0000 0000 |
0x098 |
|
RW |
32 |
0x0100 0000 |
0x09C |
|
RW |
32 |
0x0000 0000 |
0x0A0 |
|
RW |
32 |
0x001B 3423 |
0x0A4 |
|
RW |
32 |
0x0023 2C27 |
0x0A8 |
|
RW |
32 |
0x001B 1B1B |
0x0AC |
|
RW |
32 |
0x001B 1B14 |
0x0B0 |
|
RW |
32 |
0x0024 0C0A |
0x0B4 |
|
RW |
32 |
0x1B38 3B38 |
0x0B8 |
|
RW |
32 |
0x0000 0100 |
0x0C0 |
|
RW |
32 |
0x6410 0702 |
0x0D0 |
|
RW |
32 |
0x0103 4018 |
0x0D4 |
|
RW |
32 |
0x0080 0000 |
0x0D8 |
|
RW |
32 |
0x0000 0000 |
0x0DC |
|
RW |
32 |
0x0000 0000 |
0x0E0 |
|
RO |
32 |
0x0000 0000 |
0x0E4 |
|
RO |
32 |
0x0000 0000 |
0x0E8 |
|
RO |
32 |
0x0000 0000 |
0x0EC |
|
RO |
32 |
0x0000 0000 |
0x0F0 |
|
RO |
32 |
0x0000 0000 |
0x0F4 |
|
RO |
32 |
0x0000 0000 |
0x0F8 |
|
RO |
32 |
0x0000 0000 |
0x0FC |
|
RO |
32 |
0x0000 0000 |
0x100 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0104 1000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x0104 1004 |
|
RW |
32 |
0x0000 0015 |
0x008 |
0x0104 1008 |
|
RW |
32 |
0x0000 0000 |
0x00C |
0x0104 100C |
|
RW |
32 |
0x0000 0015 |
0x010 |
0x0104 1010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x0104 1014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x0104 1018 |
|
RW |
32 |
0x0000 0000 |
0x020 |
0x0104 1020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x0104 1024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x0104 1028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
0x0104 102C |
|
RW |
32 |
0x0000 00A7 |
0x030 |
0x0104 1030 |
|
RW |
32 |
0x0000 00AC |
0x034 |
0x0104 1034 |
|
RW |
32 |
0x0000 00C8 |
0x038 |
0x0104 1038 |
|
RW |
32 |
0x0000 0008 |
0x03C |
0x0104 103C |
|
RW |
32 |
0x0000 2219 |
0x040 |
0x0104 1040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
0x0104 1044 |
|
RW |
32 |
0x0000 003C |
0x048 |
0x0104 1048 |
|
RW |
32 |
0x0000 002F |
0x04C |
0x0104 104C |
|
RW |
32 |
0x0000 0000 |
0x050 |
0x0104 1050 |
|
RW |
32 |
0x0232 2219 |
0x054 |
0x0104 1054 |
|
RW |
32 |
0x2218 4418 |
0x058 |
0x0104 1058 |
|
RW |
32 |
0x0000 0230 |
0x05C |
0x0104 105C |
|
RW |
32 |
0x0000 0000 |
0x070 |
0x0104 1070 |
|
RW |
32 |
0x0000 0070 |
0x074 |
0x0104 1074 |
|
RW |
32 |
0x0000 0006 |
0x078 |
0x0104 1078 |
|
RW |
32 |
0x0000 0000 |
0x07C |
0x0104 107C |
|
RW |
32 |
0x0000 8A10 |
0x080 |
0x0104 1080 |
|
RO |
32 |
0x0000 0000 |
0x084 |
0x0104 1084 |
|
RW |
32 |
0x0000 0000 |
0x088 |
0x0104 1088 |
|
RW |
32 |
0x0000 0000 |
0x08C |
0x0104 108C |
|
RW |
32 |
0x0000 7200 |
0x090 |
0x0104 1090 |
|
RW |
32 |
0xE000 0000 |
0x094 |
0x0104 1094 |
|
RW |
32 |
0x0000 0000 |
0x098 |
0x0104 1098 |
|
RW |
32 |
0x0100 0000 |
0x09C |
0x0104 109C |
|
RW |
32 |
0x0000 0000 |
0x0A0 |
0x0104 10A0 |
|
RW |
32 |
0x001B 3423 |
0x0A4 |
0x0104 10A4 |
|
RW |
32 |
0x0023 2C27 |
0x0A8 |
0x0104 10A8 |
|
RW |
32 |
0x001B 1B1B |
0x0AC |
0x0104 10AC |
|
RW |
32 |
0x001B 1B14 |
0x0B0 |
0x0104 10B0 |
|
RW |
32 |
0x0024 0C0A |
0x0B4 |
0x0104 10B4 |
|
RW |
32 |
0x1B38 3B38 |
0x0B8 |
0x0104 10B8 |
|
RW |
32 |
0x0000 0100 |
0x0C0 |
0x0104 10C0 |
|
RW |
32 |
0x6410 0702 |
0x0D0 |
0x0104 10D0 |
|
RW |
32 |
0x0103 4018 |
0x0D4 |
0x0104 10D4 |
|
RW |
32 |
0x0080 0000 |
0x0D8 |
0x0104 10D8 |
|
RW |
32 |
0x0000 0000 |
0x0DC |
0x0104 10DC |
|
RW |
32 |
0x0000 0000 |
0x0E0 |
0x0104 10E0 |
|
RO |
32 |
0x0000 0000 |
0x0E4 |
0x0104 10E4 |
|
RO |
32 |
0x0000 0000 |
0x0E8 |
0x0104 10E8 |
|
RO |
32 |
0x0000 0000 |
0x0EC |
0x0104 10EC |
|
RO |
32 |
0x0000 0000 |
0x0F0 |
0x0104 10F0 |
|
RO |
32 |
0x0000 0000 |
0x0F4 |
0x0104 10F4 |
|
RO |
32 |
0x0000 0000 |
0x0F8 |
0x0104 10F8 |
|
RO |
32 |
0x0000 0000 |
0x0FC |
0x0104 10FC |
|
RO |
32 |
0x0000 0000 |
0x100 |
0x0104 1100 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0104 2000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x0104 2004 |
|
RW |
32 |
0x0000 0015 |
0x008 |
0x0104 2008 |
|
RW |
32 |
0x0000 0000 |
0x00C |
0x0104 200C |
|
RW |
32 |
0x0000 0015 |
0x010 |
0x0104 2010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x0104 2014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x0104 2018 |
|
RW |
32 |
0x0000 0000 |
0x020 |
0x0104 2020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x0104 2024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x0104 2028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
0x0104 202C |
|
RW |
32 |
0x0000 00A7 |
0x030 |
0x0104 2030 |
|
RW |
32 |
0x0000 00AC |
0x034 |
0x0104 2034 |
|
RW |
32 |
0x0000 00C8 |
0x038 |
0x0104 2038 |
|
RW |
32 |
0x0000 0008 |
0x03C |
0x0104 203C |
|
RW |
32 |
0x0000 2219 |
0x040 |
0x0104 2040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
0x0104 2044 |
|
RW |
32 |
0x0000 003C |
0x048 |
0x0104 2048 |
|
RW |
32 |
0x0000 002F |
0x04C |
0x0104 204C |
|
RW |
32 |
0x0000 0000 |
0x050 |
0x0104 2050 |
|
RW |
32 |
0x0232 2219 |
0x054 |
0x0104 2054 |
|
RW |
32 |
0x2218 4418 |
0x058 |
0x0104 2058 |
|
RW |
32 |
0x0000 0230 |
0x05C |
0x0104 205C |
|
RW |
32 |
0x0000 0000 |
0x070 |
0x0104 2070 |
|
RW |
32 |
0x0000 0070 |
0x074 |
0x0104 2074 |
|
RW |
32 |
0x0000 0006 |
0x078 |
0x0104 2078 |
|
RW |
32 |
0x0000 0000 |
0x07C |
0x0104 207C |
|
RW |
32 |
0x0000 8A10 |
0x080 |
0x0104 2080 |
|
RO |
32 |
0x0000 0000 |
0x084 |
0x0104 2084 |
|
RW |
32 |
0x0000 0000 |
0x088 |
0x0104 2088 |
|
RW |
32 |
0x0000 0000 |
0x08C |
0x0104 208C |
|
RW |
32 |
0x0000 7200 |
0x090 |
0x0104 2090 |
|
RW |
32 |
0xE000 0000 |
0x094 |
0x0104 2094 |
|
RW |
32 |
0x0000 0000 |
0x098 |
0x0104 2098 |
|
RW |
32 |
0x0100 0000 |
0x09C |
0x0104 209C |
|
RW |
32 |
0x0000 0000 |
0x0A0 |
0x0104 20A0 |
|
RW |
32 |
0x001B 3423 |
0x0A4 |
0x0104 20A4 |
|
RW |
32 |
0x0023 2C27 |
0x0A8 |
0x0104 20A8 |
|
RW |
32 |
0x001B 1B1B |
0x0AC |
0x0104 20AC |
|
RW |
32 |
0x001B 1B14 |
0x0B0 |
0x0104 20B0 |
|
RW |
32 |
0x0024 0C0A |
0x0B4 |
0x0104 20B4 |
|
RW |
32 |
0x1B38 3B38 |
0x0B8 |
0x0104 20B8 |
|
RW |
32 |
0x0000 0100 |
0x0C0 |
0x0104 20C0 |
|
RW |
32 |
0x6410 0702 |
0x0D0 |
0x0104 20D0 |
|
RW |
32 |
0x0103 4018 |
0x0D4 |
0x0104 20D4 |
|
RW |
32 |
0x0080 0000 |
0x0D8 |
0x0104 20D8 |
|
RW |
32 |
0x0000 0000 |
0x0DC |
0x0104 20DC |
|
RW |
32 |
0x0000 0000 |
0x0E0 |
0x0104 20E0 |
|
RO |
32 |
0x0000 0000 |
0x0E4 |
0x0104 20E4 |
|
RO |
32 |
0x0000 0000 |
0x0E8 |
0x0104 20E8 |
|
RO |
32 |
0x0000 0000 |
0x0EC |
0x0104 20EC |
|
RO |
32 |
0x0000 0000 |
0x0F0 |
0x0104 20F0 |
|
RO |
32 |
0x0000 0000 |
0x0F4 |
0x0104 20F4 |
|
RO |
32 |
0x0000 0000 |
0x0F8 |
0x0104 20F8 |
|
RO |
32 |
0x0000 0000 |
0x0FC |
0x0104 20FC |
|
RO |
32 |
0x0000 0000 |
0x100 |
0x0104 2100 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0104 4000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x0104 4004 |
|
RW |
32 |
0x0000 0015 |
0x008 |
0x0104 4008 |
|
RW |
32 |
0x0000 0000 |
0x00C |
0x0104 400C |
|
RW |
32 |
0x0000 0015 |
0x010 |
0x0104 4010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x0104 4014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x0104 4018 |
|
RW |
32 |
0x0000 0000 |
0x020 |
0x0104 4020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x0104 4024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x0104 4028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
0x0104 402C |
|
RW |
32 |
0x0000 00A7 |
0x030 |
0x0104 4030 |
|
RW |
32 |
0x0000 00AC |
0x034 |
0x0104 4034 |
|
RW |
32 |
0x0000 00C8 |
0x038 |
0x0104 4038 |
|
RW |
32 |
0x0000 0008 |
0x03C |
0x0104 403C |
|
RW |
32 |
0x0000 2219 |
0x040 |
0x0104 4040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
0x0104 4044 |
|
RW |
32 |
0x0000 003C |
0x048 |
0x0104 4048 |
|
RW |
32 |
0x0000 002F |
0x04C |
0x0104 404C |
|
RW |
32 |
0x0000 0000 |
0x050 |
0x0104 4050 |
|
RW |
32 |
0x0232 2219 |
0x054 |
0x0104 4054 |
|
RW |
32 |
0x2218 4418 |
0x058 |
0x0104 4058 |
|
RW |
32 |
0x0000 0230 |
0x05C |
0x0104 405C |
|
RW |
32 |
0x0000 0000 |
0x070 |
0x0104 4070 |
|
RW |
32 |
0x0000 0070 |
0x074 |
0x0104 4074 |
|
RW |
32 |
0x0000 0006 |
0x078 |
0x0104 4078 |
|
RW |
32 |
0x0000 0000 |
0x07C |
0x0104 407C |
|
RW |
32 |
0x0000 8A10 |
0x080 |
0x0104 4080 |
|
RO |
32 |
0x0000 0000 |
0x084 |
0x0104 4084 |
|
RW |
32 |
0x0000 0000 |
0x088 |
0x0104 4088 |
|
RW |
32 |
0x0000 0000 |
0x08C |
0x0104 408C |
|
RW |
32 |
0x0000 7200 |
0x090 |
0x0104 4090 |
|
RW |
32 |
0xE000 0000 |
0x094 |
0x0104 4094 |
|
RW |
32 |
0x0000 0000 |
0x098 |
0x0104 4098 |
|
RW |
32 |
0x0100 0000 |
0x09C |
0x0104 409C |
|
RW |
32 |
0x0000 0000 |
0x0A0 |
0x0104 40A0 |
|
RW |
32 |
0x001B 3423 |
0x0A4 |
0x0104 40A4 |
|
RW |
32 |
0x0023 2C27 |
0x0A8 |
0x0104 40A8 |
|
RW |
32 |
0x001B 1B1B |
0x0AC |
0x0104 40AC |
|
RW |
32 |
0x001B 1B14 |
0x0B0 |
0x0104 40B0 |
|
RW |
32 |
0x0024 0C0A |
0x0B4 |
0x0104 40B4 |
|
RW |
32 |
0x1B38 3B38 |
0x0B8 |
0x0104 40B8 |
|
RW |
32 |
0x0000 0100 |
0x0C0 |
0x0104 40C0 |
|
RW |
32 |
0x6410 0702 |
0x0D0 |
0x0104 40D0 |
|
RW |
32 |
0x0103 4018 |
0x0D4 |
0x0104 40D4 |
|
RW |
32 |
0x0080 0000 |
0x0D8 |
0x0104 40D8 |
|
RW |
32 |
0x0000 0000 |
0x0DC |
0x0104 40DC |
|
RW |
32 |
0x0000 0000 |
0x0E0 |
0x0104 40E0 |
|
RO |
32 |
0x0000 0000 |
0x0E4 |
0x0104 40E4 |
|
RO |
32 |
0x0000 0000 |
0x0E8 |
0x0104 40E8 |
|
RO |
32 |
0x0000 0000 |
0x0EC |
0x0104 40EC |
|
RO |
32 |
0x0000 0000 |
0x0F0 |
0x0104 40F0 |
|
RO |
32 |
0x0000 0000 |
0x0F4 |
0x0104 40F4 |
|
RO |
32 |
0x0000 0000 |
0x0F8 |
0x0104 40F8 |
|
RO |
32 |
0x0000 0000 |
0x0FC |
0x0104 40FC |
|
RO |
32 |
0x0000 0000 |
0x100 |
0x0104 4100 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0104 8000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x0104 8004 |
|
RW |
32 |
0x0000 0015 |
0x008 |
0x0104 8008 |
|
RW |
32 |
0x0000 0000 |
0x00C |
0x0104 800C |
|
RW |
32 |
0x0000 0015 |
0x010 |
0x0104 8010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x0104 8014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x0104 8018 |
|
RW |
32 |
0x0000 0000 |
0x020 |
0x0104 8020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x0104 8024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x0104 8028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
0x0104 802C |
|
RW |
32 |
0x0000 00A7 |
0x030 |
0x0104 8030 |
|
RW |
32 |
0x0000 00AC |
0x034 |
0x0104 8034 |
|
RW |
32 |
0x0000 00C8 |
0x038 |
0x0104 8038 |
|
RW |
32 |
0x0000 0008 |
0x03C |
0x0104 803C |
|
RW |
32 |
0x0000 2219 |
0x040 |
0x0104 8040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
0x0104 8044 |
|
RW |
32 |
0x0000 003C |
0x048 |
0x0104 8048 |
|
RW |
32 |
0x0000 002F |
0x04C |
0x0104 804C |
|
RW |
32 |
0x0000 0000 |
0x050 |
0x0104 8050 |
|
RW |
32 |
0x0232 2219 |
0x054 |
0x0104 8054 |
|
RW |
32 |
0x2218 4418 |
0x058 |
0x0104 8058 |
|
RW |
32 |
0x0000 0230 |
0x05C |
0x0104 805C |
|
RW |
32 |
0x0000 0000 |
0x070 |
0x0104 8070 |
|
RW |
32 |
0x0000 0070 |
0x074 |
0x0104 8074 |
|
RW |
32 |
0x0000 0006 |
0x078 |
0x0104 8078 |
|
RW |
32 |
0x0000 0000 |
0x07C |
0x0104 807C |
|
RW |
32 |
0x0000 8A10 |
0x080 |
0x0104 8080 |
|
RO |
32 |
0x0000 0000 |
0x084 |
0x0104 8084 |
|
RW |
32 |
0x0000 0000 |
0x088 |
0x0104 8088 |
|
RW |
32 |
0x0000 0000 |
0x08C |
0x0104 808C |
|
RW |
32 |
0x0000 7200 |
0x090 |
0x0104 8090 |
|
RW |
32 |
0xE000 0000 |
0x094 |
0x0104 8094 |
|
RW |
32 |
0x0000 0000 |
0x098 |
0x0104 8098 |
|
RW |
32 |
0x0100 0000 |
0x09C |
0x0104 809C |
|
RW |
32 |
0x0000 0000 |
0x0A0 |
0x0104 80A0 |
|
RW |
32 |
0x001B 3423 |
0x0A4 |
0x0104 80A4 |
|
RW |
32 |
0x0023 2C27 |
0x0A8 |
0x0104 80A8 |
|
RW |
32 |
0x001B 1B1B |
0x0AC |
0x0104 80AC |
|
RW |
32 |
0x001B 1B14 |
0x0B0 |
0x0104 80B0 |
|
RW |
32 |
0x0024 0C0A |
0x0B4 |
0x0104 80B4 |
|
RW |
32 |
0x1B38 3B38 |
0x0B8 |
0x0104 80B8 |
|
RW |
32 |
0x0000 0100 |
0x0C0 |
0x0104 80C0 |
|
RW |
32 |
0x6410 0702 |
0x0D0 |
0x0104 80D0 |
|
RW |
32 |
0x0103 4018 |
0x0D4 |
0x0104 80D4 |
|
RW |
32 |
0x0080 0000 |
0x0D8 |
0x0104 80D8 |
|
RW |
32 |
0x0000 0000 |
0x0DC |
0x0104 80DC |
|
RW |
32 |
0x0000 0000 |
0x0E0 |
0x0104 80E0 |
|
RO |
32 |
0x0000 0000 |
0x0E4 |
0x0104 80E4 |
|
RO |
32 |
0x0000 0000 |
0x0E8 |
0x0104 80E8 |
|
RO |
32 |
0x0000 0000 |
0x0EC |
0x0104 80EC |
|
RO |
32 |
0x0000 0000 |
0x0F0 |
0x0104 80F0 |
|
RO |
32 |
0x0000 0000 |
0x0F4 |
0x0104 80F4 |
|
RO |
32 |
0x0000 0000 |
0x0F8 |
0x0104 80F8 |
|
RO |
32 |
0x0000 0000 |
0x0FC |
0x0104 80FC |
|
RO |
32 |
0x0000 0000 |
0x100 |
0x0104 8100 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0108 1000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x0108 1004 |
|
RW |
32 |
0x0000 0015 |
0x008 |
0x0108 1008 |
|
RW |
32 |
0x0000 0000 |
0x00C |
0x0108 100C |
|
RW |
32 |
0x0000 0015 |
0x010 |
0x0108 1010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x0108 1014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x0108 1018 |
|
RW |
32 |
0x0000 0000 |
0x020 |
0x0108 1020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x0108 1024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x0108 1028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
0x0108 102C |
|
RW |
32 |
0x0000 00A7 |
0x030 |
0x0108 1030 |
|
RW |
32 |
0x0000 00AC |
0x034 |
0x0108 1034 |
|
RW |
32 |
0x0000 00C8 |
0x038 |
0x0108 1038 |
|
RW |
32 |
0x0000 0008 |
0x03C |
0x0108 103C |
|
RW |
32 |
0x0000 2219 |
0x040 |
0x0108 1040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
0x0108 1044 |
|
RW |
32 |
0x0000 003C |
0x048 |
0x0108 1048 |
|
RW |
32 |
0x0000 002F |
0x04C |
0x0108 104C |
|
RW |
32 |
0x0000 0000 |
0x050 |
0x0108 1050 |
|
RW |
32 |
0x0232 2219 |
0x054 |
0x0108 1054 |
|
RW |
32 |
0x2218 4418 |
0x058 |
0x0108 1058 |
|
RW |
32 |
0x0000 0230 |
0x05C |
0x0108 105C |
|
RW |
32 |
0x0000 0000 |
0x070 |
0x0108 1070 |
|
RW |
32 |
0x0000 0070 |
0x074 |
0x0108 1074 |
|
RW |
32 |
0x0000 0006 |
0x078 |
0x0108 1078 |
|
RW |
32 |
0x0000 0000 |
0x07C |
0x0108 107C |
|
RW |
32 |
0x0000 8A10 |
0x080 |
0x0108 1080 |
|
RO |
32 |
0x0000 0000 |
0x084 |
0x0108 1084 |
|
RW |
32 |
0x0000 0000 |
0x088 |
0x0108 1088 |
|
RW |
32 |
0x0000 0000 |
0x08C |
0x0108 108C |
|
RW |
32 |
0x0000 7200 |
0x090 |
0x0108 1090 |
|
RW |
32 |
0xE000 0000 |
0x094 |
0x0108 1094 |
|
RW |
32 |
0x0000 0000 |
0x098 |
0x0108 1098 |
|
RW |
32 |
0x0100 0000 |
0x09C |
0x0108 109C |
|
RW |
32 |
0x0000 0000 |
0x0A0 |
0x0108 10A0 |
|
RW |
32 |
0x001B 3423 |
0x0A4 |
0x0108 10A4 |
|
RW |
32 |
0x0023 2C27 |
0x0A8 |
0x0108 10A8 |
|
RW |
32 |
0x001B 1B1B |
0x0AC |
0x0108 10AC |
|
RW |
32 |
0x001B 1B14 |
0x0B0 |
0x0108 10B0 |
|
RW |
32 |
0x0024 0C0A |
0x0B4 |
0x0108 10B4 |
|
RW |
32 |
0x1B38 3B38 |
0x0B8 |
0x0108 10B8 |
|
RW |
32 |
0x0000 0100 |
0x0C0 |
0x0108 10C0 |
|
RW |
32 |
0x6410 0702 |
0x0D0 |
0x0108 10D0 |
|
RW |
32 |
0x0103 4018 |
0x0D4 |
0x0108 10D4 |
|
RW |
32 |
0x0080 0000 |
0x0D8 |
0x0108 10D8 |
|
RW |
32 |
0x0000 0000 |
0x0DC |
0x0108 10DC |
|
RW |
32 |
0x0000 0000 |
0x0E0 |
0x0108 10E0 |
|
RO |
32 |
0x0000 0000 |
0x0E4 |
0x0108 10E4 |
|
RO |
32 |
0x0000 0000 |
0x0E8 |
0x0108 10E8 |
|
RO |
32 |
0x0000 0000 |
0x0EC |
0x0108 10EC |
|
RO |
32 |
0x0000 0000 |
0x0F0 |
0x0108 10F0 |
|
RO |
32 |
0x0000 0000 |
0x0F4 |
0x0108 10F4 |
|
RO |
32 |
0x0000 0000 |
0x0F8 |
0x0108 10F8 |
|
RO |
32 |
0x0000 0000 |
0x0FC |
0x0108 10FC |
|
RO |
32 |
0x0000 0000 |
0x100 |
0x0108 1100 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0108 2000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x0108 2004 |
|
RW |
32 |
0x0000 0015 |
0x008 |
0x0108 2008 |
|
RW |
32 |
0x0000 0000 |
0x00C |
0x0108 200C |
|
RW |
32 |
0x0000 0015 |
0x010 |
0x0108 2010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x0108 2014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x0108 2018 |
|
RW |
32 |
0x0000 0000 |
0x020 |
0x0108 2020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x0108 2024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x0108 2028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
0x0108 202C |
|
RW |
32 |
0x0000 00A7 |
0x030 |
0x0108 2030 |
|
RW |
32 |
0x0000 00AC |
0x034 |
0x0108 2034 |
|
RW |
32 |
0x0000 00C8 |
0x038 |
0x0108 2038 |
|
RW |
32 |
0x0000 0008 |
0x03C |
0x0108 203C |
|
RW |
32 |
0x0000 2219 |
0x040 |
0x0108 2040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
0x0108 2044 |
|
RW |
32 |
0x0000 003C |
0x048 |
0x0108 2048 |
|
RW |
32 |
0x0000 002F |
0x04C |
0x0108 204C |
|
RW |
32 |
0x0000 0000 |
0x050 |
0x0108 2050 |
|
RW |
32 |
0x0232 2219 |
0x054 |
0x0108 2054 |
|
RW |
32 |
0x2218 4418 |
0x058 |
0x0108 2058 |
|
RW |
32 |
0x0000 0230 |
0x05C |
0x0108 205C |
|
RW |
32 |
0x0000 0000 |
0x070 |
0x0108 2070 |
|
RW |
32 |
0x0000 0070 |
0x074 |
0x0108 2074 |
|
RW |
32 |
0x0000 0006 |
0x078 |
0x0108 2078 |
|
RW |
32 |
0x0000 0000 |
0x07C |
0x0108 207C |
|
RW |
32 |
0x0000 8A10 |
0x080 |
0x0108 2080 |
|
RO |
32 |
0x0000 0000 |
0x084 |
0x0108 2084 |
|
RW |
32 |
0x0000 0000 |
0x088 |
0x0108 2088 |
|
RW |
32 |
0x0000 0000 |
0x08C |
0x0108 208C |
|
RW |
32 |
0x0000 7200 |
0x090 |
0x0108 2090 |
|
RW |
32 |
0xE000 0000 |
0x094 |
0x0108 2094 |
|
RW |
32 |
0x0000 0000 |
0x098 |
0x0108 2098 |
|
RW |
32 |
0x0100 0000 |
0x09C |
0x0108 209C |
|
RW |
32 |
0x0000 0000 |
0x0A0 |
0x0108 20A0 |
|
RW |
32 |
0x001B 3423 |
0x0A4 |
0x0108 20A4 |
|
RW |
32 |
0x0023 2C27 |
0x0A8 |
0x0108 20A8 |
|
RW |
32 |
0x001B 1B1B |
0x0AC |
0x0108 20AC |
|
RW |
32 |
0x001B 1B14 |
0x0B0 |
0x0108 20B0 |
|
RW |
32 |
0x0024 0C0A |
0x0B4 |
0x0108 20B4 |
|
RW |
32 |
0x1B38 3B38 |
0x0B8 |
0x0108 20B8 |
|
RW |
32 |
0x0000 0100 |
0x0C0 |
0x0108 20C0 |
|
RW |
32 |
0x6410 0702 |
0x0D0 |
0x0108 20D0 |
|
RW |
32 |
0x0103 4018 |
0x0D4 |
0x0108 20D4 |
|
RW |
32 |
0x0080 0000 |
0x0D8 |
0x0108 20D8 |
|
RW |
32 |
0x0000 0000 |
0x0DC |
0x0108 20DC |
|
RW |
32 |
0x0000 0000 |
0x0E0 |
0x0108 20E0 |
|
RO |
32 |
0x0000 0000 |
0x0E4 |
0x0108 20E4 |
|
RO |
32 |
0x0000 0000 |
0x0E8 |
0x0108 20E8 |
|
RO |
32 |
0x0000 0000 |
0x0EC |
0x0108 20EC |
|
RO |
32 |
0x0000 0000 |
0x0F0 |
0x0108 20F0 |
|
RO |
32 |
0x0000 0000 |
0x0F4 |
0x0108 20F4 |
|
RO |
32 |
0x0000 0000 |
0x0F8 |
0x0108 20F8 |
|
RO |
32 |
0x0000 0000 |
0x0FC |
0x0108 20FC |
|
RO |
32 |
0x0000 0000 |
0x100 |
0x0108 2100 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0108 4000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x0108 4004 |
|
RW |
32 |
0x0000 0015 |
0x008 |
0x0108 4008 |
|
RW |
32 |
0x0000 0000 |
0x00C |
0x0108 400C |
|
RW |
32 |
0x0000 0015 |
0x010 |
0x0108 4010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x0108 4014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x0108 4018 |
|
RW |
32 |
0x0000 0000 |
0x020 |
0x0108 4020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x0108 4024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x0108 4028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
0x0108 402C |
|
RW |
32 |
0x0000 00A7 |
0x030 |
0x0108 4030 |
|
RW |
32 |
0x0000 00AC |
0x034 |
0x0108 4034 |
|
RW |
32 |
0x0000 00C8 |
0x038 |
0x0108 4038 |
|
RW |
32 |
0x0000 0008 |
0x03C |
0x0108 403C |
|
RW |
32 |
0x0000 2219 |
0x040 |
0x0108 4040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
0x0108 4044 |
|
RW |
32 |
0x0000 003C |
0x048 |
0x0108 4048 |
|
RW |
32 |
0x0000 002F |
0x04C |
0x0108 404C |
|
RW |
32 |
0x0000 0000 |
0x050 |
0x0108 4050 |
|
RW |
32 |
0x0232 2219 |
0x054 |
0x0108 4054 |
|
RW |
32 |
0x2218 4418 |
0x058 |
0x0108 4058 |
|
RW |
32 |
0x0000 0230 |
0x05C |
0x0108 405C |
|
RW |
32 |
0x0000 0000 |
0x070 |
0x0108 4070 |
|
RW |
32 |
0x0000 0070 |
0x074 |
0x0108 4074 |
|
RW |
32 |
0x0000 0006 |
0x078 |
0x0108 4078 |
|
RW |
32 |
0x0000 0000 |
0x07C |
0x0108 407C |
|
RW |
32 |
0x0000 8A10 |
0x080 |
0x0108 4080 |
|
RO |
32 |
0x0000 0000 |
0x084 |
0x0108 4084 |
|
RW |
32 |
0x0000 0000 |
0x088 |
0x0108 4088 |
|
RW |
32 |
0x0000 0000 |
0x08C |
0x0108 408C |
|
RW |
32 |
0x0000 7200 |
0x090 |
0x0108 4090 |
|
RW |
32 |
0xE000 0000 |
0x094 |
0x0108 4094 |
|
RW |
32 |
0x0000 0000 |
0x098 |
0x0108 4098 |
|
RW |
32 |
0x0100 0000 |
0x09C |
0x0108 409C |
|
RW |
32 |
0x0000 0000 |
0x0A0 |
0x0108 40A0 |
|
RW |
32 |
0x001B 3423 |
0x0A4 |
0x0108 40A4 |
|
RW |
32 |
0x0023 2C27 |
0x0A8 |
0x0108 40A8 |
|
RW |
32 |
0x001B 1B1B |
0x0AC |
0x0108 40AC |
|
RW |
32 |
0x001B 1B14 |
0x0B0 |
0x0108 40B0 |
|
RW |
32 |
0x0024 0C0A |
0x0B4 |
0x0108 40B4 |
|
RW |
32 |
0x1B38 3B38 |
0x0B8 |
0x0108 40B8 |
|
RW |
32 |
0x0000 0100 |
0x0C0 |
0x0108 40C0 |
|
RW |
32 |
0x6410 0702 |
0x0D0 |
0x0108 40D0 |
|
RW |
32 |
0x0103 4018 |
0x0D4 |
0x0108 40D4 |
|
RW |
32 |
0x0080 0000 |
0x0D8 |
0x0108 40D8 |
|
RW |
32 |
0x0000 0000 |
0x0DC |
0x0108 40DC |
|
RW |
32 |
0x0000 0000 |
0x0E0 |
0x0108 40E0 |
|
RO |
32 |
0x0000 0000 |
0x0E4 |
0x0108 40E4 |
|
RO |
32 |
0x0000 0000 |
0x0E8 |
0x0108 40E8 |
|
RO |
32 |
0x0000 0000 |
0x0EC |
0x0108 40EC |
|
RO |
32 |
0x0000 0000 |
0x0F0 |
0x0108 40F0 |
|
RO |
32 |
0x0000 0000 |
0x0F4 |
0x0108 40F4 |
|
RO |
32 |
0x0000 0000 |
0x0F8 |
0x0108 40F8 |
|
RO |
32 |
0x0000 0000 |
0x0FC |
0x0108 40FC |
|
RO |
32 |
0x0000 0000 |
0x100 |
0x0108 4100 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0108 8000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x0108 8004 |
|
RW |
32 |
0x0000 0015 |
0x008 |
0x0108 8008 |
|
RW |
32 |
0x0000 0000 |
0x00C |
0x0108 800C |
|
RW |
32 |
0x0000 0015 |
0x010 |
0x0108 8010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x0108 8014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x0108 8018 |
|
RW |
32 |
0x0000 0000 |
0x020 |
0x0108 8020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x0108 8024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x0108 8028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
0x0108 802C |
|
RW |
32 |
0x0000 00A7 |
0x030 |
0x0108 8030 |
|
RW |
32 |
0x0000 00AC |
0x034 |
0x0108 8034 |
|
RW |
32 |
0x0000 00C8 |
0x038 |
0x0108 8038 |
|
RW |
32 |
0x0000 0008 |
0x03C |
0x0108 803C |
|
RW |
32 |
0x0000 2219 |
0x040 |
0x0108 8040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
0x0108 8044 |
|
RW |
32 |
0x0000 003C |
0x048 |
0x0108 8048 |
|
RW |
32 |
0x0000 002F |
0x04C |
0x0108 804C |
|
RW |
32 |
0x0000 0000 |
0x050 |
0x0108 8050 |
|
RW |
32 |
0x0232 2219 |
0x054 |
0x0108 8054 |
|
RW |
32 |
0x2218 4418 |
0x058 |
0x0108 8058 |
|
RW |
32 |
0x0000 0230 |
0x05C |
0x0108 805C |
|
RW |
32 |
0x0000 0000 |
0x070 |
0x0108 8070 |
|
RW |
32 |
0x0000 0070 |
0x074 |
0x0108 8074 |
|
RW |
32 |
0x0000 0006 |
0x078 |
0x0108 8078 |
|
RW |
32 |
0x0000 0000 |
0x07C |
0x0108 807C |
|
RW |
32 |
0x0000 8A10 |
0x080 |
0x0108 8080 |
|
RO |
32 |
0x0000 0000 |
0x084 |
0x0108 8084 |
|
RW |
32 |
0x0000 0000 |
0x088 |
0x0108 8088 |
|
RW |
32 |
0x0000 0000 |
0x08C |
0x0108 808C |
|
RW |
32 |
0x0000 7200 |
0x090 |
0x0108 8090 |
|
RW |
32 |
0xE000 0000 |
0x094 |
0x0108 8094 |
|
RW |
32 |
0x0000 0000 |
0x098 |
0x0108 8098 |
|
RW |
32 |
0x0100 0000 |
0x09C |
0x0108 809C |
|
RW |
32 |
0x0000 0000 |
0x0A0 |
0x0108 80A0 |
|
RW |
32 |
0x001B 3423 |
0x0A4 |
0x0108 80A4 |
|
RW |
32 |
0x0023 2C27 |
0x0A8 |
0x0108 80A8 |
|
RW |
32 |
0x001B 1B1B |
0x0AC |
0x0108 80AC |
|
RW |
32 |
0x001B 1B14 |
0x0B0 |
0x0108 80B0 |
|
RW |
32 |
0x0024 0C0A |
0x0B4 |
0x0108 80B4 |
|
RW |
32 |
0x1B38 3B38 |
0x0B8 |
0x0108 80B8 |
|
RW |
32 |
0x0000 0100 |
0x0C0 |
0x0108 80C0 |
|
RW |
32 |
0x6410 0702 |
0x0D0 |
0x0108 80D0 |
|
RW |
32 |
0x0103 4018 |
0x0D4 |
0x0108 80D4 |
|
RW |
32 |
0x0080 0000 |
0x0D8 |
0x0108 80D8 |
|
RW |
32 |
0x0000 0000 |
0x0DC |
0x0108 80DC |
|
RW |
32 |
0x0000 0000 |
0x0E0 |
0x0108 80E0 |
|
RO |
32 |
0x0000 0000 |
0x0E4 |
0x0108 80E4 |
|
RO |
32 |
0x0000 0000 |
0x0E8 |
0x0108 80E8 |
|
RO |
32 |
0x0000 0000 |
0x0EC |
0x0108 80EC |
|
RO |
32 |
0x0000 0000 |
0x0F0 |
0x0108 80F0 |
|
RO |
32 |
0x0000 0000 |
0x0F4 |
0x0108 80F4 |
|
RO |
32 |
0x0000 0000 |
0x0F8 |
0x0108 80F8 |
|
RO |
32 |
0x0000 0000 |
0x0FC |
0x0108 80FC |
|
RO |
32 |
0x0000 0000 |
0x100 |
0x0108 8100 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0110 1000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x0110 1004 |
|
RW |
32 |
0x0000 0015 |
0x008 |
0x0110 1008 |
|
RW |
32 |
0x0000 0000 |
0x00C |
0x0110 100C |
|
RW |
32 |
0x0000 0015 |
0x010 |
0x0110 1010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x0110 1014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x0110 1018 |
|
RW |
32 |
0x0000 0000 |
0x020 |
0x0110 1020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x0110 1024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x0110 1028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
0x0110 102C |
|
RW |
32 |
0x0000 00A7 |
0x030 |
0x0110 1030 |
|
RW |
32 |
0x0000 00AC |
0x034 |
0x0110 1034 |
|
RW |
32 |
0x0000 00C8 |
0x038 |
0x0110 1038 |
|
RW |
32 |
0x0000 0008 |
0x03C |
0x0110 103C |
|
RW |
32 |
0x0000 2219 |
0x040 |
0x0110 1040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
0x0110 1044 |
|
RW |
32 |
0x0000 003C |
0x048 |
0x0110 1048 |
|
RW |
32 |
0x0000 002F |
0x04C |
0x0110 104C |
|
RW |
32 |
0x0000 0000 |
0x050 |
0x0110 1050 |
|
RW |
32 |
0x0232 2219 |
0x054 |
0x0110 1054 |
|
RW |
32 |
0x2218 4418 |
0x058 |
0x0110 1058 |
|
RW |
32 |
0x0000 0230 |
0x05C |
0x0110 105C |
|
RW |
32 |
0x0000 0000 |
0x070 |
0x0110 1070 |
|
RW |
32 |
0x0000 0070 |
0x074 |
0x0110 1074 |
|
RW |
32 |
0x0000 0006 |
0x078 |
0x0110 1078 |
|
RW |
32 |
0x0000 0000 |
0x07C |
0x0110 107C |
|
RW |
32 |
0x0000 8A10 |
0x080 |
0x0110 1080 |
|
RO |
32 |
0x0000 0000 |
0x084 |
0x0110 1084 |
|
RW |
32 |
0x0000 0000 |
0x088 |
0x0110 1088 |
|
RW |
32 |
0x0000 0000 |
0x08C |
0x0110 108C |
|
RW |
32 |
0x0000 7200 |
0x090 |
0x0110 1090 |
|
RW |
32 |
0xE000 0000 |
0x094 |
0x0110 1094 |
|
RW |
32 |
0x0000 0000 |
0x098 |
0x0110 1098 |
|
RW |
32 |
0x0100 0000 |
0x09C |
0x0110 109C |
|
RW |
32 |
0x0000 0000 |
0x0A0 |
0x0110 10A0 |
|
RW |
32 |
0x001B 3423 |
0x0A4 |
0x0110 10A4 |
|
RW |
32 |
0x0023 2C27 |
0x0A8 |
0x0110 10A8 |
|
RW |
32 |
0x001B 1B1B |
0x0AC |
0x0110 10AC |
|
RW |
32 |
0x001B 1B14 |
0x0B0 |
0x0110 10B0 |
|
RW |
32 |
0x0024 0C0A |
0x0B4 |
0x0110 10B4 |
|
RW |
32 |
0x1B38 3B38 |
0x0B8 |
0x0110 10B8 |
|
RW |
32 |
0x0000 0100 |
0x0C0 |
0x0110 10C0 |
|
RW |
32 |
0x6410 0702 |
0x0D0 |
0x0110 10D0 |
|
RW |
32 |
0x0103 4018 |
0x0D4 |
0x0110 10D4 |
|
RW |
32 |
0x0080 0000 |
0x0D8 |
0x0110 10D8 |
|
RW |
32 |
0x0000 0000 |
0x0DC |
0x0110 10DC |
|
RW |
32 |
0x0000 0000 |
0x0E0 |
0x0110 10E0 |
|
RO |
32 |
0x0000 0000 |
0x0E4 |
0x0110 10E4 |
|
RO |
32 |
0x0000 0000 |
0x0E8 |
0x0110 10E8 |
|
RO |
32 |
0x0000 0000 |
0x0EC |
0x0110 10EC |
|
RO |
32 |
0x0000 0000 |
0x0F0 |
0x0110 10F0 |
|
RO |
32 |
0x0000 0000 |
0x0F4 |
0x0110 10F4 |
|
RO |
32 |
0x0000 0000 |
0x0F8 |
0x0110 10F8 |
|
RO |
32 |
0x0000 0000 |
0x0FC |
0x0110 10FC |
|
RO |
32 |
0x0000 0000 |
0x100 |
0x0110 1100 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0110 2000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x0110 2004 |
|
RW |
32 |
0x0000 0015 |
0x008 |
0x0110 2008 |
|
RW |
32 |
0x0000 0000 |
0x00C |
0x0110 200C |
|
RW |
32 |
0x0000 0015 |
0x010 |
0x0110 2010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x0110 2014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x0110 2018 |
|
RW |
32 |
0x0000 0000 |
0x020 |
0x0110 2020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x0110 2024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x0110 2028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
0x0110 202C |
|
RW |
32 |
0x0000 00A7 |
0x030 |
0x0110 2030 |
|
RW |
32 |
0x0000 00AC |
0x034 |
0x0110 2034 |
|
RW |
32 |
0x0000 00C8 |
0x038 |
0x0110 2038 |
|
RW |
32 |
0x0000 0008 |
0x03C |
0x0110 203C |
|
RW |
32 |
0x0000 2219 |
0x040 |
0x0110 2040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
0x0110 2044 |
|
RW |
32 |
0x0000 003C |
0x048 |
0x0110 2048 |
|
RW |
32 |
0x0000 002F |
0x04C |
0x0110 204C |
|
RW |
32 |
0x0000 0000 |
0x050 |
0x0110 2050 |
|
RW |
32 |
0x0232 2219 |
0x054 |
0x0110 2054 |
|
RW |
32 |
0x2218 4418 |
0x058 |
0x0110 2058 |
|
RW |
32 |
0x0000 0230 |
0x05C |
0x0110 205C |
|
RW |
32 |
0x0000 0000 |
0x070 |
0x0110 2070 |
|
RW |
32 |
0x0000 0070 |
0x074 |
0x0110 2074 |
|
RW |
32 |
0x0000 0006 |
0x078 |
0x0110 2078 |
|
RW |
32 |
0x0000 0000 |
0x07C |
0x0110 207C |
|
RW |
32 |
0x0000 8A10 |
0x080 |
0x0110 2080 |
|
RO |
32 |
0x0000 0000 |
0x084 |
0x0110 2084 |
|
RW |
32 |
0x0000 0000 |
0x088 |
0x0110 2088 |
|
RW |
32 |
0x0000 0000 |
0x08C |
0x0110 208C |
|
RW |
32 |
0x0000 7200 |
0x090 |
0x0110 2090 |
|
RW |
32 |
0xE000 0000 |
0x094 |
0x0110 2094 |
|
RW |
32 |
0x0000 0000 |
0x098 |
0x0110 2098 |
|
RW |
32 |
0x0100 0000 |
0x09C |
0x0110 209C |
|
RW |
32 |
0x0000 0000 |
0x0A0 |
0x0110 20A0 |
|
RW |
32 |
0x001B 3423 |
0x0A4 |
0x0110 20A4 |
|
RW |
32 |
0x0023 2C27 |
0x0A8 |
0x0110 20A8 |
|
RW |
32 |
0x001B 1B1B |
0x0AC |
0x0110 20AC |
|
RW |
32 |
0x001B 1B14 |
0x0B0 |
0x0110 20B0 |
|
RW |
32 |
0x0024 0C0A |
0x0B4 |
0x0110 20B4 |
|
RW |
32 |
0x1B38 3B38 |
0x0B8 |
0x0110 20B8 |
|
RW |
32 |
0x0000 0100 |
0x0C0 |
0x0110 20C0 |
|
RW |
32 |
0x6410 0702 |
0x0D0 |
0x0110 20D0 |
|
RW |
32 |
0x0103 4018 |
0x0D4 |
0x0110 20D4 |
|
RW |
32 |
0x0080 0000 |
0x0D8 |
0x0110 20D8 |
|
RW |
32 |
0x0000 0000 |
0x0DC |
0x0110 20DC |
|
RW |
32 |
0x0000 0000 |
0x0E0 |
0x0110 20E0 |
|
RO |
32 |
0x0000 0000 |
0x0E4 |
0x0110 20E4 |
|
RO |
32 |
0x0000 0000 |
0x0E8 |
0x0110 20E8 |
|
RO |
32 |
0x0000 0000 |
0x0EC |
0x0110 20EC |
|
RO |
32 |
0x0000 0000 |
0x0F0 |
0x0110 20F0 |
|
RO |
32 |
0x0000 0000 |
0x0F4 |
0x0110 20F4 |
|
RO |
32 |
0x0000 0000 |
0x0F8 |
0x0110 20F8 |
|
RO |
32 |
0x0000 0000 |
0x0FC |
0x0110 20FC |
|
RO |
32 |
0x0000 0000 |
0x100 |
0x0110 2100 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0110 4000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x0110 4004 |
|
RW |
32 |
0x0000 0015 |
0x008 |
0x0110 4008 |
|
RW |
32 |
0x0000 0000 |
0x00C |
0x0110 400C |
|
RW |
32 |
0x0000 0015 |
0x010 |
0x0110 4010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x0110 4014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x0110 4018 |
|
RW |
32 |
0x0000 0000 |
0x020 |
0x0110 4020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x0110 4024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x0110 4028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
0x0110 402C |
|
RW |
32 |
0x0000 00A7 |
0x030 |
0x0110 4030 |
|
RW |
32 |
0x0000 00AC |
0x034 |
0x0110 4034 |
|
RW |
32 |
0x0000 00C8 |
0x038 |
0x0110 4038 |
|
RW |
32 |
0x0000 0008 |
0x03C |
0x0110 403C |
|
RW |
32 |
0x0000 2219 |
0x040 |
0x0110 4040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
0x0110 4044 |
|
RW |
32 |
0x0000 003C |
0x048 |
0x0110 4048 |
|
RW |
32 |
0x0000 002F |
0x04C |
0x0110 404C |
|
RW |
32 |
0x0000 0000 |
0x050 |
0x0110 4050 |
|
RW |
32 |
0x0232 2219 |
0x054 |
0x0110 4054 |
|
RW |
32 |
0x2218 4418 |
0x058 |
0x0110 4058 |
|
RW |
32 |
0x0000 0230 |
0x05C |
0x0110 405C |
|
RW |
32 |
0x0000 0000 |
0x070 |
0x0110 4070 |
|
RW |
32 |
0x0000 0070 |
0x074 |
0x0110 4074 |
|
RW |
32 |
0x0000 0006 |
0x078 |
0x0110 4078 |
|
RW |
32 |
0x0000 0000 |
0x07C |
0x0110 407C |
|
RW |
32 |
0x0000 8A10 |
0x080 |
0x0110 4080 |
|
RO |
32 |
0x0000 0000 |
0x084 |
0x0110 4084 |
|
RW |
32 |
0x0000 0000 |
0x088 |
0x0110 4088 |
|
RW |
32 |
0x0000 0000 |
0x08C |
0x0110 408C |
|
RW |
32 |
0x0000 7200 |
0x090 |
0x0110 4090 |
|
RW |
32 |
0xE000 0000 |
0x094 |
0x0110 4094 |
|
RW |
32 |
0x0000 0000 |
0x098 |
0x0110 4098 |
|
RW |
32 |
0x0100 0000 |
0x09C |
0x0110 409C |
|
RW |
32 |
0x0000 0000 |
0x0A0 |
0x0110 40A0 |
|
RW |
32 |
0x001B 3423 |
0x0A4 |
0x0110 40A4 |
|
RW |
32 |
0x0023 2C27 |
0x0A8 |
0x0110 40A8 |
|
RW |
32 |
0x001B 1B1B |
0x0AC |
0x0110 40AC |
|
RW |
32 |
0x001B 1B14 |
0x0B0 |
0x0110 40B0 |
|
RW |
32 |
0x0024 0C0A |
0x0B4 |
0x0110 40B4 |
|
RW |
32 |
0x1B38 3B38 |
0x0B8 |
0x0110 40B8 |
|
RW |
32 |
0x0000 0100 |
0x0C0 |
0x0110 40C0 |
|
RW |
32 |
0x6410 0702 |
0x0D0 |
0x0110 40D0 |
|
RW |
32 |
0x0103 4018 |
0x0D4 |
0x0110 40D4 |
|
RW |
32 |
0x0080 0000 |
0x0D8 |
0x0110 40D8 |
|
RW |
32 |
0x0000 0000 |
0x0DC |
0x0110 40DC |
|
RW |
32 |
0x0000 0000 |
0x0E0 |
0x0110 40E0 |
|
RO |
32 |
0x0000 0000 |
0x0E4 |
0x0110 40E4 |
|
RO |
32 |
0x0000 0000 |
0x0E8 |
0x0110 40E8 |
|
RO |
32 |
0x0000 0000 |
0x0EC |
0x0110 40EC |
|
RO |
32 |
0x0000 0000 |
0x0F0 |
0x0110 40F0 |
|
RO |
32 |
0x0000 0000 |
0x0F4 |
0x0110 40F4 |
|
RO |
32 |
0x0000 0000 |
0x0F8 |
0x0110 40F8 |
|
RO |
32 |
0x0000 0000 |
0x0FC |
0x0110 40FC |
|
RO |
32 |
0x0000 0000 |
0x100 |
0x0110 4100 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0110 8000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x0110 8004 |
|
RW |
32 |
0x0000 0015 |
0x008 |
0x0110 8008 |
|
RW |
32 |
0x0000 0000 |
0x00C |
0x0110 800C |
|
RW |
32 |
0x0000 0015 |
0x010 |
0x0110 8010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x0110 8014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x0110 8018 |
|
RW |
32 |
0x0000 0000 |
0x020 |
0x0110 8020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x0110 8024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x0110 8028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
0x0110 802C |
|
RW |
32 |
0x0000 00A7 |
0x030 |
0x0110 8030 |
|
RW |
32 |
0x0000 00AC |
0x034 |
0x0110 8034 |
|
RW |
32 |
0x0000 00C8 |
0x038 |
0x0110 8038 |
|
RW |
32 |
0x0000 0008 |
0x03C |
0x0110 803C |
|
RW |
32 |
0x0000 2219 |
0x040 |
0x0110 8040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
0x0110 8044 |
|
RW |
32 |
0x0000 003C |
0x048 |
0x0110 8048 |
|
RW |
32 |
0x0000 002F |
0x04C |
0x0110 804C |
|
RW |
32 |
0x0000 0000 |
0x050 |
0x0110 8050 |
|
RW |
32 |
0x0232 2219 |
0x054 |
0x0110 8054 |
|
RW |
32 |
0x2218 4418 |
0x058 |
0x0110 8058 |
|
RW |
32 |
0x0000 0230 |
0x05C |
0x0110 805C |
|
RW |
32 |
0x0000 0000 |
0x070 |
0x0110 8070 |
|
RW |
32 |
0x0000 0070 |
0x074 |
0x0110 8074 |
|
RW |
32 |
0x0000 0006 |
0x078 |
0x0110 8078 |
|
RW |
32 |
0x0000 0000 |
0x07C |
0x0110 807C |
|
RW |
32 |
0x0000 8A10 |
0x080 |
0x0110 8080 |
|
RO |
32 |
0x0000 0000 |
0x084 |
0x0110 8084 |
|
RW |
32 |
0x0000 0000 |
0x088 |
0x0110 8088 |
|
RW |
32 |
0x0000 0000 |
0x08C |
0x0110 808C |
|
RW |
32 |
0x0000 7200 |
0x090 |
0x0110 8090 |
|
RW |
32 |
0xE000 0000 |
0x094 |
0x0110 8094 |
|
RW |
32 |
0x0000 0000 |
0x098 |
0x0110 8098 |
|
RW |
32 |
0x0100 0000 |
0x09C |
0x0110 809C |
|
RW |
32 |
0x0000 0000 |
0x0A0 |
0x0110 80A0 |
|
RW |
32 |
0x001B 3423 |
0x0A4 |
0x0110 80A4 |
|
RW |
32 |
0x0023 2C27 |
0x0A8 |
0x0110 80A8 |
|
RW |
32 |
0x001B 1B1B |
0x0AC |
0x0110 80AC |
|
RW |
32 |
0x001B 1B14 |
0x0B0 |
0x0110 80B0 |
|
RW |
32 |
0x0024 0C0A |
0x0B4 |
0x0110 80B4 |
|
RW |
32 |
0x1B38 3B38 |
0x0B8 |
0x0110 80B8 |
|
RW |
32 |
0x0000 0100 |
0x0C0 |
0x0110 80C0 |
|
RW |
32 |
0x6410 0702 |
0x0D0 |
0x0110 80D0 |
|
RW |
32 |
0x0103 4018 |
0x0D4 |
0x0110 80D4 |
|
RW |
32 |
0x0080 0000 |
0x0D8 |
0x0110 80D8 |
|
RW |
32 |
0x0000 0000 |
0x0DC |
0x0110 80DC |
|
RW |
32 |
0x0000 0000 |
0x0E0 |
0x0110 80E0 |
|
RO |
32 |
0x0000 0000 |
0x0E4 |
0x0110 80E4 |
|
RO |
32 |
0x0000 0000 |
0x0E8 |
0x0110 80E8 |
|
RO |
32 |
0x0000 0000 |
0x0EC |
0x0110 80EC |
|
RO |
32 |
0x0000 0000 |
0x0F0 |
0x0110 80F0 |
|
RO |
32 |
0x0000 0000 |
0x0F4 |
0x0110 80F4 |
|
RO |
32 |
0x0000 0000 |
0x0F8 |
0x0110 80F8 |
|
RO |
32 |
0x0000 0000 |
0x0FC |
0x0110 80FC |
|
RO |
32 |
0x0000 0000 |
0x100 |
0x0110 8100 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0120 1000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x0120 1004 |
|
RW |
32 |
0x0000 0015 |
0x008 |
0x0120 1008 |
|
RW |
32 |
0x0000 0000 |
0x00C |
0x0120 100C |
|
RW |
32 |
0x0000 0015 |
0x010 |
0x0120 1010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x0120 1014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x0120 1018 |
|
RW |
32 |
0x0000 0000 |
0x020 |
0x0120 1020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x0120 1024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x0120 1028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
0x0120 102C |
|
RW |
32 |
0x0000 00A7 |
0x030 |
0x0120 1030 |
|
RW |
32 |
0x0000 00AC |
0x034 |
0x0120 1034 |
|
RW |
32 |
0x0000 00C8 |
0x038 |
0x0120 1038 |
|
RW |
32 |
0x0000 0008 |
0x03C |
0x0120 103C |
|
RW |
32 |
0x0000 2219 |
0x040 |
0x0120 1040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
0x0120 1044 |
|
RW |
32 |
0x0000 003C |
0x048 |
0x0120 1048 |
|
RW |
32 |
0x0000 002F |
0x04C |
0x0120 104C |
|
RW |
32 |
0x0000 0000 |
0x050 |
0x0120 1050 |
|
RW |
32 |
0x0232 2219 |
0x054 |
0x0120 1054 |
|
RW |
32 |
0x2218 4418 |
0x058 |
0x0120 1058 |
|
RW |
32 |
0x0000 0230 |
0x05C |
0x0120 105C |
|
RW |
32 |
0x0000 0000 |
0x070 |
0x0120 1070 |
|
RW |
32 |
0x0000 0070 |
0x074 |
0x0120 1074 |
|
RW |
32 |
0x0000 0006 |
0x078 |
0x0120 1078 |
|
RW |
32 |
0x0000 0000 |
0x07C |
0x0120 107C |
|
RW |
32 |
0x0000 8A10 |
0x080 |
0x0120 1080 |
|
RO |
32 |
0x0000 0000 |
0x084 |
0x0120 1084 |
|
RW |
32 |
0x0000 0000 |
0x088 |
0x0120 1088 |
|
RW |
32 |
0x0000 0000 |
0x08C |
0x0120 108C |
|
RW |
32 |
0x0000 7200 |
0x090 |
0x0120 1090 |
|
RW |
32 |
0xE000 0000 |
0x094 |
0x0120 1094 |
|
RW |
32 |
0x0000 0000 |
0x098 |
0x0120 1098 |
|
RW |
32 |
0x0100 0000 |
0x09C |
0x0120 109C |
|
RW |
32 |
0x0000 0000 |
0x0A0 |
0x0120 10A0 |
|
RW |
32 |
0x001B 3423 |
0x0A4 |
0x0120 10A4 |
|
RW |
32 |
0x0023 2C27 |
0x0A8 |
0x0120 10A8 |
|
RW |
32 |
0x001B 1B1B |
0x0AC |
0x0120 10AC |
|
RW |
32 |
0x001B 1B14 |
0x0B0 |
0x0120 10B0 |
|
RW |
32 |
0x0024 0C0A |
0x0B4 |
0x0120 10B4 |
|
RW |
32 |
0x1B38 3B38 |
0x0B8 |
0x0120 10B8 |
|
RW |
32 |
0x0000 0100 |
0x0C0 |
0x0120 10C0 |
|
RW |
32 |
0x6410 0702 |
0x0D0 |
0x0120 10D0 |
|
RW |
32 |
0x0103 4018 |
0x0D4 |
0x0120 10D4 |
|
RW |
32 |
0x0080 0000 |
0x0D8 |
0x0120 10D8 |
|
RW |
32 |
0x0000 0000 |
0x0DC |
0x0120 10DC |
|
RW |
32 |
0x0000 0000 |
0x0E0 |
0x0120 10E0 |
|
RO |
32 |
0x0000 0000 |
0x0E4 |
0x0120 10E4 |
|
RO |
32 |
0x0000 0000 |
0x0E8 |
0x0120 10E8 |
|
RO |
32 |
0x0000 0000 |
0x0EC |
0x0120 10EC |
|
RO |
32 |
0x0000 0000 |
0x0F0 |
0x0120 10F0 |
|
RO |
32 |
0x0000 0000 |
0x0F4 |
0x0120 10F4 |
|
RO |
32 |
0x0000 0000 |
0x0F8 |
0x0120 10F8 |
|
RO |
32 |
0x0000 0000 |
0x0FC |
0x0120 10FC |
|
RO |
32 |
0x0000 0000 |
0x100 |
0x0120 1100 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0120 2000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x0120 2004 |
|
RW |
32 |
0x0000 0015 |
0x008 |
0x0120 2008 |
|
RW |
32 |
0x0000 0000 |
0x00C |
0x0120 200C |
|
RW |
32 |
0x0000 0015 |
0x010 |
0x0120 2010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x0120 2014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x0120 2018 |
|
RW |
32 |
0x0000 0000 |
0x020 |
0x0120 2020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x0120 2024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x0120 2028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
0x0120 202C |
|
RW |
32 |
0x0000 00A7 |
0x030 |
0x0120 2030 |
|
RW |
32 |
0x0000 00AC |
0x034 |
0x0120 2034 |
|
RW |
32 |
0x0000 00C8 |
0x038 |
0x0120 2038 |
|
RW |
32 |
0x0000 0008 |
0x03C |
0x0120 203C |
|
RW |
32 |
0x0000 2219 |
0x040 |
0x0120 2040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
0x0120 2044 |
|
RW |
32 |
0x0000 003C |
0x048 |
0x0120 2048 |
|
RW |
32 |
0x0000 002F |
0x04C |
0x0120 204C |
|
RW |
32 |
0x0000 0000 |
0x050 |
0x0120 2050 |
|
RW |
32 |
0x0232 2219 |
0x054 |
0x0120 2054 |
|
RW |
32 |
0x2218 4418 |
0x058 |
0x0120 2058 |
|
RW |
32 |
0x0000 0230 |
0x05C |
0x0120 205C |
|
RW |
32 |
0x0000 0000 |
0x070 |
0x0120 2070 |
|
RW |
32 |
0x0000 0070 |
0x074 |
0x0120 2074 |
|
RW |
32 |
0x0000 0006 |
0x078 |
0x0120 2078 |
|
RW |
32 |
0x0000 0000 |
0x07C |
0x0120 207C |
|
RW |
32 |
0x0000 8A10 |
0x080 |
0x0120 2080 |
|
RO |
32 |
0x0000 0000 |
0x084 |
0x0120 2084 |
|
RW |
32 |
0x0000 0000 |
0x088 |
0x0120 2088 |
|
RW |
32 |
0x0000 0000 |
0x08C |
0x0120 208C |
|
RW |
32 |
0x0000 7200 |
0x090 |
0x0120 2090 |
|
RW |
32 |
0xE000 0000 |
0x094 |
0x0120 2094 |
|
RW |
32 |
0x0000 0000 |
0x098 |
0x0120 2098 |
|
RW |
32 |
0x0100 0000 |
0x09C |
0x0120 209C |
|
RW |
32 |
0x0000 0000 |
0x0A0 |
0x0120 20A0 |
|
RW |
32 |
0x001B 3423 |
0x0A4 |
0x0120 20A4 |
|
RW |
32 |
0x0023 2C27 |
0x0A8 |
0x0120 20A8 |
|
RW |
32 |
0x001B 1B1B |
0x0AC |
0x0120 20AC |
|
RW |
32 |
0x001B 1B14 |
0x0B0 |
0x0120 20B0 |
|
RW |
32 |
0x0024 0C0A |
0x0B4 |
0x0120 20B4 |
|
RW |
32 |
0x1B38 3B38 |
0x0B8 |
0x0120 20B8 |
|
RW |
32 |
0x0000 0100 |
0x0C0 |
0x0120 20C0 |
|
RW |
32 |
0x6410 0702 |
0x0D0 |
0x0120 20D0 |
|
RW |
32 |
0x0103 4018 |
0x0D4 |
0x0120 20D4 |
|
RW |
32 |
0x0080 0000 |
0x0D8 |
0x0120 20D8 |
|
RW |
32 |
0x0000 0000 |
0x0DC |
0x0120 20DC |
|
RW |
32 |
0x0000 0000 |
0x0E0 |
0x0120 20E0 |
|
RO |
32 |
0x0000 0000 |
0x0E4 |
0x0120 20E4 |
|
RO |
32 |
0x0000 0000 |
0x0E8 |
0x0120 20E8 |
|
RO |
32 |
0x0000 0000 |
0x0EC |
0x0120 20EC |
|
RO |
32 |
0x0000 0000 |
0x0F0 |
0x0120 20F0 |
|
RO |
32 |
0x0000 0000 |
0x0F4 |
0x0120 20F4 |
|
RO |
32 |
0x0000 0000 |
0x0F8 |
0x0120 20F8 |
|
RO |
32 |
0x0000 0000 |
0x0FC |
0x0120 20FC |
|
RO |
32 |
0x0000 0000 |
0x100 |
0x0120 2100 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0120 4000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x0120 4004 |
|
RW |
32 |
0x0000 0015 |
0x008 |
0x0120 4008 |
|
RW |
32 |
0x0000 0000 |
0x00C |
0x0120 400C |
|
RW |
32 |
0x0000 0015 |
0x010 |
0x0120 4010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x0120 4014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x0120 4018 |
|
RW |
32 |
0x0000 0000 |
0x020 |
0x0120 4020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x0120 4024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x0120 4028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
0x0120 402C |
|
RW |
32 |
0x0000 00A7 |
0x030 |
0x0120 4030 |
|
RW |
32 |
0x0000 00AC |
0x034 |
0x0120 4034 |
|
RW |
32 |
0x0000 00C8 |
0x038 |
0x0120 4038 |
|
RW |
32 |
0x0000 0008 |
0x03C |
0x0120 403C |
|
RW |
32 |
0x0000 2219 |
0x040 |
0x0120 4040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
0x0120 4044 |
|
RW |
32 |
0x0000 003C |
0x048 |
0x0120 4048 |
|
RW |
32 |
0x0000 002F |
0x04C |
0x0120 404C |
|
RW |
32 |
0x0000 0000 |
0x050 |
0x0120 4050 |
|
RW |
32 |
0x0232 2219 |
0x054 |
0x0120 4054 |
|
RW |
32 |
0x2218 4418 |
0x058 |
0x0120 4058 |
|
RW |
32 |
0x0000 0230 |
0x05C |
0x0120 405C |
|
RW |
32 |
0x0000 0000 |
0x070 |
0x0120 4070 |
|
RW |
32 |
0x0000 0070 |
0x074 |
0x0120 4074 |
|
RW |
32 |
0x0000 0006 |
0x078 |
0x0120 4078 |
|
RW |
32 |
0x0000 0000 |
0x07C |
0x0120 407C |
|
RW |
32 |
0x0000 8A10 |
0x080 |
0x0120 4080 |
|
RO |
32 |
0x0000 0000 |
0x084 |
0x0120 4084 |
|
RW |
32 |
0x0000 0000 |
0x088 |
0x0120 4088 |
|
RW |
32 |
0x0000 0000 |
0x08C |
0x0120 408C |
|
RW |
32 |
0x0000 7200 |
0x090 |
0x0120 4090 |
|
RW |
32 |
0xE000 0000 |
0x094 |
0x0120 4094 |
|
RW |
32 |
0x0000 0000 |
0x098 |
0x0120 4098 |
|
RW |
32 |
0x0100 0000 |
0x09C |
0x0120 409C |
|
RW |
32 |
0x0000 0000 |
0x0A0 |
0x0120 40A0 |
|
RW |
32 |
0x001B 3423 |
0x0A4 |
0x0120 40A4 |
|
RW |
32 |
0x0023 2C27 |
0x0A8 |
0x0120 40A8 |
|
RW |
32 |
0x001B 1B1B |
0x0AC |
0x0120 40AC |
|
RW |
32 |
0x001B 1B14 |
0x0B0 |
0x0120 40B0 |
|
RW |
32 |
0x0024 0C0A |
0x0B4 |
0x0120 40B4 |
|
RW |
32 |
0x1B38 3B38 |
0x0B8 |
0x0120 40B8 |
|
RW |
32 |
0x0000 0100 |
0x0C0 |
0x0120 40C0 |
|
RW |
32 |
0x6410 0702 |
0x0D0 |
0x0120 40D0 |
|
RW |
32 |
0x0103 4018 |
0x0D4 |
0x0120 40D4 |
|
RW |
32 |
0x0080 0000 |
0x0D8 |
0x0120 40D8 |
|
RW |
32 |
0x0000 0000 |
0x0DC |
0x0120 40DC |
|
RW |
32 |
0x0000 0000 |
0x0E0 |
0x0120 40E0 |
|
RO |
32 |
0x0000 0000 |
0x0E4 |
0x0120 40E4 |
|
RO |
32 |
0x0000 0000 |
0x0E8 |
0x0120 40E8 |
|
RO |
32 |
0x0000 0000 |
0x0EC |
0x0120 40EC |
|
RO |
32 |
0x0000 0000 |
0x0F0 |
0x0120 40F0 |
|
RO |
32 |
0x0000 0000 |
0x0F4 |
0x0120 40F4 |
|
RO |
32 |
0x0000 0000 |
0x0F8 |
0x0120 40F8 |
|
RO |
32 |
0x0000 0000 |
0x0FC |
0x0120 40FC |
|
RO |
32 |
0x0000 0000 |
0x100 |
0x0120 4100 |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x0120 8000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x0120 8004 |
|
RW |
32 |
0x0000 0015 |
0x008 |
0x0120 8008 |
|
RW |
32 |
0x0000 0000 |
0x00C |
0x0120 800C |
|
RW |
32 |
0x0000 0015 |
0x010 |
0x0120 8010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x0120 8014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x0120 8018 |
|
RW |
32 |
0x0000 0000 |
0x020 |
0x0120 8020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x0120 8024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x0120 8028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
0x0120 802C |
|
RW |
32 |
0x0000 00A7 |
0x030 |
0x0120 8030 |
|
RW |
32 |
0x0000 00AC |
0x034 |
0x0120 8034 |
|
RW |
32 |
0x0000 00C8 |
0x038 |
0x0120 8038 |
|
RW |
32 |
0x0000 0008 |
0x03C |
0x0120 803C |
|
RW |
32 |
0x0000 2219 |
0x040 |
0x0120 8040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
0x0120 8044 |
|
RW |
32 |
0x0000 003C |
0x048 |
0x0120 8048 |
|
RW |
32 |
0x0000 002F |
0x04C |
0x0120 804C |
|
RW |
32 |
0x0000 0000 |
0x050 |
0x0120 8050 |
|
RW |
32 |
0x0232 2219 |
0x054 |
0x0120 8054 |
|
RW |
32 |
0x2218 4418 |
0x058 |
0x0120 8058 |
|
RW |
32 |
0x0000 0230 |
0x05C |
0x0120 805C |
|
RW |
32 |
0x0000 0000 |
0x070 |
0x0120 8070 |
|
RW |
32 |
0x0000 0070 |
0x074 |
0x0120 8074 |
|
RW |
32 |
0x0000 0006 |
0x078 |
0x0120 8078 |
|
RW |
32 |
0x0000 0000 |
0x07C |
0x0120 807C |
|
RW |
32 |
0x0000 8A10 |
0x080 |
0x0120 8080 |
|
RO |
32 |
0x0000 0000 |
0x084 |
0x0120 8084 |
|
RW |
32 |
0x0000 0000 |
0x088 |
0x0120 8088 |
|
RW |
32 |
0x0000 0000 |
0x08C |
0x0120 808C |
|
RW |
32 |
0x0000 7200 |
0x090 |
0x0120 8090 |
|
RW |
32 |
0xE000 0000 |
0x094 |
0x0120 8094 |
|
RW |
32 |
0x0000 0000 |
0x098 |
0x0120 8098 |
|
RW |
32 |
0x0100 0000 |
0x09C |
0x0120 809C |
|
RW |
32 |
0x0000 0000 |
0x0A0 |
0x0120 80A0 |
|
RW |
32 |
0x001B 3423 |
0x0A4 |
0x0120 80A4 |
|
RW |
32 |
0x0023 2C27 |
0x0A8 |
0x0120 80A8 |
|
RW |
32 |
0x001B 1B1B |
0x0AC |
0x0120 80AC |
|
RW |
32 |
0x001B 1B14 |
0x0B0 |
0x0120 80B0 |
|
RW |
32 |
0x0024 0C0A |
0x0B4 |
0x0120 80B4 |
|
RW |
32 |
0x1B38 3B38 |
0x0B8 |
0x0120 80B8 |
|
RW |
32 |
0x0000 0100 |
0x0C0 |
0x0120 80C0 |
|
RW |
32 |
0x6410 0702 |
0x0D0 |
0x0120 80D0 |
|
RW |
32 |
0x0103 4018 |
0x0D4 |
0x0120 80D4 |
|
RW |
32 |
0x0080 0000 |
0x0D8 |
0x0120 80D8 |
|
RW |
32 |
0x0000 0000 |
0x0DC |
0x0120 80DC |
|
RW |
32 |
0x0000 0000 |
0x0E0 |
0x0120 80E0 |
|
RO |
32 |
0x0000 0000 |
0x0E4 |
0x0120 80E4 |
|
RO |
32 |
0x0000 0000 |
0x0E8 |
0x0120 80E8 |
|
RO |
32 |
0x0000 0000 |
0x0EC |
0x0120 80EC |
|
RO |
32 |
0x0000 0000 |
0x0F0 |
0x0120 80F0 |
|
RO |
32 |
0x0000 0000 |
0x0F4 |
0x0120 80F4 |
|
RO |
32 |
0x0000 0000 |
0x0F8 |
0x0120 80F8 |
|
RO |
32 |
0x0000 0000 |
0x0FC |
0x0120 80FC |
|
RO |
32 |
0x0000 0000 |
0x100 |
0x0120 8100 |
Address offset |
0x000 |
||
Physical address |
0x0108 4000 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8000 |
serdes_2_PMA_LANE3 |
||
0x0108 2000 |
serdes_1_PMA_LANE1 |
||
0x0120 8000 |
serdes_3_PMA_LANE3 |
||
0x0104 4000 |
serdes_0_PMA_LANE2 |
||
0x0120 2000 |
serdes_3_PMA_LANE1 |
||
0x0108 1000 |
serdes_1_PMA_LANE0 |
||
0x0104 2000 |
serdes_0_PMA_LANE1 |
||
0x0110 1000 |
serdes_2_PMA_LANE0 |
||
0x0110 4000 |
serdes_2_PMA_LANE2 |
||
0x0104 8000 |
serdes_0_PMA_LANE3 |
||
0x0110 2000 |
serdes_2_PMA_LANE1 |
||
0x0108 8000 |
serdes_1_PMA_LANE3 |
||
0x0120 4000 |
serdes_3_PMA_LANE2 |
||
0x0104 1000 |
serdes_0_PMA_LANE0 |
||
0x0120 1000 |
serdes_3_PMA_LANE0 |
||
Description |
Compulsory register for all SCB slaves, facilitating
global soft reset. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:16 |
BLOCKID |
This returns the block type and chip location. The value
of BLOCKID depends on the block type and instance of Serial block containing
this page and upon the page (lane) instance number as follows: {4'h0,
SLVTYPE, CHIPID, SUBID}. The SLVTPE value is 4'h1 for PMA. The CHIPID is
determined by integration via constant applied to tieoff_chipid[3:0] . The SUBID is
the identity of the lane instance copy of this register page (lane 0 has
SUBID=0, lane 1 has SUBID=1, lane 2, lane 3 has SUBID=3). |
RO |
0x0000 |
|
|
|
Read 0x0000 |
[block_address_PMA_LANE]
Indicates the Block chip location. |
|
|
15:9 |
Reserved |
|
RO |
0x00 |
|
8 |
PERIPH |
This asserts functional reset of the peripheral block. It
is asserted and left asserted at power-up. |
WO |
0 |
|
|
|
Write 0 |
[scb_periph_not_in_soft_reset_PMA_LANE]
Reset not asserted. |
|
|
|
|
Write 1 |
[scb_periph_reset_PMA_LANE] SCB
registers reset pulsed. |
|
|
7:2 |
Reserved |
|
RO |
0x00 |
|
1 |
V_MAP |
Resets all the volatile register bits. |
WO |
0 |
|
|
|
Write 0 |
[scb_v_regs_not_in_soft_reset_PMA_LANE]
Reset not asserted. |
|
|
|
|
Write 1 |
[scb_v_regs_reset_PMA_LANE] SCB
Volatile reset (i.e. RW-X registers are reset) |
|
|
0 |
NV_MAP |
Resets all the non-volatile register bits (e.g. RW-P bits). |
WO |
0 |
|
|
|
Write 0 |
[scb_nv_regs_not_in_soft_reset_PMA_LANE]
Reset not asserted. |
|
|
|
|
Write 1 |
[scb_nv_regs_reset_PMA_LANE] SCB
Non-Volatile reset (i.e. RW-P registers are reset. |
|
Address offset |
0x004 |
||
Physical address |
0x0108 4004 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8004 |
serdes_2_PMA_LANE3 |
||
0x0108 2004 |
serdes_1_PMA_LANE1 |
||
0x0120 8004 |
serdes_3_PMA_LANE3 |
||
0x0104 4004 |
serdes_0_PMA_LANE2 |
||
0x0120 2004 |
serdes_3_PMA_LANE1 |
||
0x0108 1004 |
serdes_1_PMA_LANE0 |
||
0x0104 2004 |
serdes_0_PMA_LANE1 |
||
0x0110 1004 |
serdes_2_PMA_LANE0 |
||
0x0110 4004 |
serdes_2_PMA_LANE2 |
||
0x0104 8004 |
serdes_0_PMA_LANE3 |
||
0x0110 2004 |
serdes_2_PMA_LANE1 |
||
0x0108 8004 |
serdes_1_PMA_LANE3 |
||
0x0120 4004 |
serdes_3_PMA_LANE2 |
||
0x0104 1004 |
serdes_0_PMA_LANE0 |
||
0x0120 1004 |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer CDR
control configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:29 |
CMRTRIM_CDR |
Trim for common mode restore circuit |
RW |
0x0 |
|
|
|
0x0 |
[cdr_trim_cmn_mode_disabled]
Disables CDR Trim for common mode restore circuit. |
|
|
|
|
0x1 |
[cdr_trim_cmn_mode_min_adj] CDR
Trim for common mode restore circuit minimum adjustment |
|
|
|
|
0x7 |
[cdr_trim_cmn_mode_max_adj] CDR
Trim for common mode restore circuit maximum adjustment |
|
|
28:24 |
H0CDR3 |
DC offset calibration of CDR sampler 3 |
RW |
0x00 |
|
23:21 |
Reserved |
|
RO |
0x0 |
|
20:16 |
H0CDR2 |
DC offset calibration of CDR sampler 2 |
RW |
0x00 |
|
15:13 |
Reserved |
|
RO |
0x0 |
|
12:8 |
H0CDR1 |
DC offset calibration of CDR sampler 1 |
RW |
0x00 |
|
7:6 |
Reserved |
|
RO |
0x0 |
|
5:1 |
H0CDR0 |
DC offset calibration of CDR sampler 0 |
RW |
0x00 |
|
0 |
DCFBEN_CDR |
Enable DC offset cancellation of the first two CTLE stages
(CDR) |
RW |
0 |
|
|
|
0 |
[cdr_dc_offset_cancel_disabled]
Disables DC offset cancellation of the first two CTLE stages (CDR) |
|
|
|
|
1 |
[cdr_dc_offset_cancel_enabled]
Enable DC offset cancellation of the first two CTLE stages (CDR) |
|
Address offset |
0x008 |
||
Physical address |
0x0108 4008 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8008 |
serdes_2_PMA_LANE3 |
||
0x0108 2008 |
serdes_1_PMA_LANE1 |
||
0x0120 8008 |
serdes_3_PMA_LANE3 |
||
0x0104 4008 |
serdes_0_PMA_LANE2 |
||
0x0120 2008 |
serdes_3_PMA_LANE1 |
||
0x0108 1008 |
serdes_1_PMA_LANE0 |
||
0x0104 2008 |
serdes_0_PMA_LANE1 |
||
0x0110 1008 |
serdes_2_PMA_LANE0 |
||
0x0110 4008 |
serdes_2_PMA_LANE2 |
||
0x0104 8008 |
serdes_0_PMA_LANE3 |
||
0x0110 2008 |
serdes_2_PMA_LANE1 |
||
0x0108 8008 |
serdes_1_PMA_LANE3 |
||
0x0120 4008 |
serdes_3_PMA_LANE2 |
||
0x0104 1008 |
serdes_0_PMA_LANE0 |
||
0x0120 1008 |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer CDR
control configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:12 |
Reserved |
|
RO |
0x0 0000 |
|
11:8 |
CALOUT_CDR |
Subsampled CDR output for DC feedback correction |
RO |
0x0 |
|
7:6 |
Reserved |
|
RO |
0x0 |
|
5:4 |
CSENT3_CDR |
CTLE Current Source Trim |
RW |
0x1 |
|
|
|
0x0 |
[cdr_ctle3_current_source_trim_min] CDR CTLE3 current
source trim minimum current |
|
|
|
|
0x3 |
[cdr_ctle3_current_source_trim_max] CDR CTLE3 current
source trim maximum current |
|
|
3:2 |
CSENT2_CDR |
CTLE Current Source Trim |
RW |
0x1 |
|
|
|
0x0 |
[cdr_ctle2_current_source_trim_min] CDR CTLE2 current
source trim minimum current |
|
|
|
|
0x3 |
[cdr_ctle2_current_source_trim_max] CDR CTLE2 current
source trim maximum current |
|
|
1:0 |
CSENT1_CDR |
CTLE Current Source Trim |
RW |
0x1 |
|
|
|
0x0 |
[cdr_ctle1_current_source_trim_min] CDR CTLE1 current
source trim minimum current |
|
|
|
|
0x3 |
[cdr_ctle1_current_source_trim_max] CDR CTLE1 current
source trim maximum current |
|
Address offset |
0x00C |
||
Physical address |
0x0108 400C |
Instance |
serdes_1_PMA_LANE2 |
0x0110 800C |
serdes_2_PMA_LANE3 |
||
0x0108 200C |
serdes_1_PMA_LANE1 |
||
0x0120 800C |
serdes_3_PMA_LANE3 |
||
0x0104 400C |
serdes_0_PMA_LANE2 |
||
0x0120 200C |
serdes_3_PMA_LANE1 |
||
0x0108 100C |
serdes_1_PMA_LANE0 |
||
0x0104 200C |
serdes_0_PMA_LANE1 |
||
0x0110 100C |
serdes_2_PMA_LANE0 |
||
0x0110 400C |
serdes_2_PMA_LANE2 |
||
0x0104 800C |
serdes_0_PMA_LANE3 |
||
0x0110 200C |
serdes_2_PMA_LANE1 |
||
0x0108 800C |
serdes_1_PMA_LANE3 |
||
0x0120 400C |
serdes_3_PMA_LANE2 |
||
0x0104 100C |
serdes_0_PMA_LANE0 |
||
0x0120 100C |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer CDR
control configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:20 |
Reserved |
|
RO |
0x000 |
|
19 |
SLIP_DES_CDR_STATUS |
De-serializer CDR Slip bit status |
RO |
0 |
|
18 |
SLIP_DES_CDR_EN |
De-serializer CDR Slip function enable
|
RW |
0 |
|
|
|
0 |
[slip_deserializer_cdr_function_disabled]
Disables Slip deserializer CDR Function |
|
|
|
|
1 |
[slip_deserializer_cdr_function_enabled]
Enables Slip deserializer CDR Function |
|
|
17 |
SLIP_DES_CDR_SEL |
Select de-serializer CDR slip controller |
RW |
0 |
|
|
|
0 |
[slip_deserializer_cdr_from_fabric_sel]
Selects Slip deserializer CDR from Fabric |
|
|
|
|
1 |
[slip_deserializer_cdr_from_cfg_reg_sel]
Selects Slip deserializer CDR from Config. Register
|
|
|
16 |
SLIP_DES_CDR |
Slip de-serializer output alignment by 1 bit |
RW |
0 |
|
|
|
0 |
[slip_deserializer_cdr_disabled]
Disables Slip deserializer CDR |
|
|
|
|
1 |
[slip_deserializer_cdr_enabled]
Enables Slip deserializer CDR |
|
|
15:10 |
Reserved |
|
RO |
0x00 |
|
9:8 |
RXDRV_CDR |
RX CLTLE BW control for CDR path |
RW |
0x0 |
|
|
|
0x0 |
[rx_cltle_bandwidth_ctrl_cdr_path_disabled]
RX CLTLE BW control for CDR path off for DC calibration |
|
|
|
|
0x1 |
[rx_cltle_bandwidth_ctrl_cdr_path_min]
RX CLTLE minimum bandwidth control for CDR path |
|
|
|
|
0x3 |
[rx_cltle_bandwidth_ctrl_cdr_path_max]
RX CLTLE maximum bandwidth control for CDR path |
|
|
7:6 |
RST2_CDR |
CTLE source resistor trim, second CTLE stage |
RW |
0x0 |
|
|
|
0x0 |
[cdr_ctle2_source_res_trim_1st_stg_min] CDR CTLE source
resistor trim for first stage minimum value |
|
|
|
|
0x3 |
[cdr_ctle2_source_res_trim_1st_stg_max] CDR CTLE source
resistor trim for first stage maximum value |
|
|
5:4 |
RST1_CDR |
CTLE source resistor trim, second CTLE stage |
RW |
0x0 |
|
|
|
0x0 |
[cdr_ctle1_source_res_trim_2nd_stg_min] CDR CTLE source
resistor trim for second stage minimum value |
|
|
|
|
0x3 |
[cdr_ctle1_source_res_trim_2nd_stg_max] CDR CTLE source
resistor trim for second stage maximum value |
|
|
3:2 |
CST2_CDR |
CTLE shunt capacitor trim for first stage |
RW |
0x0 |
|
|
|
0x0 |
[cdr_ctle2_shunt_cap_trim_1st_stg_min] CDR CTLE2 shunt
capacitor trim for first stage minimum peaking |
|
|
|
|
0x3 |
[cdr_ctle2_shunt_cap_trim_1st_stg_max] CDR CTLE2 shunt
capacitor trim for first stage maximum peaking |
|
|
1:0 |
CST1_CDR |
CTLE shunt capacitor trim for second stage |
RW |
0x0 |
|
|
|
0x0 |
[cdr_ctle1_shunt_cap_trim_2nd_stg_min] CDR CTLE1 shunt
capacitor trim for second stage minimum peaking |
|
|
|
|
0x3 |
[cdr_ctle1_shunt_cap_trim_2nd_stg_max] CDR CTLE1 shunt
capacitor trim for second stage maximum peaking |
|
Address offset |
0x010 |
||
Physical address |
0x0108 4010 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8010 |
serdes_2_PMA_LANE3 |
||
0x0108 2010 |
serdes_1_PMA_LANE1 |
||
0x0120 8010 |
serdes_3_PMA_LANE3 |
||
0x0104 4010 |
serdes_0_PMA_LANE2 |
||
0x0120 2010 |
serdes_3_PMA_LANE1 |
||
0x0108 1010 |
serdes_1_PMA_LANE0 |
||
0x0104 2010 |
serdes_0_PMA_LANE1 |
||
0x0110 1010 |
serdes_2_PMA_LANE0 |
||
0x0110 4010 |
serdes_2_PMA_LANE2 |
||
0x0104 8010 |
serdes_0_PMA_LANE3 |
||
0x0110 2010 |
serdes_2_PMA_LANE1 |
||
0x0108 8010 |
serdes_1_PMA_LANE3 |
||
0x0120 4010 |
serdes_3_PMA_LANE2 |
||
0x0104 1010 |
serdes_0_PMA_LANE0 |
||
0x0120 1010 |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer DFEEM
control configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:11 |
Reserved |
|
RO |
0x00 0000 |
|
10:8 |
CMRTRIM_DFEEM |
For DFE/Eye Monitor Trim for common mode restore circuit |
RW |
0x0 |
|
|
|
0x0 |
[dfeem_trim_cmn_mode_disabled]
CDR Trim for common mode restore circuit Disables |
|
|
|
|
0x1 |
[dfeem_trim_cmn_mode_min_adj]
CDR Trim for common mode restore circuit minimum adjustment |
|
|
|
|
0x7 |
[dfeem_trim_cmn_mode_max_adj]
CDR Trim for common mode restore circuit maximum adjustment |
|
|
7:6 |
Reserved |
|
RO |
0x0 |
|
5:4 |
CSENT3_DFEEM |
CTLE Current Source Trim |
RW |
0x1 |
|
|
|
0x0 |
[dfeem_ctle3_current_source_trim_min] DFEEM CTLE3 current
source trim minimum current |
|
|
|
|
0x3 |
[dfeem_ctle3_current_source_trim_max] DFEEM CTLE3 current
source trim maximum current |
|
|
3:2 |
CSENT2_DFEEM |
CTLE Current Source Trim |
RW |
0x1 |
|
|
|
0x0 |
[dfeem_ctle2_current_source_trim_min] DFEEM CTLE2 current
source trim minimum current |
|
|
|
|
0x3 |
[dfeem_ctle2_current_source_trim_max] DFEEM CTLE2 current
source trim maximum current |
|
|
1:0 |
CSENT1_DFEEM |
CTLE Current Source Trim |
RW |
0x1 |
|
|
|
0x0 |
[dfeem_ctle1_current_source_trim_min] DFEEM CTLE1 current
source trim minimum current |
|
|
|
|
0x3 |
[dfeem_ctle1_current_source_trim_max] DFEEM CTLE1 current
source trim maximum current |
|
Address offset |
0x014 |
||
Physical address |
0x0108 4014 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8014 |
serdes_2_PMA_LANE3 |
||
0x0108 2014 |
serdes_1_PMA_LANE1 |
||
0x0120 8014 |
serdes_3_PMA_LANE3 |
||
0x0104 4014 |
serdes_0_PMA_LANE2 |
||
0x0120 2014 |
serdes_3_PMA_LANE1 |
||
0x0108 1014 |
serdes_1_PMA_LANE0 |
||
0x0104 2014 |
serdes_0_PMA_LANE1 |
||
0x0110 1014 |
serdes_2_PMA_LANE0 |
||
0x0110 4014 |
serdes_2_PMA_LANE2 |
||
0x0104 8014 |
serdes_0_PMA_LANE3 |
||
0x0110 2014 |
serdes_2_PMA_LANE1 |
||
0x0108 8014 |
serdes_1_PMA_LANE3 |
||
0x0120 4014 |
serdes_3_PMA_LANE2 |
||
0x0104 1014 |
serdes_0_PMA_LANE0 |
||
0x0120 1014 |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer DFEEM
control configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:29 |
Reserved |
|
RO |
0x0 |
28:24 |
H4 |
DFE, eye monitor tap 4 |
RW |
0x00 |
23:21 |
Reserved |
|
RO |
0x0 |
20:16 |
H3 |
DFE, eye monitor tap 3 |
RW |
0x00 |
15:13 |
Reserved |
|
RO |
0x0 |
12:8 |
H2 |
DFE, eye monitor tap 2 |
RW |
0x00 |
7:5 |
Reserved |
|
RO |
0x0 |
4:0 |
H1 |
DFE, eye monitor tap 1 |
RW |
0x00 |
Address offset |
0x018 |
||
Physical address |
0x0108 4018 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8018 |
serdes_2_PMA_LANE3 |
||
0x0108 2018 |
serdes_1_PMA_LANE1 |
||
0x0120 8018 |
serdes_3_PMA_LANE3 |
||
0x0104 4018 |
serdes_0_PMA_LANE2 |
||
0x0120 2018 |
serdes_3_PMA_LANE1 |
||
0x0108 1018 |
serdes_1_PMA_LANE0 |
||
0x0104 2018 |
serdes_0_PMA_LANE1 |
||
0x0110 1018 |
serdes_2_PMA_LANE0 |
||
0x0110 4018 |
serdes_2_PMA_LANE2 |
||
0x0104 8018 |
serdes_0_PMA_LANE3 |
||
0x0110 2018 |
serdes_2_PMA_LANE1 |
||
0x0108 8018 |
serdes_1_PMA_LANE3 |
||
0x0120 4018 |
serdes_3_PMA_LANE2 |
||
0x0104 1018 |
serdes_0_PMA_LANE0 |
||
0x0120 1018 |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer DFEEM
control configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:16 |
Reserved |
|
RO |
0x0000 |
|
15:14 |
RST2_DFEEM |
CTLE source resistor trim, first CTLE stage |
RW |
0x0 |
|
|
|
0x0 |
[dfeem_ctle2_source_res_trim_1st_stg_min] DFEEM CTLE
source resistor trim for first stage minimum value |
|
|
|
|
0x3 |
[dfeem_ctle2_source_res_trim_1st_stg_max] DFEEM CTLE
source resistor trim for first stage maximum value |
|
|
13:12 |
RST1_DFEEM |
CTLE source resistor trim, first CTLE stage |
RW |
0x0 |
|
|
|
0x0 |
[dfeem_ctle1_source_res_trim_2nd_stg_min] DFEEM CTLE source
resistor trim for second stage minimum value |
|
|
|
|
0x3 |
[dfeem_ctle1_source_res_trim_2nd_stg_max] DFEEM CTLE
source resistor trim for second stage maximum value |
|
|
11:10 |
CST2_DFEEM |
CTLE shunt capacitor trim for first stage |
RW |
0x0 |
|
|
|
0x0 |
[dfeem_ctle2_shunt_cap_trim_1st_stg_min] DFEEM CTLE2 shunt
capacitor trim for first stage minimum peaking |
|
|
|
|
0x3 |
[dfeem_ctle2_shunt_cap_trim_1st_stg_max] DFEEM CTLE2 shunt
capacitor trim for first stage maximum peaking |
|
|
9:8 |
CST1_DFEEM |
CTLE shunt capacitor trim for first stage |
RW |
0x0 |
|
|
|
0x0 |
[dfeem_ctle1_shunt_cap_trim_2nd_stg_min] DFEEM CTLE1 shunt
capacitor trim for second stage minimum peaking |
|
|
|
|
0x3 |
[dfeem_ctle1_shunt_cap_trim_2nd_stg_max] DFEEM CTLE1 shunt
capacitor trim for second stage maximum peaking |
|
|
7:5 |
Reserved |
|
RO |
0x0 |
|
4:0 |
H5 |
DFE, eye monitor tap 5 |
RW |
0x00 |
Address offset |
0x020 |
||
Physical address |
0x0108 4020 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8020 |
serdes_2_PMA_LANE3 |
||
0x0108 2020 |
serdes_1_PMA_LANE1 |
||
0x0120 8020 |
serdes_3_PMA_LANE3 |
||
0x0104 4020 |
serdes_0_PMA_LANE2 |
||
0x0120 2020 |
serdes_3_PMA_LANE1 |
||
0x0108 1020 |
serdes_1_PMA_LANE0 |
||
0x0104 2020 |
serdes_0_PMA_LANE1 |
||
0x0110 1020 |
serdes_2_PMA_LANE0 |
||
0x0110 4020 |
serdes_2_PMA_LANE2 |
||
0x0104 8020 |
serdes_0_PMA_LANE3 |
||
0x0110 2020 |
serdes_2_PMA_LANE1 |
||
0x0108 8020 |
serdes_1_PMA_LANE3 |
||
0x0120 4020 |
serdes_3_PMA_LANE2 |
||
0x0104 1020 |
serdes_0_PMA_LANE0 |
||
0x0120 1020 |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer DFE
control configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:18 |
Reserved |
|
RO |
0x0000 |
|
17:16 |
CALOUT_DFE |
Subsampled DFE output for DC feedback correction |
RO |
0x0 |
|
15:13 |
Reserved |
|
RO |
0x0 |
|
12:8 |
H0DFE1 |
DFE tap1 and DC offset calibration for DFE sampler 1 |
RW |
0x00 |
|
7:6 |
Reserved |
|
RO |
0x0 |
|
5:1 |
H0DFE0 |
DFE tap1 and DC offset calibration for DFE sampler 0 |
RW |
0x00 |
|
0 |
DCFBEN_DFE |
Enable DC offset cancellation of the first two CTLE stages
(DFE) |
RW |
0 |
|
|
|
0 |
[dfe_dc_offset_cancel_disabled]
Disables DC offset cancellation of the first two CTLE stages (DFE) |
|
|
|
|
1 |
[dfe_dc_offset_cancel_enabled]
Enables DC offset cancellation of the first two CTLE stages (DFE) |
|
Address offset |
0x024 |
||
Physical address |
0x0108 4024 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8024 |
serdes_2_PMA_LANE3 |
||
0x0108 2024 |
serdes_1_PMA_LANE1 |
||
0x0120 8024 |
serdes_3_PMA_LANE3 |
||
0x0104 4024 |
serdes_0_PMA_LANE2 |
||
0x0120 2024 |
serdes_3_PMA_LANE1 |
||
0x0108 1024 |
serdes_1_PMA_LANE0 |
||
0x0104 2024 |
serdes_0_PMA_LANE1 |
||
0x0110 1024 |
serdes_2_PMA_LANE0 |
||
0x0110 4024 |
serdes_2_PMA_LANE2 |
||
0x0104 8024 |
serdes_0_PMA_LANE3 |
||
0x0110 2024 |
serdes_2_PMA_LANE1 |
||
0x0108 8024 |
serdes_1_PMA_LANE3 |
||
0x0120 4024 |
serdes_3_PMA_LANE2 |
||
0x0104 1024 |
serdes_0_PMA_LANE0 |
||
0x0120 1024 |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer DFE
control configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:28 |
Reserved |
|
RO |
0x0 |
|
27 |
SLIP_DES_DFE_STATUS |
De-serializer DFE Slip bit status |
RO |
0 |
|
26 |
SLIP_DES_DFE_EN |
De-serializer DFE Slip function enable |
RW |
0 |
|
|
|
0 |
[slip_deserializer_dfe_function_disabled]
Disables Slip deserializer DFE Function |
|
|
|
|
1 |
[slip_deserializer_dfe_function_enabled]
Enables Slip deserializer DFE Function |
|
|
25 |
SLIP_DES_DFE_SEL |
Select de-serializer DFE slip controller |
RW |
0 |
|
|
|
0 |
[slip_deserializer_dfe_from_fabric_sel]
Selects Slip deserializer DFE from Fabric |
|
|
|
|
1 |
[slip_deserializer_dfe_from_cfg_reg_sel]
Selects Slip deserializer DFE from Config. Register
|
|
|
24 |
SLIP_DES_DFE |
Slip de-serializer output alignment by 1 bit |
RW |
0 |
|
|
|
0 |
[slip_deserializer_dfe_disabled]
Disables Slip deserializer DFE |
|
|
|
|
1 |
[slip_deserializer_dfe_enabled]
Enables Slip deserializer DFE |
|
|
23:19 |
Reserved |
|
RO |
0x00 |
|
18:16 |
PHICTRL_GRAY_DFE |
Gray Coded Phase control for DFE |
RW |
0x0 |
|
15:8 |
PHICTRL_TH_DFE |
Thermometer Coded Phase control for DFE |
RW |
0x00 |
|
7:3 |
Reserved |
|
RO |
0x00 |
|
2 |
CTLEEN_DFE |
CTLE Enable For the DFE Path |
RW |
0 |
|
|
|
0 |
[ctle_dfe_path_disabled]
Disables CTLE for DFE path |
|
|
|
|
1 |
[ctle_dfe_path_enabled] Enables
CTLE for DFE path |
|
|
1:0 |
RXDRV_DFE |
RX CLTLE BW control for DFE path |
RW |
0x0 |
|
|
|
0x0 |
[rx_cltle_bandwidth_ctrl_dfe_path_disabled]
RX CLTLE BW control for DFE path off for DC calibration |
|
|
|
|
0x1 |
[rx_cltle_bandwidth_ctrl_dfe_path_min]
RX CLTLE minimum bandwidth control for DFE path |
|
|
|
|
0x3 |
[rx_cltle_bandwidth_ctrl_dfe_path_max]
RX CLTLE maximum bandwidth control for DFE path |
|
Address offset |
0x028 |
||
Physical address |
0x0108 4028 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8028 |
serdes_2_PMA_LANE3 |
||
0x0108 2028 |
serdes_1_PMA_LANE1 |
||
0x0120 8028 |
serdes_3_PMA_LANE3 |
||
0x0104 4028 |
serdes_0_PMA_LANE2 |
||
0x0120 2028 |
serdes_3_PMA_LANE1 |
||
0x0108 1028 |
serdes_1_PMA_LANE0 |
||
0x0104 2028 |
serdes_0_PMA_LANE1 |
||
0x0110 1028 |
serdes_2_PMA_LANE0 |
||
0x0110 4028 |
serdes_2_PMA_LANE2 |
||
0x0104 8028 |
serdes_0_PMA_LANE3 |
||
0x0110 2028 |
serdes_2_PMA_LANE1 |
||
0x0108 8028 |
serdes_1_PMA_LANE3 |
||
0x0120 4028 |
serdes_3_PMA_LANE2 |
||
0x0104 1028 |
serdes_0_PMA_LANE0 |
||
0x0120 1028 |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer EM
control configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:26 |
Reserved |
|
RO |
0x00 |
|
25:24 |
CALOUT_EM |
Subsampled DFE output for DC feedback correction |
RO |
0x0 |
|
23:17 |
Reserved |
|
RO |
0x00 |
|
16 |
CALIBRATION_CLK_EN |
Enable de-serializer DC calibration clock |
RW |
0 |
|
|
|
0 |
[deserializer_calibration_clk_disabled]
Disables de-serializer DC calibration clock |
|
|
|
|
1 |
[deserializer_calibration_clk_enabled]
Enables de-serializer DC calibration clock |
|
|
15:13 |
Reserved |
|
RO |
0x0 |
|
12:8 |
H0EM1 |
EM tap1 and DC offset calibration for Eye monitor sampler
1 |
RW |
0x00 |
|
7:6 |
Reserved |
|
RO |
0x0 |
|
5:1 |
H0EM0 |
EM tap1 and DC offset calibration for Eye monitor sampler
0 |
RW |
0x00 |
|
0 |
DCFBEN_EM |
Enable DC offset cancellation of the first two CTLE stages
(Eye Monitor) |
RW |
0 |
|
|
|
0 |
[em_dc_offset_cancel_disabled]
Disables DC offset cancellation of the first two CTLE stages (EM) |
|
|
|
|
1 |
[em_dc_offset_cancel_enabled]
Enables DC offset cancellation of the first two CTLE stages (EM) |
|
Address offset |
0x02C |
||
Physical address |
0x0108 402C |
Instance |
serdes_1_PMA_LANE2 |
0x0110 802C |
serdes_2_PMA_LANE3 |
||
0x0108 202C |
serdes_1_PMA_LANE1 |
||
0x0120 802C |
serdes_3_PMA_LANE3 |
||
0x0104 402C |
serdes_0_PMA_LANE2 |
||
0x0120 202C |
serdes_3_PMA_LANE1 |
||
0x0108 102C |
serdes_1_PMA_LANE0 |
||
0x0104 202C |
serdes_0_PMA_LANE1 |
||
0x0110 102C |
serdes_2_PMA_LANE0 |
||
0x0110 402C |
serdes_2_PMA_LANE2 |
||
0x0104 802C |
serdes_0_PMA_LANE3 |
||
0x0110 202C |
serdes_2_PMA_LANE1 |
||
0x0108 802C |
serdes_1_PMA_LANE3 |
||
0x0120 402C |
serdes_3_PMA_LANE2 |
||
0x0104 102C |
serdes_0_PMA_LANE0 |
||
0x0120 102C |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer EM
control configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:28 |
Reserved |
|
RO |
0x0 |
|
27 |
SLIP_DES_EM_STATUS |
De-serializer Eye Monitor Slip bit status |
RO |
0 |
|
26 |
SLIP_DES_EM_EN |
De-serializer Eye Monitor Slip function enable
|
RW |
0 |
|
|
|
0 |
[slip_deserializer_em_function_disabled]
Disables Slip deserializer EM Function |
|
|
|
|
1 |
[slip_deserializer_em_function_enabled]
Enables Slip deserializer EM Function |
|
|
25 |
SLIP_DES_EM_SEL |
Select de-serializer eye monitor slip controller |
RW |
0 |
|
|
|
0 |
[slip_deserializer_em_from_fabric_sel]
Selects Slip deserializer EM from Fabric |
|
|
|
|
1 |
[slip_deserializer_em_from_cfg_reg_sel]
Selects Slip deserializer EM from Config. Register |
|
|
24 |
SLIP_DES_EM |
Slip de-serializer output alignment by 1 bit |
RW |
0 |
|
|
|
0 |
[slip_deserializer_em_disabled]
Disables Slip deserializer EM |
|
|
|
|
1 |
[slip_deserializer_em_enabled]
Enables Slip deserializer EM |
|
|
23:19 |
Reserved |
|
RO |
0x00 |
|
18:16 |
PHICTRL_GRAY_EM |
Gray Coded Phase control for Eye Monitor |
RW |
0x0 |
|
15:8 |
PHICTRL_TH_EM |
Thermometer Coded Phase control for Eye Monitor |
RW |
0x00 |
|
7:3 |
Reserved |
|
RO |
0x00 |
|
2 |
CTLEEN_EM |
CTLE Enable For the Eye Monitor
Path |
RW |
0 |
|
|
|
0 |
[ctle_em_path_disabled] Disables
CTLE for EM path |
|
|
|
|
1 |
[ctle_em_path_enabled] Enables
CTLE for EM path |
|
|
1:0 |
RXDRV_EM |
RX CLTLE BW control for EM path |
RW |
0x0 |
|
|
|
0x0 |
[rx_cltle_bandwidth_ctrl_em_path_disabled]
RX CLTLE BW control for EM path off for DC calibration |
|
|
|
|
0x1 |
[rx_cltle_bandwidth_ctrl_em_path_min]
RX CLTLE minimum bandwidth control for EM path |
|
|
|
|
0x3 |
[rx_cltle_bandwidth_ctrl_em_path_max]
RX CLTLE maximum bandwidth control for EM path |
|
Address offset |
0x030 |
||
Physical address |
0x0108 4030 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8030 |
serdes_2_PMA_LANE3 |
||
0x0108 2030 |
serdes_1_PMA_LANE1 |
||
0x0120 8030 |
serdes_3_PMA_LANE3 |
||
0x0104 4030 |
serdes_0_PMA_LANE2 |
||
0x0120 2030 |
serdes_3_PMA_LANE1 |
||
0x0108 1030 |
serdes_1_PMA_LANE0 |
||
0x0104 2030 |
serdes_0_PMA_LANE1 |
||
0x0110 1030 |
serdes_2_PMA_LANE0 |
||
0x0110 4030 |
serdes_2_PMA_LANE2 |
||
0x0104 8030 |
serdes_0_PMA_LANE3 |
||
0x0110 2030 |
serdes_2_PMA_LANE1 |
||
0x0108 8030 |
serdes_1_PMA_LANE3 |
||
0x0120 4030 |
serdes_3_PMA_LANE2 |
||
0x0104 1030 |
serdes_0_PMA_LANE0 |
||
0x0120 1030 |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer input
termination configuration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:8 |
Reserved |
|
RO |
0x00 0000 |
|
7 |
ACCOUPLE_RXVCM_EN |
Select AC couple mode (external AC coupling cap) or DC
couple mode for receiver |
RW |
1 |
|
|
|
0 |
[rxvcm_dc_couple_sel] DC couple
mode, common mode taken from input data |
|
|
|
|
1 |
[rxvcm_ac_couple_sel] AC couple
mode, internally generated common mode |
|
|
6:5 |
RXRTRIM_SEL |
Select RX resistor trim |
RW |
0x1 |
|
|
|
0x0 |
[rx_resistor_trim_rtermcal85_sel] Select RTERMCAL85
register value for RX resistor trim value |
|
|
|
|
0x1 |
[rx_resistor_trim_rtermcal100_sel] Select RTERMCAL100
register value for RX resistor trim value |
|
|
|
|
0x2 |
[rx_resistor_trim_rtermcal150_sel] Select RTERMCAL150
register value for RX resistor trim value |
|
|
|
|
0x3 |
[rx_resistor_trim_lane_rxrtrim_sel]
Select Lane RXRTRIM register value for RX resistor trim value |
|
|
4 |
RXTEN |
RX Vtt termination select |
RW |
0 |
|
|
|
0 |
[rx_input_termination_disabled]
Disables Vtt bias to allow DC coupling |
|
|
|
|
1 |
[rx_input_termination_enabled]
Enables RX input termination approximately 0.8*VDDA Vtt
bias to enable AC coupling |
|
|
3:0 |
RXRTRIM |
RX termination trim |
RW |
0x7 |
|
|
|
0x0 |
[rx_termination_trim_min]
Minimum RX termination trim value = 76 ohms |
|
|
|
|
0xF |
[rx_termination_trim_max]
Maximum RX terminatino trim value = 171 ohms |
|
Address offset |
0x034 |
||
Physical address |
0x0108 4034 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8034 |
serdes_2_PMA_LANE3 |
||
0x0108 2034 |
serdes_1_PMA_LANE1 |
||
0x0120 8034 |
serdes_3_PMA_LANE3 |
||
0x0104 4034 |
serdes_0_PMA_LANE2 |
||
0x0120 2034 |
serdes_3_PMA_LANE1 |
||
0x0108 1034 |
serdes_1_PMA_LANE0 |
||
0x0104 2034 |
serdes_0_PMA_LANE1 |
||
0x0110 1034 |
serdes_2_PMA_LANE0 |
||
0x0110 4034 |
serdes_2_PMA_LANE2 |
||
0x0104 8034 |
serdes_0_PMA_LANE3 |
||
0x0110 2034 |
serdes_2_PMA_LANE1 |
||
0x0108 8034 |
serdes_1_PMA_LANE3 |
||
0x0120 4034 |
serdes_3_PMA_LANE2 |
||
0x0104 1034 |
serdes_0_PMA_LANE0 |
||
0x0120 1034 |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer PKDET |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:15 |
Reserved |
|
RO |
0x0 0000 |
|
14:8 |
RXPKDETOUT |
Thermometer Coded Peak Detector Output |
RO |
0x00 |
|
7:5 |
RXPKDET_HIGH_THRESHOLD |
RX Peak Detector HIGH threshold |
RW |
0x5 |
|
4:2 |
RXPKDET_LOW_THRESHOLD |
RX Peak Detector LOW threshold |
RW |
0x3 |
|
1 |
RXPKDETRANGE |
Setting RX peak detector range |
RW |
0 |
|
|
|
0 |
[rx_peak_detector_range_30mvpb] gain is 30mV / bit |
|
|
|
|
1 |
[rx_peak_detector_range_50mvpb] gain is 50mV / bit |
|
|
0 |
RXPKDETEN |
Enable the receiver peak detector |
RW |
0 |
|
|
|
0 |
[rx_peak_detector_disabled]
Disables RX peak detector |
|
|
|
|
1 |
[rx_peak_detector_enabled]
Enables RX peak detector |
|
Address offset |
0x038 |
||
Physical address |
0x0108 4038 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8038 |
serdes_2_PMA_LANE3 |
||
0x0108 2038 |
serdes_1_PMA_LANE1 |
||
0x0120 8038 |
serdes_3_PMA_LANE3 |
||
0x0104 4038 |
serdes_0_PMA_LANE2 |
||
0x0120 2038 |
serdes_3_PMA_LANE1 |
||
0x0108 1038 |
serdes_1_PMA_LANE0 |
||
0x0104 2038 |
serdes_0_PMA_LANE1 |
||
0x0110 1038 |
serdes_2_PMA_LANE0 |
||
0x0110 4038 |
serdes_2_PMA_LANE2 |
||
0x0104 8038 |
serdes_0_PMA_LANE3 |
||
0x0110 2038 |
serdes_2_PMA_LANE1 |
||
0x0108 8038 |
serdes_1_PMA_LANE3 |
||
0x0120 4038 |
serdes_3_PMA_LANE2 |
||
0x0104 1038 |
serdes_0_PMA_LANE0 |
||
0x0120 1038 |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer RTL Eyemonitor |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:16 |
EYEMONITOR_COMPARISON_OUT |
Eye Monitor comparison error count |
RO |
0x0000 |
|
15:14 |
Reserved |
|
RO |
0x0 |
|
13 |
EYEMONITOR_COMPARISON_DONE |
Eye Monitor Done Signal |
RO |
0 |
|
12:1 |
EYEMONITOR_SAMPLE_COUNT |
Eye Monitor comparison sample count |
RW |
0x064 |
|
0 |
RUN_EYEMONITOR_COMPARISON |
Eye Monitor Comparison RTL starts on a 0->1 transition
of RUN_EYEMONITOR_COMPARISON |
RW |
0 |
|
|
|
0 |
[eyemonitor_comparison_disabled]
Disables Eye Monitor comparison |
|
|
|
|
1 |
[eyemonitor_comparison_enabled]
Enables Eye Monitor comparison |
|
Address offset |
0x03C |
||
Physical address |
0x0108 403C |
Instance |
serdes_1_PMA_LANE2 |
0x0110 803C |
serdes_2_PMA_LANE3 |
||
0x0108 203C |
serdes_1_PMA_LANE1 |
||
0x0120 803C |
serdes_3_PMA_LANE3 |
||
0x0104 403C |
serdes_0_PMA_LANE2 |
||
0x0120 203C |
serdes_3_PMA_LANE1 |
||
0x0108 103C |
serdes_1_PMA_LANE0 |
||
0x0104 203C |
serdes_0_PMA_LANE1 |
||
0x0110 103C |
serdes_2_PMA_LANE0 |
||
0x0110 403C |
serdes_2_PMA_LANE2 |
||
0x0104 803C |
serdes_0_PMA_LANE3 |
||
0x0110 203C |
serdes_2_PMA_LANE1 |
||
0x0108 803C |
serdes_1_PMA_LANE3 |
||
0x0120 403C |
serdes_3_PMA_LANE2 |
||
0x0104 103C |
serdes_0_PMA_LANE0 |
||
0x0120 103C |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer RTL LOCK
Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:25 |
Reserved |
|
RO |
0x00 |
|
24 |
LOCK_OVERRIDE_FROMFAB |
Select between LOCK_OVERRIDE and FAB_LOCK_OVERRIDE for
RXPLL lock override functionality |
RW |
0 |
|
|
|
0 |
[lock_override_sel]
LOCK_OVERRIDE controls Rx lock detector override |
|
|
|
|
1 |
[fab_lock_override_sel]
FAB_LOCK_OVERRIDE controls Rx lock detector override |
|
|
23 |
RXPLL_FLOCK |
RX PLL frequency lock indication for CDR |
RO |
0 |
|
22 |
RXPLL_LOCK |
RX PLL lock indication input for CDR |
RO |
0 |
|
21 |
FDET_VALID |
Frequency output is valid |
RO |
0 |
|
20:16 |
FDET_CURRENT_SAMPLE |
Frequency detector current sample |
RO |
0x00 |
|
15:8 |
FDET_COUNT |
Frequency detector count |
RO |
0x00 |
|
7:3 |
FDET_SAMPLE_PERIODS |
Frequency detector |
RW |
0x01 |
|
2:1 |
LOCK_OVERRIDE |
Override control for lock signal |
RW |
0x0 |
|
|
|
0x0 |
[lock_override_disabled] normal
operation (low gain mode) |
|
|
|
|
0x1 |
[lock_override_high_gain] high
gain mode |
|
|
|
|
0x2 |
[lock_override_0] forces LOCK to low (disables LOCK) |
|
|
|
|
0x3 |
[lock_override_1] forces LOCK to high (low gain mode) |
|
|
0 |
LOCK_MODE |
Set Number of Loss-Of-Lock events for LOCK to go low |
RW |
0 |
|
|
|
0 |
[lock_mode_loss_of_lock_1] 1 event of loss_of_lock
for LOCK to go low (normal operation) |
|
|
|
|
1 |
[lock_mode_loss_of_lock_2] 2 events of loss_of_lock
for LOCK to go low |
|
Address offset |
0x040 |
||
Physical address |
0x0108 4040 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8040 |
serdes_2_PMA_LANE3 |
||
0x0108 2040 |
serdes_1_PMA_LANE1 |
||
0x0120 8040 |
serdes_3_PMA_LANE3 |
||
0x0104 4040 |
serdes_0_PMA_LANE2 |
||
0x0120 2040 |
serdes_3_PMA_LANE1 |
||
0x0108 1040 |
serdes_1_PMA_LANE0 |
||
0x0104 2040 |
serdes_0_PMA_LANE1 |
||
0x0110 1040 |
serdes_2_PMA_LANE0 |
||
0x0110 4040 |
serdes_2_PMA_LANE2 |
||
0x0104 8040 |
serdes_0_PMA_LANE3 |
||
0x0110 2040 |
serdes_2_PMA_LANE1 |
||
0x0108 8040 |
serdes_1_PMA_LANE3 |
||
0x0120 4040 |
serdes_3_PMA_LANE2 |
||
0x0104 1040 |
serdes_0_PMA_LANE0 |
||
0x0120 1040 |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer RXPLL
Dividers |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:16 |
Reserved |
|
RO |
0x0000 |
|
15 |
CDR_GAIN |
Set CDR Gain |
RW |
0 |
|
|
|
0 |
[cdr_gain_low] Low Gain, lower
jitter tolerance, lower hunting jitter output |
|
|
|
|
1 |
[cdr_gain_default] Default Gain,
higher jitter tolerance, higher hunting jitter output |
|
|
14:13 |
RXPLL_RANGE |
RX PLL Range Bit for CDR |
RW |
0x1 |
|
|
|
0x0 |
[rxpll_range_high_speed_vco_d1] High Speed Mode (Above
3.125Gb/s, VCO divide by 1) |
|
|
|
|
0x1 |
[rxpll_range_medium_speed_vco_d2] Medium Speed Mode
(1.56Gb/s-(3.125)Gb/s, VCO divide by 2) |
|
|
|
|
0x2 |
[rxpll_range_low_speed_vco_d4] Low Speed Mode (780Mb/s-3.125Gb/s,
VCO divide by 4) |
|
|
|
|
0x3 |
[rxpll_range_low_speed_vco_d8] Low Speed Mode
(390Mb/s-1.56Gb/s, VCO divide by 8) |
|
|
12:8 |
RXPLL_REFDIV |
RX PLL reference reference
divide |
RW |
0x02 |
|
7:0 |
RXPLL_FBDIV |
RX PLL reference feedback divide (min 16) |
RW |
0x19 |
Address offset |
0x044 |
||
Physical address |
0x0108 4044 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8044 |
serdes_2_PMA_LANE3 |
||
0x0108 2044 |
serdes_1_PMA_LANE1 |
||
0x0120 8044 |
serdes_3_PMA_LANE3 |
||
0x0104 4044 |
serdes_0_PMA_LANE2 |
||
0x0120 2044 |
serdes_3_PMA_LANE1 |
||
0x0108 1044 |
serdes_1_PMA_LANE0 |
||
0x0104 2044 |
serdes_0_PMA_LANE1 |
||
0x0110 1044 |
serdes_2_PMA_LANE0 |
||
0x0110 4044 |
serdes_2_PMA_LANE2 |
||
0x0104 8044 |
serdes_0_PMA_LANE3 |
||
0x0110 2044 |
serdes_2_PMA_LANE1 |
||
0x0108 8044 |
serdes_1_PMA_LANE3 |
||
0x0120 4044 |
serdes_3_PMA_LANE2 |
||
0x0104 1044 |
serdes_0_PMA_LANE0 |
||
0x0120 1044 |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer Test Bus |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:25 |
Reserved |
|
RO |
0x00 |
|
24 |
RXDTESTOUT |
Digital test bus output |
RO |
0 |
|
23:20 |
Reserved |
|
RO |
0x0 |
|
19:17 |
RXDTESTSEL |
Digital test bus select for RX channel |
RW |
0x0 |
|
|
|
0x0 |
[rxdtest_logic0_sel] Select core VSS for RX digital test |
|
|
|
|
0x1 |
[rxdtest_logic1_sel] Select core VDD for RX digital test |
|
|
|
|
0x2 |
[rxdtest_rxpll_lock_sel] Select
RXPLL Lock signal for RX digital test |
|
|
|
|
0x3 |
[rxdtest_rxpll_cdrmode_sel]
Select RXPLL CDRMODE signal for RX digital test |
|
|
|
|
0x4 |
[rxdtest_div_feedback_clock_sel]
Select divided feedback clock (half PFD rate) for RX digital test |
|
|
|
|
0x5 |
[rxdtest_rxseout_sel] Select
RXSEOUT test signal for RX digital test |
|
|
|
|
0x6 |
[rxdtest_rx_ref_clk_sel] Select
RX reference clock for RX digital test |
|
|
|
|
0x7 |
[rxdtest_pll_reset_lock_sel]
Select PLL reset lock signal for RX digital test |
|
|
16 |
RXDTESTEN |
Digital test bus enable for RX
channel |
RW |
0 |
|
|
|
0 |
[rx_digital_test_disabled]
Disables Digital test bus for RX channel |
|
|
|
|
1 |
[rx_digital_test_enabled]
Enables Digital test bus for RX channel |
|
|
15:11 |
Reserved |
|
RO |
0x00 |
|
10:8 |
RXATESTSEL |
Analog test bus select for RX channel |
RW |
0x0 |
|
|
|
0x0 |
[rxatest_common_mode_resistor_output_sel]
Select Common mode resistor output level for RX analog test |
|
|
|
|
0x1 |
[rxatest_40ua_bandgap_current_sel] Select 40uA bandgap
current for RX analog test |
|
|
|
|
0x2 |
[rxatest_em_reg_phase_rotator_supply_sel]
Select regulated phase rotator supply for EM for RX analog test |
|
|
|
|
0x3 |
[rxatest_dfe_reg_phase_rotator_supply_sel]
Select regulated phase rotator supply for EM for RX analog test |
|
|
|
|
0x4 |
[rxatest_vco_replica_current_sel]
Select VCO replica for RX analog test |
|
|
|
|
0x5 |
[rxatest_vsss_sel] Select VSSS
ground for RX analog test |
|
|
|
|
0x6 |
[rxatest_logic1_level_sel] Select Logic 1 level for RX
analog test |
|
|
|
|
0x7 |
[rxatest_vddhv_sel] Select VDDHV
supply for RX analog test |
|
|
7:1 |
Reserved |
|
RO |
0x00 |
|
0 |
RXATESTEN |
Analog test bus enable for RX
channel |
RW |
0 |
|
|
|
0 |
[rx_analog_test_disabled]
Disables Analog test bus for RX channel |
|
|
|
|
1 |
[rx_analog_test_enabled] Enables
Analog test bus for RX channel |
|
Address offset |
0x048 |
||
Physical address |
0x0108 4048 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8048 |
serdes_2_PMA_LANE3 |
||
0x0108 2048 |
serdes_1_PMA_LANE1 |
||
0x0120 8048 |
serdes_3_PMA_LANE3 |
||
0x0104 4048 |
serdes_0_PMA_LANE2 |
||
0x0120 2048 |
serdes_3_PMA_LANE1 |
||
0x0108 1048 |
serdes_1_PMA_LANE0 |
||
0x0104 2048 |
serdes_0_PMA_LANE1 |
||
0x0110 1048 |
serdes_2_PMA_LANE0 |
||
0x0110 4048 |
serdes_2_PMA_LANE2 |
||
0x0104 8048 |
serdes_0_PMA_LANE3 |
||
0x0110 2048 |
serdes_2_PMA_LANE1 |
||
0x0108 8048 |
serdes_1_PMA_LANE3 |
||
0x0120 4048 |
serdes_3_PMA_LANE2 |
||
0x0104 1048 |
serdes_0_PMA_LANE0 |
||
0x0120 1048 |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer Clock
Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:9 |
Reserved |
|
RO |
0x00 0000 |
|
8 |
RXBYPASSEN |
Enable RXP/RXN to RXSEOUT path |
RW |
0 |
|
|
|
0 |
[rxdata_to_rxseout_disabled]
Disables RX differential data (P/N) to RXSEOUT signal ended data path |
|
|
|
|
1 |
[rxdata_to_rxseout_enabled]
Enables RX differential data (P/N) to RXSEOUT signal ended data path |
|
|
7 |
DATALOCKDIVEN |
Enable divide-by-32 path from Rx
data to CDR reference clock when in "DATALOCKEN" mode. |
RW |
0 |
|
|
|
0 |
[div_32_datapath_cdrrefclk_disabled] Disables divide-by-32
path from Rx data to CDR reference clock when Rx Reference Clock is embedded
in Rx data (DATALOCKEN = 1) |
|
|
|
|
1 |
[div_32_datapath_cdrrefclk_enabled] Enables divide-by-32 path from Rx data to CDR reference clock when Rx Reference
Clock is embedded in Rx data (DATALOCKEN = 1) |
|
|
6 |
DATALOCKEN |
Enables the mode where the Reference Clock is embedded
within the Rx data stream during training |
RW |
0 |
|
|
|
0 |
[lock_cdr_data_mode_disabled]
Disables Reference clock embedded in Rx data mode (Reference clock comes from
normal Rx Reference clock input) |
|
|
|
|
1 |
[lock_cdr_data_mode_enabled] Enalbes Reference clock embedded in Rx data mode |
|
|
5:3 |
DESMODE |
De-Serializer Mode Control |
RW |
0x7 |
|
|
|
0x0 |
[desmode_data_width_8bit_sel] Select 8-bit data width for
De-Serialization |
|
|
|
|
0x1 |
[desmode_data_width_10bit_sel] Select 10-bit data width
for De-Serialization |
|
|
|
|
0x2 |
[desmode_data_width_8bit_sel2] Select 8-bit data width for
De-Serialization |
|
|
|
|
0x3 |
[desmode_data_width_10bit_sel2] Select 10-bit data width
for De-Serialization |
|
|
|
|
0x4 |
[desmode_data_width_16bit_sel] Select 16-bit data width
for De-Serialization |
|
|
|
|
0x5 |
[desmode_data_width_20bit_sel] Select 20-bit data width
for De-Serialization |
|
|
|
|
0x6 |
[desmode_data_width_32bit_sel] Select 32-bit data width
for De-Serialization |
|
|
|
|
0x7 |
[desmode_data_width_40bit_sel] Select 40-bit data width
for De-Serialization |
|
|
2:0 |
RXREFCLK_SEL |
RX PLL Reference Clock Select |
RW |
0x4 |
|
|
|
0x0 |
[rxrefclk_rxrefclk_sel] Select
RX reference clock input from fabric for RX PLL reference clock input |
|
|
|
|
0x1 |
[rxrefclk_cascade_clk_in_sm_sel]
Select soft macro cascade clock input for RX PLL reference clock input |
|
|
|
|
0x2 |
[rxrefclk_extpll_dualclk0_in_sel] Select external PLL dual
clock 0 input for RX PLL reference clock input |
|
|
|
|
0x3 |
[rxrefclk_extpll_dualclk1_in_sel] Select external PLL dual
clock 1 input for RX PLL reference clock input |
|
|
|
|
0x4 |
[rxrefclk_txpll_dualclk0_in_sel] Select internal TX PLL
dual clock 0 input for RX PLL reference clock input |
|
|
|
|
0x5 |
[rxrefclk_txpll_dualclk1_in_sel] Select internal TX PLL
dual clock 1 input for RX PLL reference clock input |
|
|
|
|
0x6 |
[rxrefclk_txpll_cascade_clk_in_hm_sel]
Select hard macro cascade clock input for RX PLL reference clock input |
|
|
|
|
0x7 |
[rxrefclk_tie_low_sel] Select
tie low (1'b0) for RX PLL reference clock input |
|
Address offset |
0x04C |
||
Physical address |
0x0108 404C |
Instance |
serdes_1_PMA_LANE2 |
0x0110 804C |
serdes_2_PMA_LANE3 |
||
0x0108 204C |
serdes_1_PMA_LANE1 |
||
0x0120 804C |
serdes_3_PMA_LANE3 |
||
0x0104 404C |
serdes_0_PMA_LANE2 |
||
0x0120 204C |
serdes_3_PMA_LANE1 |
||
0x0108 104C |
serdes_1_PMA_LANE0 |
||
0x0104 204C |
serdes_0_PMA_LANE1 |
||
0x0110 104C |
serdes_2_PMA_LANE0 |
||
0x0110 404C |
serdes_2_PMA_LANE2 |
||
0x0104 804C |
serdes_0_PMA_LANE3 |
||
0x0110 204C |
serdes_2_PMA_LANE1 |
||
0x0108 804C |
serdes_1_PMA_LANE3 |
||
0x0120 404C |
serdes_3_PMA_LANE2 |
||
0x0104 104C |
serdes_0_PMA_LANE0 |
||
0x0120 104C |
serdes_3_PMA_LANE0 |
||
Description |
Deserializer RESET
& PD |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:6 |
Reserved |
|
RO |
0x000 0000 |
|
5 |
RESET_FIFO |
Reset FIFO |
RW |
1 |
|
|
|
0 |
[fifo_reset_deasserted] FIFO
reset is deasserted |
|
|
|
|
1 |
[fifo_reset_asserted] FIFO reset
is asserted |
|
|
4 |
RCVEN |
Receiver Enable |
RW |
0 |
|
|
|
0 |
[receiver_disabled] Disables
receiver |
|
|
|
|
1 |
[receiver_enabled] Enables
receiver |
|
|
3 |
PDEM |
Powerdown control
for the Eye Monitor |
RW |
1 |
|
|
|
0 |
[eye_monitor_powerdown_off] DFE
is in power up |
|
|
|
|
1 |
[eye_monitor_powerdown_on] DFE
is in power down |
|
|
2 |
PDDFE |
Powerdown control
for the DFE |
RW |
1 |
|
|
|
0 |
[dfe_powerdown_off] DFE is in
power up |
|
|
|
|
1 |
[dfe_powerdown_on] DFE is in
power down |
|
|
1 |
RESETDES |
Reset all deserializers for the
channel. Acti ve High. |
RW |
1 |
|
|
|
0 |
[rx_reset_deasserted] RX reset
is deasserted |
|
|
|
|
1 |
[rx_reset_asserted] RX reset is
asserted |
|
|
0 |
RXPD |
Receiver Power down / reset |
RW |
1 |
|
|
|
0 |
[rx_powerdown_off] RX is in
power up |
|
|
|
|
1 |
[rx_powerdown_on] RX is in power
down |
|
Address offset |
0x050 |
||
Physical address |
0x0108 4050 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8050 |
serdes_2_PMA_LANE3 |
||
0x0108 2050 |
serdes_1_PMA_LANE1 |
||
0x0120 8050 |
serdes_3_PMA_LANE3 |
||
0x0104 4050 |
serdes_0_PMA_LANE2 |
||
0x0120 2050 |
serdes_3_PMA_LANE1 |
||
0x0108 1050 |
serdes_1_PMA_LANE0 |
||
0x0104 2050 |
serdes_0_PMA_LANE1 |
||
0x0110 1050 |
serdes_2_PMA_LANE0 |
||
0x0110 4050 |
serdes_2_PMA_LANE2 |
||
0x0104 8050 |
serdes_0_PMA_LANE3 |
||
0x0110 2050 |
serdes_2_PMA_LANE1 |
||
0x0108 8050 |
serdes_1_PMA_LANE3 |
||
0x0120 4050 |
serdes_3_PMA_LANE2 |
||
0x0104 1050 |
serdes_0_PMA_LANE0 |
||
0x0120 1050 |
serdes_3_PMA_LANE0 |
||
Description |
Deserializer RTL Error
Check |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:16 |
Reserved |
|
RO |
0x0000 |
|
15:8 |
PRBSERR_COUNT |
PRBS error count |
RO |
0x00 |
|
7:5 |
Reserved |
|
RO |
0x0 |
|
4 |
PRBSMON_RXPLL_LOCK |
RX PLL lock indication input for CDR |
RO |
0 |
|
3:2 |
Reserved |
|
RO |
0x0 |
|
1 |
ERROROUT |
PRBS raw error information |
RO |
0 |
|
0 |
READ_ERROR |
Read PRBS errors |
RW |
0 |
|
|
|
0 |
[read_prbs_error_disabled]
Disables reading PRBS error |
|
|
|
|
1 |
[read_prbs_error_enabled]
Enables reading PRBS error |
|
Address offset |
0x054 |
||
Physical address |
0x0108 4054 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8054 |
serdes_2_PMA_LANE3 |
||
0x0108 2054 |
serdes_1_PMA_LANE1 |
||
0x0120 8054 |
serdes_3_PMA_LANE3 |
||
0x0104 4054 |
serdes_0_PMA_LANE2 |
||
0x0120 2054 |
serdes_3_PMA_LANE1 |
||
0x0108 1054 |
serdes_1_PMA_LANE0 |
||
0x0104 2054 |
serdes_0_PMA_LANE1 |
||
0x0110 1054 |
serdes_2_PMA_LANE0 |
||
0x0110 4054 |
serdes_2_PMA_LANE2 |
||
0x0104 8054 |
serdes_0_PMA_LANE3 |
||
0x0110 2054 |
serdes_2_PMA_LANE1 |
||
0x0108 8054 |
serdes_1_PMA_LANE3 |
||
0x0120 4054 |
serdes_3_PMA_LANE2 |
||
0x0104 1054 |
serdes_0_PMA_LANE0 |
||
0x0120 1054 |
serdes_3_PMA_LANE0 |
||
Description |
Deserializer RXPLL
Dividers for PCIE 1 & 2 mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31 |
Reserved |
|
RO |
0 |
|
30:29 |
PCIE2_RXPLL_RANGE |
For PCIE Gen2 (5.0 GT/s) |
RW |
0x0 |
|
|
|
0x0 |
[pcie2_rxpll_range_high_speed_vco_d1] High Speed Mode
(Above 3.125Gb/s, VCO divide by 1) for PCIe Gen2 Mode (5.0 GT/s) |
|
|
|
|
0x1 |
[pcie2_rxpll_range_medium_speed_vco_d2] Medium Speed Mode
(1.56Gb/s-(3.125)Gb/s, VCO divide by 2) for PCIe
Gen2 Mode (5.0 GT/s) |
|
|
|
|
0x2 |
[pcie2_rxpll_range_low_speed_vco_d4] Low Speed Mode
(780Mb/s-3.125Gb/s, VCO divide by 4) for PCIe Gen2 Mode (5.0 GT/s) |
|
|
|
|
0x3 |
[pcie2_rxpll_range_low_speed_vco_d8] Low Speed Mode
(390Mb/s-1.56Gb/s, VCO divide by 8) for PCIe Gen2 Mode (5.0 GT/s) |
|
|
28:24 |
PCIE2_RXPLL_REFDIV |
For PCIE Gen2 (5.0 GT/s) |
RW |
0x02 |
|
23:16 |
PCIE2_RXPLL_FBDIV |
For PCIE Gen2 (5.0 GT/s) |
RW |
0x32 |
|
15 |
Reserved |
|
RO |
0 |
|
14:13 |
PCIE1_RXPLL_RANGE |
For PCIE Gen1 (2.5 GT/s) |
RW |
0x1 |
|
|
|
0x0 |
[pcie1_rxpll_range_high_speed_vco_d1] High Speed Mode
(Above 3.125Gb/s, VCO divide by 1) for PCIe Gen1 Mode (2.5 GT/s) |
|
|
|
|
0x1 |
[pcie1_rxpll_range_medium_speed_vco_d2] Medium Speed Mode
(1.56Gb/s-(3.125)Gb/s, VCO divide by 2) for PCIe
Gen1 Mode (2.5 GT/s) |
|
|
|
|
0x2 |
[pcie1_rxpll_range_low_speed_vco_d4] Low Speed Mode
(780Mb/s-3.125Gb/s, VCO divide by 4) for PCIe Gen1 Mode (2.5 GT/s) |
|
|
|
|
0x3 |
[pcie1_rxpll_range_low_speed_vco_d8] Low Speed Mode
(390Mb/s-1.56Gb/s, VCO divide by 8) for PCIe Gen1 Mode (2.5 GT/s) |
|
|
12:8 |
PCIE1_RXPLL_REFDIV |
For PCIE Gen1 (2.5 GT/s) |
RW |
0x02 |
|
7:0 |
PCIE1_RXPLL_FBDIV |
For PCIE Gen1 (2.5 GT/s) |
RW |
0x19 |
Address offset |
0x058 |
||
Physical address |
0x0108 4058 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8058 |
serdes_2_PMA_LANE3 |
||
0x0108 2058 |
serdes_1_PMA_LANE1 |
||
0x0120 8058 |
serdes_3_PMA_LANE3 |
||
0x0104 4058 |
serdes_0_PMA_LANE2 |
||
0x0120 2058 |
serdes_3_PMA_LANE1 |
||
0x0108 1058 |
serdes_1_PMA_LANE0 |
||
0x0104 2058 |
serdes_0_PMA_LANE1 |
||
0x0110 1058 |
serdes_2_PMA_LANE0 |
||
0x0110 4058 |
serdes_2_PMA_LANE2 |
||
0x0104 8058 |
serdes_0_PMA_LANE3 |
||
0x0110 2058 |
serdes_2_PMA_LANE1 |
||
0x0108 8058 |
serdes_1_PMA_LANE3 |
||
0x0120 4058 |
serdes_3_PMA_LANE2 |
||
0x0104 1058 |
serdes_0_PMA_LANE0 |
||
0x0120 1058 |
serdes_3_PMA_LANE0 |
||
Description |
Deserializer RXPLL
Dividers for SATA 1 & 2 mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31 |
Reserved |
|
RO |
0 |
|
30:29 |
SATA2_RXPLL_RANGE |
For SATA 2.0 Mode (3.0 Gb/s) |
RW |
0x1 |
|
|
|
0x0 |
[sata2_rxpll_range_high_speed_vco_d1] High Speed Mode
(Above 3.125Gb/s, VCO divide by 1) for SATA 2.0 Mode (3.0 Gb/s) |
|
|
|
|
0x1 |
[sata2_rxpll_range_medium_speed_vco_d2] Medium Speed Mode
(1.56Gb/s-(3.125)Gb/s, VCO divide by 2) for SATA 2.0
Mode (3.0 Gb/s) |
|
|
|
|
0x2 |
[sata2_rxpll_range_low_speed_vco_d4] Low Speed Mode (780Mb/s-3.125Gb/s,
VCO divide by 4) for SATA 2.0 Mode (3.0 Gb/s) |
|
|
|
|
0x3 |
[sata2_rxpll_range_low_speed_vco_d8] Low Speed Mode
(390Mb/s-1.56Gb/s, VCO divide by 8) for SATA 2.0 Mode (3.0 Gb/s) |
|
|
28:24 |
SATA2_RXPLL_REFDIV |
For SATA 2.0 Mode (3.0 Gb/s) |
RW |
0x02 |
|
23:16 |
SATA2_RXPLL_FBDIV |
For SATA 2.0 Mode (3.0 Gb/s) |
RW |
0x18 |
|
15 |
Reserved |
|
RO |
0 |
|
14:13 |
SATA1_RXPLL_RANGE |
For SATA 1.0 Mode (1.5 Gb/s) |
RW |
0x2 |
|
|
|
0x0 |
[sata1_rxpll_range_high_speed_vco_d1] High Speed Mode
(Above 3.125Gb/s, VCO divide by 1) for SATA 1.0 Mode (1.5 Gb/s) |
|
|
|
|
0x1 |
[sata1_rxpll_range_medium_speed_vco_d2] Medium Speed Mode
(1.56Gb/s-(3.125)Gb/s, VCO divide by 2) for SATA 1.0
Mode (1.5 Gb/s) |
|
|
|
|
0x2 |
[sata1_rxpll_range_low_speed_vco_d4] Low Speed Mode
(780Mb/s-3.125Gb/s, VCO divide by 4) for SATA 1.0 Mode (1.5 Gb/s) |
|
|
|
|
0x3 |
[sata1_rxpll_range_low_speed_vco_d8] Low Speed Mode
(390Mb/s-1.56Gb/s, VCO divide by 8) for SATA 1.0 Mode (1.5 Gb/s) |
|
|
12:8 |
SATA1_RXPLL_REFDIV |
For SATA 1.0 Mode (1.5 Gb/s) |
RW |
0x04 |
|
7:0 |
SATA1_RXPLL_FBDIV |
For SATA 1.0 Mode (1.5 Gb/s) |
RW |
0x18 |
Address offset |
0x05C |
||
Physical address |
0x0108 405C |
Instance |
serdes_1_PMA_LANE2 |
0x0110 805C |
serdes_2_PMA_LANE3 |
||
0x0108 205C |
serdes_1_PMA_LANE1 |
||
0x0120 805C |
serdes_3_PMA_LANE3 |
||
0x0104 405C |
serdes_0_PMA_LANE2 |
||
0x0120 205C |
serdes_3_PMA_LANE1 |
||
0x0108 105C |
serdes_1_PMA_LANE0 |
||
0x0104 205C |
serdes_0_PMA_LANE1 |
||
0x0110 105C |
serdes_2_PMA_LANE0 |
||
0x0110 405C |
serdes_2_PMA_LANE2 |
||
0x0104 805C |
serdes_0_PMA_LANE3 |
||
0x0110 205C |
serdes_2_PMA_LANE1 |
||
0x0108 805C |
serdes_1_PMA_LANE3 |
||
0x0120 405C |
serdes_3_PMA_LANE2 |
||
0x0104 105C |
serdes_0_PMA_LANE0 |
||
0x0120 105C |
serdes_3_PMA_LANE0 |
||
Description |
Deserializer RXPLL
Dividers for SATA 3 mode |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:15 |
Reserved |
|
RO |
0x0 0000 |
|
14:13 |
SATA3_RXPLL_RANGE |
For SATA 3.0 Mode (6.0 Gb/s) |
RW |
0x0 |
|
|
|
0x0 |
[sata3_rxpll_range_high_speed_vco_d1] High Speed Mode
(Above 3.125Gb/s, VCO divide by 1) for SATA 3.0 Mode (6.0 Gb/s) |
|
|
|
|
0x1 |
[sata3_rxpll_range_medium_speed_vco_d2] Medium Speed Mode
(1.56Gb/s-(3.125)Gb/s, VCO divide by 2) for SATA 3.0
Mode (6.0 Gb/s) |
|
|
|
|
0x2 |
[sata3_rxpll_range_low_speed_vco_d4] Low Speed Mode
(780Mb/s-3.125Gb/s, VCO divide by 4) for SATA 3.0 Mode (6.0 Gb/s) |
|
|
|
|
0x3 |
[sata3_rxpll_range_low_speed_vco_d8] Low Speed Mode
(390Mb/s-1.56Gb/s, VCO divide by 8) for SATA 3.0 Mode (6.0 Gb/s) |
|
|
12:8 |
SATA3_RXPLL_REFDIV |
For SATA 3.0 Mode (6.0 Gb/s) |
RW |
0x02 |
|
7:0 |
SATA3_RXPLL_FBDIV |
For SATA 3.0 Mode (6.0 Gb/s) |
RW |
0x30 |
Address offset |
0x070 |
||
Physical address |
0x0108 4070 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8070 |
serdes_2_PMA_LANE3 |
||
0x0108 2070 |
serdes_1_PMA_LANE1 |
||
0x0120 8070 |
serdes_3_PMA_LANE3 |
||
0x0104 4070 |
serdes_0_PMA_LANE2 |
||
0x0120 2070 |
serdes_3_PMA_LANE1 |
||
0x0108 1070 |
serdes_1_PMA_LANE0 |
||
0x0104 2070 |
serdes_0_PMA_LANE1 |
||
0x0110 1070 |
serdes_2_PMA_LANE0 |
||
0x0110 4070 |
serdes_2_PMA_LANE2 |
||
0x0104 8070 |
serdes_0_PMA_LANE3 |
||
0x0110 2070 |
serdes_2_PMA_LANE1 |
||
0x0108 8070 |
serdes_1_PMA_LANE3 |
||
0x0120 4070 |
serdes_3_PMA_LANE2 |
||
0x0104 1070 |
serdes_0_PMA_LANE0 |
||
0x0120 1070 |
serdes_3_PMA_LANE0 |
||
Description |
Serializer Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:15 |
Reserved |
|
RO |
0x0 0000 |
|
14:12 |
HSLPBK_SEL |
High speed internal loopback serializer unit select |
RW |
0x0 |
|
11 |
HSLPBKEN |
Near-End High Speed loopback enable |
RW |
0 |
|
|
|
0 |
[near_end_high_speed_lpbk_disabled]
Disables Near-End High speed Loopback |
|
|
|
|
1 |
[near_end_high_speed_lpbk_enabled]
Enables Near-End High speed Loopback |
|
|
10 |
NLPBK_EN |
Near-End T-gate Loopback enable |
RW |
0 |
|
|
|
0 |
[near_end_tgate_lpbk_disabled]
Disables Near-End T-gate Loopback |
|
|
|
|
1 |
[near_end_tgate_lpbk_enabled]
Enables Near-End T-gate Loopback |
|
|
9 |
CMSTEP |
Step the common mode of TX to VDD |
RW |
0 |
|
|
|
0 |
[cmn_mode_step_func_disabled]
Disables common mode step function of TX |
|
|
|
|
1 |
[cmn_mode_step_func_enabled]
Enables common mode step function of TX to VDD |
|
|
8 |
CMSTEP_VALUE |
Voltage to step to when CMSTEP is asserted |
RW |
0 |
|
|
|
0 |
[cmn_mode_step_value_vsss_sel]
Select VSSS for voltage to step to when CMSTEP is asserted. |
|
|
|
|
1 |
[cmn_mode_step_value_vdda_sel] Select
VDDA for voltage to step to when CMSTEP is asserted. |
|
|
7:1 |
Reserved |
|
RO |
0x00 |
|
0 |
TXVBGREF_SEL |
Select VBG Reference for PLL voltage regulator |
RW |
0 |
|
|
|
0 |
[tx_vbgref_vdda_pll_voltreg_sel]
Select VDDA for VBG Reference for PLL voltage regulator |
|
|
|
|
1 |
[tx_vbgref_1p1v_pll_voltreg_sel] Select 1.1V for VBG
Reference for PLL voltage regulator |
|
Address offset |
0x074 |
||
Physical address |
0x0108 4074 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8074 |
serdes_2_PMA_LANE3 |
||
0x0108 2074 |
serdes_1_PMA_LANE1 |
||
0x0120 8074 |
serdes_3_PMA_LANE3 |
||
0x0104 4074 |
serdes_0_PMA_LANE2 |
||
0x0120 2074 |
serdes_3_PMA_LANE1 |
||
0x0108 1074 |
serdes_1_PMA_LANE0 |
||
0x0104 2074 |
serdes_0_PMA_LANE1 |
||
0x0110 1074 |
serdes_2_PMA_LANE0 |
||
0x0110 4074 |
serdes_2_PMA_LANE2 |
||
0x0104 8074 |
serdes_0_PMA_LANE3 |
||
0x0110 2074 |
serdes_2_PMA_LANE1 |
||
0x0108 8074 |
serdes_1_PMA_LANE3 |
||
0x0120 4074 |
serdes_3_PMA_LANE2 |
||
0x0104 1074 |
serdes_0_PMA_LANE0 |
||
0x0120 1074 |
serdes_3_PMA_LANE0 |
||
Description |
Serializer Clock Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:7 |
Reserved |
|
RO |
0x000 0000 |
|
6:4 |
SERMODE |
Serializer Mode Control |
RW |
0x7 |
|
|
|
0x0 |
[sermode_data_width_8bit_sel] Select 8-bit data width for
Serialization |
|
|
|
|
0x1 |
[sermode_data_width_10bit_sel] Select 10-bit data width
for Serialization |
|
|
|
|
0x2 |
[sermode_data_width_8bit_sel2] Select 8-bit data width for
Serialization |
|
|
|
|
0x3 |
[sermode_data_width_10bit_sel2] Select 10-bit data width
for Serialization |
|
|
|
|
0x4 |
[sermode_data_width_16bit_sel] Select 16-bit data width
for Serialization |
|
|
|
|
0x5 |
[sermode_data_width_20bit_sel] Select 20-bit data width
for Serialization |
|
|
|
|
0x6 |
[sermode_data_width_32bit_sel] Select 32-bit data width
for Serialization |
|
|
|
|
0x7 |
[sermode_data_width_40bit_sel] Select 40-bit data width
for Serialization |
|
|
3 |
TXBITCLKSEL |
Transmitter bit clock select |
RW |
0 |
|
|
|
0 |
[tx_bit_clock_int_txpll_sel]
Select Internal TXPLL FOUT for TX bit clock |
|
|
|
|
1 |
[tx_bit_clock_ext_txpll_sel]
Select External TXPLL FOUT for TX bit clock |
|
|
2:1 |
TXPOSTDIV |
Serializer Per-Channel Division |
RW |
0x0 |
|
|
|
0x0 |
[tx_post_divider_div_by_2] Set TX post divider to
divide-by-2 mode |
|
|
|
|
0x1 |
[tx_post_divider_div_by_4] Set TX post divider to
divide-by-4 mode |
|
|
|
|
0x2 |
[tx_post_divider_div_by_8] Set TX post divider to
divide-by-8 mode |
|
|
|
|
0x3 |
[tx_post_divider_div_by_11] Set TX post divider to
divide-by-11 mode |
|
|
0 |
TXPOSTDIVEN |
Serializer post-divider enable |
RW |
0 |
|
|
|
0 |
[tx_post_divider_disabled]
Disables Serializer post-divider. Sets divide-by-1 mode. |
|
|
|
|
1 |
[tx_post_divider_enabled]
Enables Serializer post-divider. TXPOSTDIV sets the divider value. |
|
Address offset |
0x078 |
||
Physical address |
0x0108 4078 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8078 |
serdes_2_PMA_LANE3 |
||
0x0108 2078 |
serdes_1_PMA_LANE1 |
||
0x0120 8078 |
serdes_3_PMA_LANE3 |
||
0x0104 4078 |
serdes_0_PMA_LANE2 |
||
0x0120 2078 |
serdes_3_PMA_LANE1 |
||
0x0108 1078 |
serdes_1_PMA_LANE0 |
||
0x0104 2078 |
serdes_0_PMA_LANE1 |
||
0x0110 1078 |
serdes_2_PMA_LANE0 |
||
0x0110 4078 |
serdes_2_PMA_LANE2 |
||
0x0104 8078 |
serdes_0_PMA_LANE3 |
||
0x0110 2078 |
serdes_2_PMA_LANE1 |
||
0x0108 8078 |
serdes_1_PMA_LANE3 |
||
0x0120 4078 |
serdes_3_PMA_LANE2 |
||
0x0104 1078 |
serdes_0_PMA_LANE0 |
||
0x0120 1078 |
serdes_3_PMA_LANE0 |
||
Description |
Serializer Reset & PD |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:3 |
Reserved |
|
RO |
0x0000 0000 |
|
2 |
TXPD |
Power down / reset for serializer channels |
RW |
1 |
|
|
|
0 |
[tx_powerdown_off] TX is in
power up |
|
|
|
|
1 |
[tx_powerdown_on] TX is in power
down |
|
|
1 |
RESETSER |
Serializer Reset |
RW |
1 |
|
|
|
0 |
[tx_reset_deasserted] TX reset
is deasserted |
|
|
|
|
1 |
[tx_reset_asserted] TX reset is
asserted |
|
|
0 |
RESETSEREN |
Enable for RESETSER logic |
RW |
0 |
|
|
|
0 |
[tx_reset_disabled] Disables TX
reset logic |
|
|
|
|
1 |
[tx_reset_enabled] Enables TX
reset logic |
|
Address offset |
0x07C |
||
Physical address |
0x0108 407C |
Instance |
serdes_1_PMA_LANE2 |
0x0110 807C |
serdes_2_PMA_LANE3 |
||
0x0108 207C |
serdes_1_PMA_LANE1 |
||
0x0120 807C |
serdes_3_PMA_LANE3 |
||
0x0104 407C |
serdes_0_PMA_LANE2 |
||
0x0120 207C |
serdes_3_PMA_LANE1 |
||
0x0108 107C |
serdes_1_PMA_LANE0 |
||
0x0104 207C |
serdes_0_PMA_LANE1 |
||
0x0110 107C |
serdes_2_PMA_LANE0 |
||
0x0110 407C |
serdes_2_PMA_LANE2 |
||
0x0104 807C |
serdes_0_PMA_LANE3 |
||
0x0110 207C |
serdes_2_PMA_LANE1 |
||
0x0108 807C |
serdes_1_PMA_LANE3 |
||
0x0120 407C |
serdes_3_PMA_LANE2 |
||
0x0104 107C |
serdes_0_PMA_LANE0 |
||
0x0120 107C |
serdes_3_PMA_LANE0 |
||
Description |
Serializer Driver Bypass |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:17 |
Reserved |
|
RO |
0x0000 |
|
16 |
BYPASSSER |
Bypass enable for output driver |
RW |
0 |
|
|
|
0 |
[tx_bypass_disabled] Disables TX
Bypass for output driver |
|
|
|
|
1 |
[tx_bypass_enabled] Enables TX
Bypass for output driver |
|
|
15:11 |
Reserved |
|
RO |
0x00 |
|
10 |
TX_BYPASS_SELECT |
Hard Macro BYPASS_VALUE Input Select |
RW |
0 |
|
|
|
0 |
[tx_bypass_rtl_bypass_value_sel]
Select Hard Macro bypass value from RTL Bypass Value |
|
|
|
|
1 |
[tx_bypass_deserializer_sel]
Select Hard Macro bypass value from de-serializer |
|
|
9:8 |
TX_BYPASS_SELECT_RTL |
RTL BYPASS_VALUE Input Select |
RW |
0x0 |
|
|
|
0x0 |
[tx_bypass_value_sel] Select
BYPASS_VALUE[7:0] for TX RTL BYPASS Value input |
|
|
|
|
0x1 |
[tx_bypass_0s_sel] Select 8'b0 for TX RTL BYPASS Value
input |
|
|
|
|
0x2 |
[tx_bypass_txpll_refclk_sel]
Select TXPLL Reference Clock for TX RTL BYPASS Value input |
|
|
|
|
0x3 |
[tx_bypass_0s_sel2] Select 8'b0 for TX RTL BYPASS Value
input |
|
|
7:0 |
BYPASS_VALUE |
Bypass value for each output driver segment (of 8) |
RW |
0x00 |
Address offset |
0x080 |
||
Physical address |
0x0108 4080 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8080 |
serdes_2_PMA_LANE3 |
||
0x0108 2080 |
serdes_1_PMA_LANE1 |
||
0x0120 8080 |
serdes_3_PMA_LANE3 |
||
0x0104 4080 |
serdes_0_PMA_LANE2 |
||
0x0120 2080 |
serdes_3_PMA_LANE1 |
||
0x0108 1080 |
serdes_1_PMA_LANE0 |
||
0x0104 2080 |
serdes_0_PMA_LANE1 |
||
0x0110 1080 |
serdes_2_PMA_LANE0 |
||
0x0110 4080 |
serdes_2_PMA_LANE2 |
||
0x0104 8080 |
serdes_0_PMA_LANE3 |
||
0x0110 2080 |
serdes_2_PMA_LANE1 |
||
0x0108 8080 |
serdes_1_PMA_LANE3 |
||
0x0120 4080 |
serdes_3_PMA_LANE2 |
||
0x0104 1080 |
serdes_0_PMA_LANE0 |
||
0x0120 1080 |
serdes_3_PMA_LANE0 |
||
Description |
Serializer RXDetect Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:24 |
Reserved |
|
RO |
0x00 |
|
23 |
RXDETECT_START |
Receiver detection start signal |
RW |
0 |
|
|
|
0 |
[tx_detect_rx_start_disabled]
Disables TX detect RX start |
|
|
|
|
1 |
[tx_detect_rx_start_enabled]
Enables TX detect RX start |
|
|
22 |
RX_DETECT_EN |
TX detect of RX enable |
RW |
0 |
|
|
|
0 |
[tx_detect_rx_disabled] Disables
TX detect RX function |
|
|
|
|
1 |
[tx_detect_rx_enabled] Enables
TX detect RX function |
|
|
21:8 |
RXDETECT_COUNT_THRESHOLD |
TX detect RX counter threshold for Deserializer
|
RW |
0x008A |
|
7:5 |
Reserved |
|
RO |
0x0 |
|
4:0 |
RXDETECT_STEP_WAIT_COUNT |
Set wait duration after CMSTEP is asserted to ignore
RXDETOUT |
RW |
0x10 |
Address offset |
0x084 |
||
Physical address |
0x0108 4084 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8084 |
serdes_2_PMA_LANE3 |
||
0x0108 2084 |
serdes_1_PMA_LANE1 |
||
0x0120 8084 |
serdes_3_PMA_LANE3 |
||
0x0104 4084 |
serdes_0_PMA_LANE2 |
||
0x0120 2084 |
serdes_3_PMA_LANE1 |
||
0x0108 1084 |
serdes_1_PMA_LANE0 |
||
0x0104 2084 |
serdes_0_PMA_LANE1 |
||
0x0110 1084 |
serdes_2_PMA_LANE0 |
||
0x0110 4084 |
serdes_2_PMA_LANE2 |
||
0x0104 8084 |
serdes_0_PMA_LANE3 |
||
0x0110 2084 |
serdes_2_PMA_LANE1 |
||
0x0108 8084 |
serdes_1_PMA_LANE3 |
||
0x0120 4084 |
serdes_3_PMA_LANE2 |
||
0x0104 1084 |
serdes_0_PMA_LANE0 |
||
0x0120 1084 |
serdes_3_PMA_LANE0 |
||
Description |
Serializer RXDetect Output |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
Reserved |
|
RO |
0x0000 |
15 |
RXDETECT_DONE |
Receiver detection RTL done signal |
RO |
0 |
14 |
RXDETOUT |
Output of clocked receiver detect sensor |
RO |
0 |
13:0 |
RXDETECT_COUNT |
Receiver detect RTL
duration count in TXPLL reference periods |
RO |
0x0000 |
Address offset |
0x088 |
||
Physical address |
0x0108 4088 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8088 |
serdes_2_PMA_LANE3 |
||
0x0108 2088 |
serdes_1_PMA_LANE1 |
||
0x0120 8088 |
serdes_3_PMA_LANE3 |
||
0x0104 4088 |
serdes_0_PMA_LANE2 |
||
0x0120 2088 |
serdes_3_PMA_LANE1 |
||
0x0108 1088 |
serdes_1_PMA_LANE0 |
||
0x0104 2088 |
serdes_0_PMA_LANE1 |
||
0x0110 1088 |
serdes_2_PMA_LANE0 |
||
0x0110 4088 |
serdes_2_PMA_LANE2 |
||
0x0104 8088 |
serdes_0_PMA_LANE3 |
||
0x0110 2088 |
serdes_2_PMA_LANE1 |
||
0x0108 8088 |
serdes_1_PMA_LANE3 |
||
0x0120 4088 |
serdes_3_PMA_LANE2 |
||
0x0104 1088 |
serdes_0_PMA_LANE0 |
||
0x0120 1088 |
serdes_3_PMA_LANE0 |
||
Description |
Serializer Static Pattern Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:20 |
Reserved |
|
RO |
0x000 |
19:0 |
STATIC_PATTERN_LSB |
Transmitter Static Pattern MSB Control |
RW |
0x0 0000 |
Address offset |
0x08C |
||
Physical address |
0x0108 408C |
Instance |
serdes_1_PMA_LANE2 |
0x0110 808C |
serdes_2_PMA_LANE3 |
||
0x0108 208C |
serdes_1_PMA_LANE1 |
||
0x0120 808C |
serdes_3_PMA_LANE3 |
||
0x0104 408C |
serdes_0_PMA_LANE2 |
||
0x0120 208C |
serdes_3_PMA_LANE1 |
||
0x0108 108C |
serdes_1_PMA_LANE0 |
||
0x0104 208C |
serdes_0_PMA_LANE1 |
||
0x0110 108C |
serdes_2_PMA_LANE0 |
||
0x0110 408C |
serdes_2_PMA_LANE2 |
||
0x0104 808C |
serdes_0_PMA_LANE3 |
||
0x0110 208C |
serdes_2_PMA_LANE1 |
||
0x0108 808C |
serdes_1_PMA_LANE3 |
||
0x0120 408C |
serdes_3_PMA_LANE2 |
||
0x0104 108C |
serdes_0_PMA_LANE0 |
||
0x0120 108C |
serdes_3_PMA_LANE0 |
||
Description |
Serializer Static Pattern Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:20 |
Reserved |
|
RO |
0x000 |
19:0 |
STATIC_PATTERN_MSB |
Transmitter Static Pattern MSB Control |
RW |
0x0 0000 |
Address offset |
0x090 |
||
Physical address |
0x0108 4090 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8090 |
serdes_2_PMA_LANE3 |
||
0x0108 2090 |
serdes_1_PMA_LANE1 |
||
0x0120 8090 |
serdes_3_PMA_LANE3 |
||
0x0104 4090 |
serdes_0_PMA_LANE2 |
||
0x0120 2090 |
serdes_3_PMA_LANE1 |
||
0x0108 1090 |
serdes_1_PMA_LANE0 |
||
0x0104 2090 |
serdes_0_PMA_LANE1 |
||
0x0110 1090 |
serdes_2_PMA_LANE0 |
||
0x0110 4090 |
serdes_2_PMA_LANE2 |
||
0x0104 8090 |
serdes_0_PMA_LANE3 |
||
0x0110 2090 |
serdes_2_PMA_LANE1 |
||
0x0108 8090 |
serdes_1_PMA_LANE3 |
||
0x0120 4090 |
serdes_3_PMA_LANE2 |
||
0x0104 1090 |
serdes_0_PMA_LANE0 |
||
0x0120 1090 |
serdes_3_PMA_LANE0 |
||
Description |
Serializer Termination Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:16 |
Reserved |
|
RO |
0x0000 |
|
15:12 |
TXRTRIM |
TX resistor trim |
RW |
0x7 |
|
|
|
0x0 |
[tx_resistor_trim_min] Select TX
resistor trim value to minimum (76 ohms) |
|
|
|
|
0xF |
[tx_resistor_trim_max] Select TX
resistor trim value to maximum(171 ohms) |
|
|
11 |
Reserved |
|
RO |
0 |
|
10:9 |
TXRTRIM_SEL |
Select TX resistor trim |
RW |
0x1 |
|
|
|
0x0 |
[tx_resistor_trim_rtermcal85_sel] Select RTERMCAL85
register value for TX resistor trim value |
|
|
|
|
0x1 |
[tx_resistor_trim_rtermcal100_sel] Select RTERMCAL100
register value for TX resistor trim value |
|
|
|
|
0x2 |
[tx_resistor_trim_rtermcal150_sel] Select RTERMCAL150
register value for TX resistor trim value |
|
|
|
|
0x3 |
[tx_resistor_trim_lane_txrtrim_sel]
Select Lane TXRTRIM register value for TX resistor trim value |
|
|
8 |
TXTEN |
TX back termination enable |
RW |
0 |
|
|
|
0 |
[tx_back_termination_disabled]
Disables TX back termination |
|
|
|
|
1 |
[tx_back_termination_enabled]
Enables TX back termination |
|
|
7:2 |
Reserved |
|
RO |
0x00 |
|
1:0 |
TXCM_LEVEL |
Transmitter DC Level |
RW |
0x0 |
|
|
|
0x0 |
[tx_cmn_mode_dc_level_0p525x_sel] Select 0.525*VDDA for TX
driver output common mode DC level |
|
|
|
|
0x1 |
[tx_cmn_mode_dc_level_0p6x_sel] Select 0.6*VDDA for TX
driver output common mode DC level |
|
|
|
|
0x2 |
[tx_cmn_mode_dc_level_0p7x_sel] Select 0.7*VDDA for TX
driver output common mode DC level |
|
|
|
|
0x3 |
[tx_cmn_mode_dc_level_0p8x_sel] Select 0.8*VDDA for TX
driver output common mode DC level |
|
Address offset |
0x094 |
||
Physical address |
0x0108 4094 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8094 |
serdes_2_PMA_LANE3 |
||
0x0108 2094 |
serdes_1_PMA_LANE1 |
||
0x0120 8094 |
serdes_3_PMA_LANE3 |
||
0x0104 4094 |
serdes_0_PMA_LANE2 |
||
0x0120 2094 |
serdes_3_PMA_LANE1 |
||
0x0108 1094 |
serdes_1_PMA_LANE0 |
||
0x0104 2094 |
serdes_0_PMA_LANE1 |
||
0x0110 1094 |
serdes_2_PMA_LANE0 |
||
0x0110 4094 |
serdes_2_PMA_LANE2 |
||
0x0104 8094 |
serdes_0_PMA_LANE3 |
||
0x0110 2094 |
serdes_2_PMA_LANE1 |
||
0x0108 8094 |
serdes_1_PMA_LANE3 |
||
0x0120 4094 |
serdes_3_PMA_LANE2 |
||
0x0104 1094 |
serdes_0_PMA_LANE0 |
||
0x0120 1094 |
serdes_3_PMA_LANE0 |
||
Description |
Serializer Test Bus |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:29 |
RXPKDETOUT_TO_DTEST_SEL |
Select Receiver Peak Detector Output to Digital Test Mux |
RW |
0x7 |
|
|
|
0x0 |
[rx_peak_detectout0_to_dtest_sel] Select RX Peak Detector
bit 0 for TX digital test |
|
|
|
|
0x1 |
[rx_peak_detectout1_to_dtest_sel] Select RX Peak Detector
bit 1 for TX digital test |
|
|
|
|
0x2 |
[rx_peak_detectout2_to_dtest_sel] Select RX Peak Detector
bit 2 for TX digital test |
|
|
|
|
0x3 |
[rx_peak_detectout3_to_dtest_sel] Select RX Peak Detector
bit 3 for TX digital test |
|
|
|
|
0x4 |
[rx_peak_detectout4_to_dtest_sel] Select RX Peak Detector
bit 4 for TX digital test |
|
|
|
|
0x5 |
[rx_peak_detectout5_to_dtest_sel] Select RX Peak Detector
bit 5 for TX digital test |
|
|
|
|
0x6 |
[rx_peak_detectout6_to_dtest_sel] Select RX Peak Detector
bit 6 for TX digital test |
|
|
|
|
0x7 |
[rxpkdetout_logic0_to_dtest_sel] Select Logic 0 for TX
digital test |
|
|
28:27 |
PRBSERR_TO_DTEST_SEL |
Select PRBS Error Source to Digital Test Mux |
RW |
0x0 |
|
|
|
0x0 |
[prbserr_cdr_to_dtest_sel]
Select CDR PRBS error for TX digital test |
|
|
|
|
0x1 |
[prbserr_dfe_to_dtest_sel]
Select DFE PRBS error for TX digital test |
|
|
|
|
0x2 |
[prbserr_em_to_dtest_sel] Select
Eye Monitor PRBS error for TX digital test |
|
|
|
|
0x3 |
[prbserr_em_compout_to_dtest_sel]
Select Eye Monitor Comparison out bit for TX digital test |
|
|
26:24 |
JTAG_TO_DTEST_SEL |
Select JTAG_OUT_LATCHED, JTAG_SET, and JTAG_CLEAR to the
DTESTSEL_RTLA Mux |
RW |
0x0 |
|
|
|
0x0 |
[jtag_to_dtest_ln3_sel0] Select jtag_out_latched_ln3[0],
jtag_set_ln3[0], jtag_clear_ln3[0] for jtag_out_latched,
jtag_set, and jtag_clear
for TX digital test |
|
|
|
|
0x1 |
[jtag_to_dtest_ln2_sel0] Select jtag_out_latched_ln2[0],
jtag_set_ln2[0], jtag_clear_ln2[0] for jtag_out_latched,
jtag_set, and jtag_clear
for TX digital test |
|
|
|
|
0x2 |
[jtag_to_dtest_ln1_sel0] Select jtag_out_latched_ln1[0],
jtag_set_ln1[0], jtag_clear_ln1[0] for jtag_out_latched,
jtag_set, and jtag_clear
for TX digital test |
|
|
|
|
0x3 |
[jtag_to_dtest_ln0_sel0] Select jtag_out_latched_ln0[0],
jtag_set_ln0[0], jtag_clear_ln0[0] for jtag_out_latched,
jtag_set, and jtag_clear
for TX digital test |
|
|
|
|
0x4 |
[jtag_to_dtest_ln3_sel1] Select jtag_out_latched_ln3[1],
jtag_set_ln3[1], jtag_clear_ln3[1] for jtag_out_latched,
jtag_set, and jtag_clear
for TX digital test |
|
|
|
|
0x5 |
[jtag_to_dtest_ln2_sel1] Select jtag_out_latched_ln2[1],
jtag_set_ln2[1], jtag_clear_ln2[1] for jtag_out_latched,
jtag_set, and jtag_clear
for TX digital test |
|
|
|
|
0x6 |
[jtag_to_dtest_ln1_sel1] Select jtag_out_latched_ln1[1],
jtag_set_ln1[1], jtag_clear_ln1[1] for jtag_out_latched,
jtag_set, and jtag_clear
for TX digital test |
|
|
|
|
0x7 |
[jtag_to_dtest_ln0_sel1] Select jtag_out_latched_ln0[1],
jtag_set_ln0[1], jtag_clear_ln0[1] for jtag_out_latched,
jtag_set, and jtag_clear
for TX digital test |
|
|
23:21 |
Reserved |
|
RO |
0x0 |
|
20:17 |
DTESTSEL_RTL |
RTL Digital Test Bus Select |
RW |
0x0 |
|
|
|
0x0 |
[txdtest_logic1_sel] Select Logic 1 level for TX digital
test |
|
|
|
|
0x1 |
[txdtest_logic0_sel] Select Logic 0 level for TX digital
test |
|
|
|
|
0x2 |
[txdtest_txpll_refclk_sel]
Select TX PLL reference clock for TX digital test |
|
|
|
|
0x3 |
[txdtest_txpll_lock_sel] Select
TX PLL lock for TX digital test |
|
|
|
|
0x4 |
[txdtest_local_prbs_error_sel]
Select local PRBS error for TX digital test |
|
|
|
|
0x5 |
[txdtest_neighbor_prbs_error_sel]
Select neighbor channel PRBS error for TX digital test |
|
|
|
|
0x6 |
[txdtest_rxpkdet_out_sel] Select
RX peak detector otuput for TX digital test |
|
|
|
|
0x7 |
[txdtest_rxdtestout_sel] Select
RX digital test out for TX digital test |
|
|
|
|
0x8 |
[txdtest_rxdetout_sel] Select RX
detect otuput for TX digital test |
|
|
|
|
0x9 |
[txdtest_cmstepout_neighbor_sel]
Select common mode step neighbor channel for TX digital test |
|
|
|
|
0xA |
[txdtest_jtag_out_latched_sel]
Select JTAG out latched for TX digital test |
|
|
|
|
0xB |
[txdtest_jtag_set_sel] Select JTAG
set for TX digital test |
|
|
|
|
0xC |
[txdtest_jtag_clear_sel] Select
JTAG clear for TX digital test |
|
|
|
|
0xD |
[txdtest_logic0_sel2] Select Logic 0 level for TX digital
test |
|
|
|
|
0xE |
[txdtest_logic0_sel3] Select Logic 0 level for TX digital
test |
|
|
|
|
0xF |
[txdtest_logic0_sel4] Select Logic 0 level for TX digital
test |
|
|
16 |
DTESTEN_RTL |
RTL Digital Test Bus Enable |
RW |
0 |
|
|
|
0 |
[tx_digital_test_disabled]
Disables digital test bus for TX channel |
|
|
|
|
1 |
[tx_digital_test_enabled]
Enables digital test bus for TX channel |
|
|
15:11 |
Reserved |
|
RO |
0x00 |
|
10:8 |
TXATESTSEL |
Serializer Analog Test Bus Select |
RW |
0x0 |
|
|
|
0x0 |
[txatest_16ua_ptat_current_sel] Select 16uA PTAT current
for TX analog test |
|
|
|
|
0x1 |
[txatest_8ua_ptat_current_sel] Select 8uA PTAT current for
TX analog test |
|
|
|
|
0x2 |
[txatest_common_mode_voltage_sel]
Select TX common mode voltage for TX analog test |
|
|
|
|
0x3 |
[txatest_10ua_bandgap_current_sel] Select 10uA bandgap
current for TX analog test |
|
|
|
|
0x4 |
[txatest_regulated_clock_supply_sel]
Select regulated clock supply for TX analog test |
|
|
|
|
0x5 |
[txatest_vsss_sel] Select VSSS
for TX analog test |
|
|
|
|
0x6 |
[txatest_logic1_sel] Select Logic 1 level for TX analog
test |
|
|
|
|
0x7 |
[txatest_vddhv_sel] Select VDDHV
for TX analog test |
|
|
7:1 |
Reserved |
|
RO |
0x00 |
|
0 |
TXATESTEN |
Analog test bus enable for TX
channel |
RW |
0 |
|
|
|
0 |
[tx_analog_test_disabled]
Disables Analog test bus for TX channel |
|
|
|
|
1 |
[tx_analog_test_enabled] Enables
Analog test bus for TX channel |
|
Address offset |
0x098 |
||
Physical address |
0x0108 4098 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8098 |
serdes_2_PMA_LANE3 |
||
0x0108 2098 |
serdes_1_PMA_LANE1 |
||
0x0120 8098 |
serdes_3_PMA_LANE3 |
||
0x0104 4098 |
serdes_0_PMA_LANE2 |
||
0x0120 2098 |
serdes_3_PMA_LANE1 |
||
0x0108 1098 |
serdes_1_PMA_LANE0 |
||
0x0104 2098 |
serdes_0_PMA_LANE1 |
||
0x0110 1098 |
serdes_2_PMA_LANE0 |
||
0x0110 4098 |
serdes_2_PMA_LANE2 |
||
0x0104 8098 |
serdes_0_PMA_LANE3 |
||
0x0110 2098 |
serdes_2_PMA_LANE1 |
||
0x0108 8098 |
serdes_1_PMA_LANE3 |
||
0x0120 4098 |
serdes_3_PMA_LANE2 |
||
0x0104 1098 |
serdes_0_PMA_LANE0 |
||
0x0120 1098 |
serdes_3_PMA_LANE0 |
||
Description |
Serializer Driver Data Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23:16 |
TXDATA_INV |
Invert data for each output driver segment (of 8) |
RW |
0x00 |
15:0 |
TXDEL |
Delay data for each output driver segment (of 8) |
RW |
0x0000 |
Address offset |
0x09C |
||
Physical address |
0x0108 409C |
Instance |
serdes_1_PMA_LANE2 |
0x0110 809C |
serdes_2_PMA_LANE3 |
||
0x0108 209C |
serdes_1_PMA_LANE1 |
||
0x0120 809C |
serdes_3_PMA_LANE3 |
||
0x0104 409C |
serdes_0_PMA_LANE2 |
||
0x0120 209C |
serdes_3_PMA_LANE1 |
||
0x0108 109C |
serdes_1_PMA_LANE0 |
||
0x0104 209C |
serdes_0_PMA_LANE1 |
||
0x0110 109C |
serdes_2_PMA_LANE0 |
||
0x0110 409C |
serdes_2_PMA_LANE2 |
||
0x0104 809C |
serdes_0_PMA_LANE3 |
||
0x0110 209C |
serdes_2_PMA_LANE1 |
||
0x0108 809C |
serdes_1_PMA_LANE3 |
||
0x0120 409C |
serdes_3_PMA_LANE2 |
||
0x0104 109C |
serdes_0_PMA_LANE0 |
||
0x0120 109C |
serdes_3_PMA_LANE0 |
||
Description |
Serializer Driver Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31 |
Reserved |
|
RO |
0 |
|
30:29 |
TXODRV |
Transmitter Overdrive Control |
RW |
0x0 |
|
|
|
0x0 |
[tx_overdrive_by_normal_sel]
Select normal setting for TX overdrive control |
|
|
|
|
0x1 |
[tx_overdrive_by_25pct_sel] Select + 25% for TX overdrive
control |
|
|
|
|
0x2 |
[tx_overdrive_by_50pct_sel] Select + 50% for TX overdrive
control |
|
|
|
|
0x3 |
[tx_overdrive_by_75pct_sel] Select + 75% for TX overdrive
control |
|
|
28:27 |
TXITRIM |
Overall current scaling for TX Driver |
RW |
0x0 |
|
|
|
0x0 |
[tx_drive_current_trim_m10pct_sel] Select - 10% overall
current scaling fro TX driver |
|
|
|
|
0x1 |
[tx_drive_current_trim_m5pct_sel] Select - 5% overall
current scaling fro TX driver |
|
|
|
|
0x2 |
[tx_drive_current_trim_nominal_sel]
Select nominal overall current scaling fro TX
driver |
|
|
|
|
0x3 |
[tx_drive_current_trim_5pct_sel] Select + 5% overall
current scaling fro TX driver |
|
|
26:24 |
TXDRV |
Enable for driver segments 2 to 8 (of 8) |
RW |
0x1 |
|
|
|
0x0 |
[tx_drive_segment1_enabled] Enables TX driver segment 1
(with TXPD = 0) |
|
|
|
|
0x1 |
[tx_drive_segment2_enabled] Enables TX driver segment 2 |
|
|
|
|
0x2 |
[tx_drive_segment3_enabled] Enables TX driver segment 3 |
|
|
|
|
0x3 |
[tx_drive_segment4_enabled] Enables TX driver segment 4 |
|
|
|
|
0x4 |
[tx_drive_segment5_enabled] Enables TX driver segment 5 |
|
|
|
|
0x5 |
[tx_drive_segment6_enabled] Enables TX driver segment 6 |
|
|
|
|
0x6 |
[tx_drive_segment7_enabled] Enables TX driver segment 7 |
|
|
|
|
0x7 |
[tx_drive_segment8_enabled] Enables TX driver segment 8 |
|
|
23:0 |
TXDRVTRIM |
Each enabled TX driver segment swing level |
RW |
0x00 0000 |
Address offset |
0x0A0 |
||
Physical address |
0x0108 40A0 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 80A0 |
serdes_2_PMA_LANE3 |
||
0x0108 20A0 |
serdes_1_PMA_LANE1 |
||
0x0120 80A0 |
serdes_3_PMA_LANE3 |
||
0x0104 40A0 |
serdes_0_PMA_LANE2 |
||
0x0120 20A0 |
serdes_3_PMA_LANE1 |
||
0x0108 10A0 |
serdes_1_PMA_LANE0 |
||
0x0104 20A0 |
serdes_0_PMA_LANE1 |
||
0x0110 10A0 |
serdes_2_PMA_LANE0 |
||
0x0110 40A0 |
serdes_2_PMA_LANE2 |
||
0x0104 80A0 |
serdes_0_PMA_LANE3 |
||
0x0110 20A0 |
serdes_2_PMA_LANE1 |
||
0x0108 80A0 |
serdes_1_PMA_LANE3 |
||
0x0120 40A0 |
serdes_3_PMA_LANE2 |
||
0x0104 10A0 |
serdes_0_PMA_LANE0 |
||
0x0120 10A0 |
serdes_3_PMA_LANE0 |
||
Description |
Serializer Driver Control Select |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:9 |
Reserved |
|
RO |
0x00 0000 |
|
8 |
TXDEEMPHASIS_BEACON |
TX De-emphasis for BEACON |
RW |
0 |
|
|
|
0 |
[txbeacon_3p5db_deemphasis_sel] Select -3.5dB for TX
De-emphasis |
|
|
|
|
1 |
[txbeacon_6p0db_deemphasis_sel] Select 6.0dB for TX
De-emphasis |
|
|
7 |
Reserved |
|
RO |
0 |
|
6 |
TXDEEMPHASIS |
TX De-emphasis |
RW |
0 |
|
|
|
0 |
[tx_drive_3p5db_deemphasis_sel] Select -3.5dB for TX
De-emphasis |
|
|
|
|
1 |
[tx_drive_6p0db_deemphasis_sel] Select 6.0dB for TX
De-emphasis |
|
|
5 |
TXSWING |
TX Swing |
RW |
0 |
|
|
|
0 |
[tx_drive_full_swing_sel] Select
full swing for TX drive |
|
|
|
|
1 |
[tx_drive_half_swing_sel] Select
half swing for TX drive |
|
|
4:2 |
TXMARGIN |
TX margin select |
RW |
0x0 |
|
|
|
0x0 |
[tx_drive_margin_fs1v_hs500mv_sel] Select TX margin : 1000 ~ 1200 mV for TX full swing |
|
|
|
|
0x1 |
[tx_drive_margin_fs800mv_hs400mv_sel] Select TX margin : 800 ~ 1000 mV for TX full swing |
|
|
|
|
0x2 |
[tx_drive_margin_fs600mv_hs300mv_sel] Select TX margin : 600 ~ 800 mV for TX full swing |
|
|
|
|
0x3 |
[tx_drive_margin_fs400mv_hs200mv_sel] Select TX margin : 400 ~ 600 mV for TX full swing |
|
|
|
|
0x4 |
[tx_drive_margin_fs200mv_hs100mv_sel] Select TX margin : 200 ~ 400 mV for TX full swing |
|
|
|
|
0x5 |
[tx_drive_margin_fs200mv_hs100mv_sel2] Select TX margin : 200 ~ 400 mV for TX full swing |
|
|
|
|
0x6 |
[tx_drive_margin_fs200mv_hs100mv_sel3] Select TX margin : 200 ~ 400 mV for TX full swing |
|
|
|
|
0x7 |
[tx_drive_margin_fs200mv_hs100mv_sel4] Select TX margin : 200 ~ 400 mV for TX full swing |
|
|
1 |
TXODRV_BOOSTER |
TX Overdrive Control Booster |
RW |
0 |
|
|
|
0 |
[tx_overdrive_booster_disabled]
Disables TX overdrive booster by TXODRV[1] = 0 |
|
|
|
|
1 |
[tx_overdrive_booster_enabled]
Enables TX overdrive booster by TXODRV[1] = 1 |
|
|
0 |
TXDRV_CTRL_SEL |
TX Drive Control signals select between the SER_DRV_CTRL_M*
register inputs (programmed by TXMARGIN, TXSWING and TXDEEMHASIS) and user's
defined SER_DRV_CTRL and SER_DRV_DATA_CTRL registers. |
RW |
0 |
|
|
|
0 |
[tx_drive_ctrl_by_ser_drv_ctrl_sel]
Select SER_DRV_CTRL registers to configure the TXDRVTRIM, TXDRV, TXODRV,
TXDEL and TXDATA_INV control values. |
|
|
|
|
1 |
[tx_drive_ctrl_by_ser_drv_ctrl_m0to4_sel] Select
SER_DRV_CTRL_M0 to SER_DRV_CTRL_M4 registers to configure the TXDRVTRIM,
TXDRV, TXODRV, TXDEL and TXDATA_INV control values. |
|
Address offset |
0x0A4 |
||
Physical address |
0x0108 40A4 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 80A4 |
serdes_2_PMA_LANE3 |
||
0x0108 20A4 |
serdes_1_PMA_LANE1 |
||
0x0120 80A4 |
serdes_3_PMA_LANE3 |
||
0x0104 40A4 |
serdes_0_PMA_LANE2 |
||
0x0120 20A4 |
serdes_3_PMA_LANE1 |
||
0x0108 10A4 |
serdes_1_PMA_LANE0 |
||
0x0104 20A4 |
serdes_0_PMA_LANE1 |
||
0x0110 10A4 |
serdes_2_PMA_LANE0 |
||
0x0110 40A4 |
serdes_2_PMA_LANE2 |
||
0x0104 80A4 |
serdes_0_PMA_LANE3 |
||
0x0110 20A4 |
serdes_2_PMA_LANE1 |
||
0x0108 80A4 |
serdes_1_PMA_LANE3 |
||
0x0120 40A4 |
serdes_3_PMA_LANE2 |
||
0x0104 10A4 |
serdes_0_PMA_LANE0 |
||
0x0120 10A4 |
serdes_3_PMA_LANE0 |
||
Description |
Serializer Driver Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:22 |
Reserved |
|
RO |
0x000 |
21:16 |
TXDRVTRIM_HS_0DB_M0 |
TX Drive Trim for Half Swing and 0dB de-emphasis and TXmargin = 000 |
RW |
0x1B |
15:14 |
Reserved |
|
RO |
0x0 |
13:8 |
TXDRVTRIM_FS_6P0DB_M0 |
TX Drive Trim for Full Swing and -6.0dB de-emphasis and TXmargin = 000 |
RW |
0x34 |
7:6 |
Reserved |
|
RO |
0x0 |
5:0 |
TXDRVTRIM_FS_3P5DB_M0 |
TX Drive Trim for Full Swing and -3.5dB de-emphasis and TXmargin = 000 |
RW |
0x23 |
Address offset |
0x0A8 |
||
Physical address |
0x0108 40A8 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 80A8 |
serdes_2_PMA_LANE3 |
||
0x0108 20A8 |
serdes_1_PMA_LANE1 |
||
0x0120 80A8 |
serdes_3_PMA_LANE3 |
||
0x0104 40A8 |
serdes_0_PMA_LANE2 |
||
0x0120 20A8 |
serdes_3_PMA_LANE1 |
||
0x0108 10A8 |
serdes_1_PMA_LANE0 |
||
0x0104 20A8 |
serdes_0_PMA_LANE1 |
||
0x0110 10A8 |
serdes_2_PMA_LANE0 |
||
0x0110 40A8 |
serdes_2_PMA_LANE2 |
||
0x0104 80A8 |
serdes_0_PMA_LANE3 |
||
0x0110 20A8 |
serdes_2_PMA_LANE1 |
||
0x0108 80A8 |
serdes_1_PMA_LANE3 |
||
0x0120 40A8 |
serdes_3_PMA_LANE2 |
||
0x0104 10A8 |
serdes_0_PMA_LANE0 |
||
0x0120 10A8 |
serdes_3_PMA_LANE0 |
||
Description |
Serializer Driver Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:22 |
Reserved |
|
RO |
0x000 |
21:16 |
TXDRVTRIM_HS_0DB_M1 |
TX Drive Trim for Half Swing and 0dB de-emphasis and TXmargin = 001 |
RW |
0x23 |
15:14 |
Reserved |
|
RO |
0x0 |
13:8 |
TXDRVTRIM_FS_6P0DB_M1 |
TX Drive Trim for Full Swing and -6.0dB de-emphasis and TXmargin = 001 |
RW |
0x2C |
7:6 |
Reserved |
|
RO |
0x0 |
5:0 |
TXDRVTRIM_FS_3P5DB_M1 |
TX Drive Trim for Full Swing and -3.5dB de-emphasis and TXmargin = 001 |
RW |
0x27 |
Address offset |
0x0AC |
||
Physical address |
0x0108 40AC |
Instance |
serdes_1_PMA_LANE2 |
0x0110 80AC |
serdes_2_PMA_LANE3 |
||
0x0108 20AC |
serdes_1_PMA_LANE1 |
||
0x0120 80AC |
serdes_3_PMA_LANE3 |
||
0x0104 40AC |
serdes_0_PMA_LANE2 |
||
0x0120 20AC |
serdes_3_PMA_LANE1 |
||
0x0108 10AC |
serdes_1_PMA_LANE0 |
||
0x0104 20AC |
serdes_0_PMA_LANE1 |
||
0x0110 10AC |
serdes_2_PMA_LANE0 |
||
0x0110 40AC |
serdes_2_PMA_LANE2 |
||
0x0104 80AC |
serdes_0_PMA_LANE3 |
||
0x0110 20AC |
serdes_2_PMA_LANE1 |
||
0x0108 80AC |
serdes_1_PMA_LANE3 |
||
0x0120 40AC |
serdes_3_PMA_LANE2 |
||
0x0104 10AC |
serdes_0_PMA_LANE0 |
||
0x0120 10AC |
serdes_3_PMA_LANE0 |
||
Description |
Serializer Driver Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:22 |
Reserved |
|
RO |
0x000 |
21:16 |
TXDRVTRIM_HS_0DB_M2 |
TX Drive Trim for Half Swing and 0dB de-emphasis and TXmargin = 010 |
RW |
0x1B |
15:14 |
Reserved |
|
RO |
0x0 |
13:8 |
TXDRVTRIM_FS_6P0DB_M2 |
TX Drive Trim for Full Swing and -6.0dB de-emphasis and TXmargin = 010 |
RW |
0x1B |
7:6 |
Reserved |
|
RO |
0x0 |
5:0 |
TXDRVTRIM_FS_3P5DB_M2 |
TX Drive Trim for Full Swing and -3.5dB de-emphasis and TXmargin = 010 |
RW |
0x1B |
Address offset |
0x0B0 |
||
Physical address |
0x0108 40B0 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 80B0 |
serdes_2_PMA_LANE3 |
||
0x0108 20B0 |
serdes_1_PMA_LANE1 |
||
0x0120 80B0 |
serdes_3_PMA_LANE3 |
||
0x0104 40B0 |
serdes_0_PMA_LANE2 |
||
0x0120 20B0 |
serdes_3_PMA_LANE1 |
||
0x0108 10B0 |
serdes_1_PMA_LANE0 |
||
0x0104 20B0 |
serdes_0_PMA_LANE1 |
||
0x0110 10B0 |
serdes_2_PMA_LANE0 |
||
0x0110 40B0 |
serdes_2_PMA_LANE2 |
||
0x0104 80B0 |
serdes_0_PMA_LANE3 |
||
0x0110 20B0 |
serdes_2_PMA_LANE1 |
||
0x0108 80B0 |
serdes_1_PMA_LANE3 |
||
0x0120 40B0 |
serdes_3_PMA_LANE2 |
||
0x0104 10B0 |
serdes_0_PMA_LANE0 |
||
0x0120 10B0 |
serdes_3_PMA_LANE0 |
||
Description |
Serializer Driver Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:22 |
Reserved |
|
RO |
0x000 |
21:16 |
TXDRVTRIM_HS_0DB_M3 |
TX Drive Trim for Half Swing and 0dB de-emphasis and TXmargin = 011 |
RW |
0x1B |
15:14 |
Reserved |
|
RO |
0x0 |
13:8 |
TXDRVTRIM_FS_6P0DB_M3 |
TX Drive Trim for Full Swing and -6.0dB de-emphasis and TXmargin = 011 |
RW |
0x1B |
7:6 |
Reserved |
|
RO |
0x0 |
5:0 |
TXDRVTRIM_FS_3P5DB_M3 |
TX Drive Trim for Full Swing and -3.5dB de-emphasis and TXmargin = 011 |
RW |
0x14 |
Address offset |
0x0B4 |
||
Physical address |
0x0108 40B4 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 80B4 |
serdes_2_PMA_LANE3 |
||
0x0108 20B4 |
serdes_1_PMA_LANE1 |
||
0x0120 80B4 |
serdes_3_PMA_LANE3 |
||
0x0104 40B4 |
serdes_0_PMA_LANE2 |
||
0x0120 20B4 |
serdes_3_PMA_LANE1 |
||
0x0108 10B4 |
serdes_1_PMA_LANE0 |
||
0x0104 20B4 |
serdes_0_PMA_LANE1 |
||
0x0110 10B4 |
serdes_2_PMA_LANE0 |
||
0x0110 40B4 |
serdes_2_PMA_LANE2 |
||
0x0104 80B4 |
serdes_0_PMA_LANE3 |
||
0x0110 20B4 |
serdes_2_PMA_LANE1 |
||
0x0108 80B4 |
serdes_1_PMA_LANE3 |
||
0x0120 40B4 |
serdes_3_PMA_LANE2 |
||
0x0104 10B4 |
serdes_0_PMA_LANE0 |
||
0x0120 10B4 |
serdes_3_PMA_LANE0 |
||
Description |
Serializer Driver Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:22 |
Reserved |
|
RO |
0x000 |
21:16 |
TXDRVTRIM_HS_0DB_M4 |
TX Drive Trim for Half Swing and 0dB de-emphasis and TXmargin = 100 |
RW |
0x24 |
15:14 |
Reserved |
|
RO |
0x0 |
13:8 |
TXDRVTRIM_FS_6P0DB_M4 |
TX Drive Trim for Full Swing and -6.0dB de-emphasis and TXmargin = 100 |
RW |
0x0C |
7:6 |
Reserved |
|
RO |
0x0 |
5:0 |
TXDRVTRIM_FS_3P5DB_M4 |
TX Drive Trim for Full Swing and -3.5dB de-emphasis and TXmargin = 100 |
RW |
0x0A |
Address offset |
0x0B8 |
||
Physical address |
0x0108 40B8 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 80B8 |
serdes_2_PMA_LANE3 |
||
0x0108 20B8 |
serdes_1_PMA_LANE1 |
||
0x0120 80B8 |
serdes_3_PMA_LANE3 |
||
0x0104 40B8 |
serdes_0_PMA_LANE2 |
||
0x0120 20B8 |
serdes_3_PMA_LANE1 |
||
0x0108 10B8 |
serdes_1_PMA_LANE0 |
||
0x0104 20B8 |
serdes_0_PMA_LANE1 |
||
0x0110 10B8 |
serdes_2_PMA_LANE0 |
||
0x0110 40B8 |
serdes_2_PMA_LANE2 |
||
0x0104 80B8 |
serdes_0_PMA_LANE3 |
||
0x0110 20B8 |
serdes_2_PMA_LANE1 |
||
0x0108 80B8 |
serdes_1_PMA_LANE3 |
||
0x0120 40B8 |
serdes_3_PMA_LANE2 |
||
0x0104 10B8 |
serdes_0_PMA_LANE0 |
||
0x0120 10B8 |
serdes_3_PMA_LANE0 |
||
Description |
Serializer Driver Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:30 |
Reserved |
|
RO |
0x0 |
29:24 |
TXDRVTRIM_BEACON_6P0DB_1 |
TX Drive Trim for TX Beacon and -6.0dB de-emphasis |
RW |
0x1B |
23:22 |
Reserved |
|
RO |
0x0 |
21:16 |
TXDRVTRIM_BEACON_6P0DB_0 |
TX Drive Trim for TX Beacon and -6.0dB de-emphasis |
RW |
0x38 |
15:14 |
Reserved |
|
RO |
0x0 |
13:8 |
TXDRVTRIM_BEACON_3P5DB_1 |
TX Drive Trim for TX Beacon and -3.5dB de-emphasis |
RW |
0x3B |
7:6 |
Reserved |
|
RO |
0x0 |
5:0 |
TXDRVTRIM_BEACON_3P5DB_0 |
TX Drive Trim for TX Beacon and -3.5dB de-emphasis |
RW |
0x38 |
Address offset |
0x0C0 |
||
Physical address |
0x0108 40C0 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 80C0 |
serdes_2_PMA_LANE3 |
||
0x0108 20C0 |
serdes_1_PMA_LANE1 |
||
0x0120 80C0 |
serdes_3_PMA_LANE3 |
||
0x0104 40C0 |
serdes_0_PMA_LANE2 |
||
0x0120 20C0 |
serdes_3_PMA_LANE1 |
||
0x0108 10C0 |
serdes_1_PMA_LANE0 |
||
0x0104 20C0 |
serdes_0_PMA_LANE1 |
||
0x0110 10C0 |
serdes_2_PMA_LANE0 |
||
0x0110 40C0 |
serdes_2_PMA_LANE2 |
||
0x0104 80C0 |
serdes_0_PMA_LANE3 |
||
0x0110 20C0 |
serdes_2_PMA_LANE1 |
||
0x0108 80C0 |
serdes_1_PMA_LANE3 |
||
0x0120 40C0 |
serdes_3_PMA_LANE2 |
||
0x0104 10C0 |
serdes_0_PMA_LANE0 |
||
0x0120 10C0 |
serdes_3_PMA_LANE0 |
||
Description |
SERDES RTL Control |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:20 |
Reserved |
|
RO |
0x000 |
|
19 |
RX_EYEMONITOR_COMPARISON_DATA_SEL |
Send 40 bit eye monitor
comparison result to RX_DATA_TO_CORE40 |
RW |
0 |
|
|
|
0 |
[rx_data40_from_org_rx_data40_sel] Select normal RX Data40
for core RX data40 |
|
|
|
|
1 |
[rx_data40_from_em_comp_rx_data40_sel] Select RX Data40
from Eye Monitor Comparison data out for core RX data40 |
|
|
18 |
RX_FIFO_INPUT_SELECT_NEIGHBOR |
select data and clock to RX FIFO from deserializer |
RW |
0 |
|
|
|
0 |
[rx_fifo_from_local_rx_fifo_data_sel]
Select local RX data and RX clock for RX FIFO |
|
|
|
|
1 |
[rx_fifo_from_neighbor_rx_fifo_data_sel]
Select neighbor RX data and RX clock for RX FIFO |
|
|
17:16 |
RX_DATA_SELECT |
select data and clock to core from deserializer
|
RW |
0x0 |
|
|
|
0x0 |
[rxdata_from_cdr_data_sel]
Select CDR/CTLE data and clock to core from de-serializer |
|
|
|
|
0x1 |
[rxdata_from_dfe_data_sel]
Select DFE data and clock to core from de-serializer |
|
|
|
|
0x2 |
[rxdata_from_em_data_sel] Select
Eye Monitor data and clock to core from de-serializer |
|
|
|
|
0x3 |
[rxdata_from_em_data_sel2] Select Eye Monitor data and
clock to core from de-serializer |
|
|
15 |
Reserved |
|
RO |
0 |
|
14:12 |
TX_DATA_SELECT |
Serializer Data Mux Select |
RW |
0x0 |
|
|
|
0x0 |
[txdata_from_core_txdata_sel]
Select TX data from core for serializer data |
|
|
|
|
0x1 |
[txdata_from_rx_fifo_sel] Select
RX FIFO data for serializer data |
|
|
|
|
0x2 |
[txdata_from_prbs_pattern_gen_sel]
Select PRBS pattern generator data for serializer data |
|
|
|
|
0x3 |
[txdata_from_prog_static_pattern_sel]
Select programmable static pattern for serializer data |
|
|
|
|
0x4 |
[txdata_from_txoob_data_sel]
Select TX OOB data for serializer data |
|
|
|
|
0x5 |
[txdata_from_core_txdata_sel2] Select TX data from core
for serializer data |
|
|
|
|
0x6 |
[txdata_from_static_pattern2_sel] Select static pattern 2
for serializer data |
|
|
|
|
0x7 |
[txdata_from_static_pattern50_sel] Select static pattern
50 for serializer data |
|
|
11:9 |
TX_PRBSMODE |
Serializer PRBS Pattern Select |
RW |
0x0 |
|
|
|
0x0 |
[tx_prbs7_mode_sel] Select PRBS7 mode for PRBS
generator/checker ( f(x) = x^7 +x^6 + 1 ) |
|
|
|
|
0x1 |
[tx_prbs9_mode_sel] Select PRBS9 mode for PRBS
generator/checker ( f(x) = x^9 +x^5 + 1 ) |
|
|
|
|
0x2 |
[tx_prbs15_mode_sel] Select PRBS15 mode for PRBS
generator/checker ( f(x) = x^15 +x^14 + 1 ) |
|
|
|
|
0x3 |
[tx_prbs23_mode_sel] Select PRBS23 mode for PRBS
generator/checker ( f(x) = x^23 +x^18 + 1 ) |
|
|
|
|
0x4 |
[tx_prbs31_mode_sel] Select PRBS31 mode for PRBS
generator/checker ( f(x) = x^31 +x^28 + 1 ) |
|
|
|
|
0x5 |
[tx_prbs31_mode_sel2] Select PRBS31 mode for PRBS
generator/checker ( f(x) = x^31 +x^28 + 1 ) |
|
|
|
|
0x6 |
[tx_prbs31_mode_sel3] Select PRBS31 mode for PRBS
generator/checker ( f(x) = x^31 +x^28 + 1 ) |
|
|
|
|
0x7 |
[tx_prbs31_mode_sel4] Select PRBS31 mode for PRBS
generator/checker ( f(x) = x^31 +x^28 + 1 ) |
|
|
8 |
RESET_RTL |
Reset all RTL for the channel. |
RW |
1 |
|
|
|
0 |
[serdes_rtl_reset_deasserted]
SERDES RTL reset is deasserted |
|
|
|
|
1 |
[serdes_rtl_reset_asserted]
SERDES RTL reset is asserted |
|
|
7:2 |
Reserved |
|
RO |
0x00 |
|
1 |
TX_HALF_RATE10BIT |
Passes each bit from TXDATA10[n] to TXDATA20[2*n] and
TXDATA20[(2*n)+1]. |
RW |
0 |
|
|
|
0 |
[tx_half_rate_10bit_disabled] Disables TX half rate 10bit
function |
|
|
|
|
1 |
[tx_half_rate_10bit_enabled] Enables TX half rate 10bit
function: Passes each bit from TXDATA10[n] to TXDATA20[2*n] and TXDATA20[(2*n)+1] |
|
|
0 |
RX_HALF_RATE10BIT |
Passes every other bit (19,17,15...etc)
from RX_DATA_TO_CORE20 to RX_DATA_TO_CORE10 |
RW |
0 |
|
|
|
0 |
[rx_half_rate_10bit_disabled] Disables RX half rate 10bit
function |
|
|
|
|
1 |
[rx_half_rate_10bit_enabled] Enables RX half rate 10bit
function: Passes every other bit (19,17,15...etc)
from RX_DATA_TO_CORE20 to RX_DATA_TO_CORE10 |
|
Address offset |
0x0D0 |
||
Physical address |
0x0108 40D0 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 80D0 |
serdes_2_PMA_LANE3 |
||
0x0108 20D0 |
serdes_1_PMA_LANE1 |
||
0x0120 80D0 |
serdes_3_PMA_LANE3 |
||
0x0104 40D0 |
serdes_0_PMA_LANE2 |
||
0x0120 20D0 |
serdes_3_PMA_LANE1 |
||
0x0108 10D0 |
serdes_1_PMA_LANE0 |
||
0x0104 20D0 |
serdes_0_PMA_LANE1 |
||
0x0110 10D0 |
serdes_2_PMA_LANE0 |
||
0x0110 40D0 |
serdes_2_PMA_LANE2 |
||
0x0104 80D0 |
serdes_0_PMA_LANE3 |
||
0x0110 20D0 |
serdes_2_PMA_LANE1 |
||
0x0108 80D0 |
serdes_1_PMA_LANE3 |
||
0x0120 40D0 |
serdes_3_PMA_LANE2 |
||
0x0104 10D0 |
serdes_0_PMA_LANE0 |
||
0x0120 10D0 |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer DFE
Calibration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:24 |
NUM_SAMPLES_GOOD_LOCK |
Number of clock cycles the RX PLL
lock signal will be observed and is expected to stay high to assume the PLL
is properly locked. |
RW |
0x64 |
|
23:22 |
Reserved |
|
RO |
0x0 |
|
21:16 |
NUM_SAMPLES_CTLE_OFFSET_CAL |
Number of samples to collect from the CTLE outputs to
determine if its output is in average logic high or low. Used during CTLE
DC-offset calibration. |
RW |
0x10 |
|
15:11 |
Reserved |
|
RO |
0x00 |
|
10:8 |
WAIT_PERIOD_GOOD_LOCK |
Number of clock cycles to wait after a change in settings
before starting to monitor the RX PLL lock signal. I.e.
how long it takes to settle to logic high. |
RW |
0x7 |
|
7:5 |
Reserved |
|
RO |
0x0 |
|
4 |
EN_OFFSET_CAL |
Enable CTLE Offset Calibration |
RW |
0 |
|
|
|
0 |
[ctle_offset_cal_disabled]
Disables CTLE Offset Calibration |
|
|
|
|
1 |
[ctle_offset_cal_enabled]
Enables CTLE Offset Calibration |
|
|
3 |
EN_DFE_CAL |
Enable DFE Calibration |
RW |
0 |
|
|
|
0 |
[dfe_cal_disabled] Disables DFE
Calibration |
|
|
|
|
1 |
[dfe_cal_enabled] Enables DFE
Calibration |
|
|
2 |
EN_FE_CAL |
Enable Front-End Calibration |
RW |
0 |
|
|
|
0 |
[fe_cal_disabled] Disables
Front-End Calibration |
|
|
|
|
1 |
[fe_cal_enabled] Enables
Front-End Calibration |
|
|
1 |
DFE_CAL_RESET |
Reset DFE Calibration |
RW |
1 |
|
|
|
0 |
[dfe_cal_reset_deasserted] DFE
Calibration reset is deasserted |
|
|
|
|
1 |
[dfe_cal_reset_asserted] DFE
Calibration reset is asserted |
|
|
0 |
DFE_CAL_CEN |
Enable control for DFE Calibration |
RW |
0 |
|
|
|
0 |
[dfe_cal_ctrl_disabled] Disables
control for DFE Calibration |
|
|
|
|
1 |
[dfe_cal_ctrl_enabled] Enables
control for DFE Calibration |
|
Address offset |
0x0D4 |
||
Physical address |
0x0108 40D4 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 80D4 |
serdes_2_PMA_LANE3 |
||
0x0108 20D4 |
serdes_1_PMA_LANE1 |
||
0x0120 80D4 |
serdes_3_PMA_LANE3 |
||
0x0104 40D4 |
serdes_0_PMA_LANE2 |
||
0x0120 20D4 |
serdes_3_PMA_LANE1 |
||
0x0108 10D4 |
serdes_1_PMA_LANE0 |
||
0x0104 20D4 |
serdes_0_PMA_LANE1 |
||
0x0110 10D4 |
serdes_2_PMA_LANE0 |
||
0x0110 40D4 |
serdes_2_PMA_LANE2 |
||
0x0104 80D4 |
serdes_0_PMA_LANE3 |
||
0x0110 20D4 |
serdes_2_PMA_LANE1 |
||
0x0108 80D4 |
serdes_1_PMA_LANE3 |
||
0x0120 40D4 |
serdes_3_PMA_LANE2 |
||
0x0104 10D4 |
serdes_0_PMA_LANE0 |
||
0x0120 10D4 |
serdes_3_PMA_LANE0 |
||
Description |
Deserializer DFE
Calibration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:26 |
Reserved |
|
RO |
0x00 |
|
25:24 |
MAX_AREA_CYCLES |
Maximum number of iterations used to refine the center of
the eye opening during area computation. |
RW |
0x1 |
|
23:21 |
Reserved |
|
RO |
0x0 |
|
20:16 |
MAX_DFE_CYCLES |
Maximum number of cycles without improvement before the
DFE calibration quits. Do not set to 0x00. |
RW |
0x03 |
|
15 |
Reserved |
|
RO |
0 |
|
14:12 |
DFE_CAL_NUM_COEFFS |
Number of coefficients to use during DFE calibration. For DFE_CAL_NUM_COEFFS
= n, then coefficients H1 to H(n+1) are used. |
RW |
0x4 |
|
11 |
DFE_CAL_FORCE_CDR_COEFFS |
Forces the CTLE coefficients for the CDR to be the same as
the CTLE coefficients for the DFE when calibration is running. |
RW |
0 |
|
|
|
0 |
[dfe_cal_force_cdr_coeffs_disabled]
Disables setting the CTLE coefficients for the CDR to be the same as the CTLE
coefficients for the DFE when calibration is running. |
|
|
|
|
1 |
[dfe_cal_force_cdr_coeffs_enbled]
Enables setting the CTLE coefficients for the CDR to be the same as the CTLE
coefficients for the DFE when calibration is running. |
|
|
10:8 |
DFE_CAL_FREQUENCY |
Frequency of operation. Used to determine RX CTLE
emphasis. |
RW |
0x0 |
|
7:4 |
DFE_CAL_CLKDIV |
DFE Calibration input clock divider |
RW |
0x1 |
|
3 |
PHASE_DIRECTION_USER |
Sets the direction of the phase stepper |
RW |
1 |
|
|
|
0 |
[phase_direction_set_disabled]
Disables setting the direction of the phase stepper |
|
|
|
|
1 |
[phase_direction_set_enabled]
Enables setting the direction of the phase stepper |
|
|
2 |
DFE_CAL_FORCEH |
Forces the alternative DFE coefficients to be the the only option for FE calibration and initial
coefficients for DFE calibration. |
RW |
0 |
|
|
|
0 |
[dfe_cal_force_disabled]
Disables setting the alternative DFE coefficients to be the the only option for FE calibration and initial
coefficients for DFE calibration. |
|
|
|
|
1 |
[dfe_cal_force_enabled] Enables
setting the alternative DFE coefficients to be the the
only option for FE calibration and initial coefficients for DFE calibration. |
|
|
1 |
DFE_CAL_EM_ONLY |
Perform eye area calculation using eye monitor only |
RW |
0 |
|
|
|
0 |
[dfe_cal_em_only_disabled]
Disables performing eye area calculation using eye monitor only function. |
|
|
|
|
1 |
[dfe_cal_em_only_enabled]
Enables performing eye area calculation using eye monitor only function. |
|
|
0 |
BYPASS_DFECAL_USER |
Bypass DFE Coefficients |
RW |
0 |
|
|
|
0 |
[dfe_coeffs_bypass_disabled]
Disables DFE Coefficients bypass |
|
|
|
|
1 |
[dfe_coeffs_bypass_enabled]
Enables DFE Coefficients bypass |
|
Address offset |
0x0D8 |
||
Physical address |
0x0108 40D8 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 80D8 |
serdes_2_PMA_LANE3 |
||
0x0108 20D8 |
serdes_1_PMA_LANE1 |
||
0x0120 80D8 |
serdes_3_PMA_LANE3 |
||
0x0104 40D8 |
serdes_0_PMA_LANE2 |
||
0x0120 20D8 |
serdes_3_PMA_LANE1 |
||
0x0108 10D8 |
serdes_1_PMA_LANE0 |
||
0x0104 20D8 |
serdes_0_PMA_LANE1 |
||
0x0110 10D8 |
serdes_2_PMA_LANE0 |
||
0x0110 40D8 |
serdes_2_PMA_LANE2 |
||
0x0104 80D8 |
serdes_0_PMA_LANE3 |
||
0x0110 20D8 |
serdes_2_PMA_LANE1 |
||
0x0108 80D8 |
serdes_1_PMA_LANE3 |
||
0x0120 40D8 |
serdes_3_PMA_LANE2 |
||
0x0104 10D8 |
serdes_0_PMA_LANE0 |
||
0x0120 10D8 |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer DFE
Calibration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:28 |
Reserved |
|
RO |
0x0 |
27:16 |
ERROR_THR_CHANNEL_ALIGN |
Number of eye-monitor errors (in multiples of 16) above
which the DFE and EM receivers are assumed to be misaligned. |
RW |
0x080 |
15:5 |
Reserved |
|
RO |
0x000 |
4 |
SET_DFE_COEFFS_USER |
Use preset DFE coefficients as a starting point for
calibration |
RW |
0 |
3 |
SETALT_OFFSET_EM1 |
By asserting a low-to-high transition switched the CTLE
DC-offset correction set by calibration to those specified by the user in offset_XXX_alt. |
RW |
0 |
2 |
SETALT_OFFSET_EM0 |
By asserting a low-to-high transition switched the CTLE
DC-offset correction set by calibration to those specified by the user in offset_XXX_alt. |
RW |
0 |
1 |
SETALT_OFFSET_DFE1 |
By asserting a low-to-high transition switched the CTLE
DC-offset correction set by calibration to those specified by the user in offset_XXX_alt. |
RW |
0 |
0 |
SETALT_OFFSET_DFE0 |
By asserting a low-to-high transition switched the CTLE
DC-offset correction set by calibration to those specified by the user in offset_XXX_alt. |
RW |
0 |
Address offset |
0x0DC |
||
Physical address |
0x0108 40DC |
Instance |
serdes_1_PMA_LANE2 |
0x0110 80DC |
serdes_2_PMA_LANE3 |
||
0x0108 20DC |
serdes_1_PMA_LANE1 |
||
0x0120 80DC |
serdes_3_PMA_LANE3 |
||
0x0104 40DC |
serdes_0_PMA_LANE2 |
||
0x0120 20DC |
serdes_3_PMA_LANE1 |
||
0x0108 10DC |
serdes_1_PMA_LANE0 |
||
0x0104 20DC |
serdes_0_PMA_LANE1 |
||
0x0110 10DC |
serdes_2_PMA_LANE0 |
||
0x0110 40DC |
serdes_2_PMA_LANE2 |
||
0x0104 80DC |
serdes_0_PMA_LANE3 |
||
0x0110 20DC |
serdes_2_PMA_LANE1 |
||
0x0108 80DC |
serdes_1_PMA_LANE3 |
||
0x0120 40DC |
serdes_3_PMA_LANE2 |
||
0x0104 10DC |
serdes_0_PMA_LANE0 |
||
0x0120 10DC |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer DFE
Calibration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:22 |
Reserved |
|
RO |
0x000 |
|
21 |
RUN_STEP_PHASE_EM_USER |
Changes the sampling clock phase of the EM receiver on
positive transition. PHASE_DIRECTION_USER controls the step direction. |
RW |
0 |
|
|
|
0 |
[run_step_phase_em_disabled]
Disables changing the sampling clock phase of the EM receiver on positive
transition. |
|
|
|
|
1 |
[run_step_phase_em_enabled]
Enables changing the sampling clock phase of the EM receiver on positive
transition. |
|
|
20 |
RUN_STEP_PHASE_DFE_USER |
Changes the sampling clock phase of the DFE receiver on
positive transition. PHASE_DIRECTION_USER controls the step direction. |
RW |
0 |
|
|
|
0 |
[run_step_phase_dfe_disabled]
Disables changing the sampling clock phase of the DFE receiver on positive
transition. |
|
|
|
|
1 |
[run_step_phase_dfe_enabled]
Enables changing the sampling clock phase of the DFE receiver on positive
transition. |
|
|
19 |
RUN_GOOD_LOCK_USER |
Starts a Good-lock test on positive transition |
RW |
0 |
|
|
|
0 |
[run_good_lock_test_pos_tran_disabled]
Disables starting a Good-lock test on positive transition |
|
|
|
|
1 |
[run_good_lock_test_pos_tran_enabled]
Starts a Good-lock test on positive transition |
|
|
18 |
RUN_FULL_CAL_USER |
Starts a Full Calibration on positive transition. |
RW |
0 |
|
|
|
0 |
[run_full_cal_pos_tran_disabled]
Disables starting a Full Calibration on positive transition. |
|
|
|
|
1 |
[run_full_cal_pos_tran_enabled]
Starts a Full Calibration on positive transition. |
|
|
17 |
RUN_FE_CALIBRATION_USER |
Starts Front-End (FE) Calibration on positive transition. |
RW |
0 |
|
|
|
0 |
[run_fe_cal_pos_tran_disabled]
Disables starting Front-End (FE) Calibration on positive transition. |
|
|
|
|
1 |
[run_fe_cal_pos_tran_enabled]
Starts Front-End (FE) Calibration on positive transition. |
|
|
16 |
RUN_DFECAL_USER |
Starts DFE Calibration on positive transition. |
RW |
0 |
|
|
|
0 |
[run_dfe_cal_pos_tran_disabled] Disables
starting DFE Calibration on positive transition. |
|
|
|
|
1 |
[run_dfe_cal_pos_tran_enabled]
Starts DFE Calibration on positive transition. |
|
|
15 |
RUN_VERTICAL_USER |
Starts a Vertical Scan on positive transition. |
RW |
0 |
|
|
|
0 |
[run_vertical_scan_pos_tran_disabled]
Disables starting a Vertical Scan on positive transition. |
|
|
|
|
1 |
[run_vertical_scan_pos_tran_enabled]
Starts a Vertical Scan on positive transition. |
|
|
14 |
RUN_VERTICAL_EM_USER |
Starts an EM-Only Vertical Scan on positive transition. |
RW |
0 |
|
|
|
0 |
[run_em_vertical_scan_pos_tran_disabled]
Disables starting an EM-Only Vertical Scan on positive transition. |
|
|
|
|
1 |
[run_em_vertical_scan_pos_tran_enabled]
Starts an EM-Only Vertical Scan on positive transition. |
|
|
13 |
RUN_HORIZONTAL_USER |
Starts a Horizontal Scan on positive transition. |
RW |
0 |
|
|
|
0 |
[run_horizontal_scan_pos_tran_disabled]
Disables starting a Horizontal Scan on positive transition. |
|
|
|
|
1 |
[run_horizontal_scan_pos_tran_enabled]
Starts a Horizontal Scan on positive transition. |
|
|
12 |
RUN_HORIZONTAL_EM_USER |
Starts an EM-Only Horizontal Scan on positive transition. |
RW |
0 |
|
|
|
0 |
[run_em_horizontal_scan_pos_tran_disabled]
Disables starting an EM-Only Horizontal Scan on positive transition. |
|
|
|
|
1 |
[run_em_horizontal_scan_pos_tran_enabled]
Starts an EM-Only Horizontal Scan on positive transition. |
|
|
11 |
RUN_CENTER_HORIZONTAL_USER |
Starts Phase Centering on positive transition. |
RW |
0 |
|
|
|
0 |
[run_center_horizontal_pos_tran_disabled]
Disables starting Phase Centering on positive transition. |
|
|
|
|
1 |
[run_center_horizontal_pos_tran_enabled]
Starts Phase Centering on positive transition. |
|
|
10 |
RUN_CENTER_HORIZONTAL_EM_USER |
Starts Phase Centering (EMOnly)
on positive transition. |
RW |
0 |
|
|
|
0 |
[run_em_center_horizontal_pos_tran_disabled]
Disables starting Phase Centering (EMOnly) on
positive transition. |
|
|
|
|
1 |
[run_em_center_horizontal_pos_tran_enabled]
Starts Phase Centering (EMOnly) on positive
transition. |
|
|
9 |
RUN_CHANNEL_ALIGN_USER |
Starts Channel Alignment on positive transition. |
RW |
0 |
|
|
|
0 |
[run_channel_alignment_pos_tran_disabled]
Disables starting Channel Alignment on positive transition. |
|
|
|
|
1 |
[run_channel_alignment_pos_tran_enabled]
Starts Channel Alignment on positive transition. |
|
|
8 |
RUN_AREA_COMPUTE_USER |
Starts Eye-Area Computation on positive transition. |
RW |
0 |
|
|
|
0 |
[run_eye_area_comp_pos_tran_disabled]
Disables starting Eye-Area Computation on positive transition. |
|
|
|
|
1 |
[run_eye_area_comp_pos_tran_enabled]
Starts Eye-Area Computation on positive transition. |
|
|
7 |
RUN_CTLE_OFFSET_CAL7_USER |
Starts CTLE DC-Offset calibration on positive transition. |
RW |
0 |
|
|
|
0 |
[run_ctle_dc_offset_cal7_pos_tran_disabled] Disables
starting CTLE DC-Offset Calibration 7 on positive transition |
|
|
|
|
1 |
[run_ctle_dc_offset_cal7_pos_tran_enabled] Starts CTLE
DC-Offset Calibration 7 on positive transition |
|
|
6 |
RUN_CTLE_OFFSET_CAL6_USER |
Starts CTLE DC-Offset calibration on positive transition. |
RW |
0 |
|
|
|
0 |
[run_ctle_dc_offset_cal6_pos_tran_disabled] Disables
starting CTLE DC-Offset Calibration 6 on positive transition |
|
|
|
|
1 |
[run_ctle_dc_offset_cal6_pos_tran_enabled] Starts CTLE
DC-Offset Calibration 6 on positive transition |
|
|
5 |
RUN_CTLE_OFFSET_CAL5_USER |
Starts CTLE DC-Offset calibration on positive transition. |
RW |
0 |
|
|
|
0 |
[run_ctle_dc_offset_cal5_pos_tran_disabled] Disables
starting CTLE DC-Offset Calibration 5 on positive transition |
|
|
|
|
1 |
[run_ctle_dc_offset_cal5_pos_tran_enabled] Starts CTLE
DC-Offset Calibration 5 on positive transition |
|
|
4 |
RUN_CTLE_OFFSET_CAL4_USER |
Starts CTLE DC-Offset calibration on positive transition. |
RW |
0 |
|
|
|
0 |
[run_ctle_dc_offset_cal4_pos_tran_disabled] Disables starting
CTLE DC-Offset Calibration 4 on positive transition |
|
|
|
|
1 |
[run_ctle_dc_offset_cal4_pos_tran_enabled] Starts CTLE
DC-Offset Calibration 4 on positive transition |
|
|
3 |
RUN_CTLE_OFFSET_CAL3_USER |
Starts CTLE DC-Offset calibration on positive transition. |
RW |
0 |
|
|
|
0 |
[run_ctle_dc_offset_cal3_pos_tran_disabled] Disables
starting CTLE DC-Offset Calibration 3 on positive transition |
|
|
|
|
1 |
[run_ctle_dc_offset_cal3_pos_tran_enabled] Starts CTLE
DC-Offset Calibration 3 on positive transition |
|
|
2 |
RUN_CTLE_OFFSET_CAL2_USER |
Starts CTLE DC-Offset calibration on positive transition. |
RW |
0 |
|
|
|
0 |
[run_ctle_dc_offset_cal2_pos_tran_disabled] Disables
starting CTLE DC-Offset Calibration 2 on positive transition |
|
|
|
|
1 |
[run_ctle_dc_offset_cal2_pos_tran_enabled] Starts CTLE
DC-Offset Calibration 2 on positive transition |
|
|
1 |
RUN_CTLE_OFFSET_CAL1_USER |
Starts CTLE DC-Offset calibration on positive transition. |
RW |
0 |
|
|
|
0 |
[run_ctle_dc_offset_cal1_pos_tran_disabled] Disables
starting CTLE DC-Offset Calibration 1 on positive transition |
|
|
|
|
1 |
[run_ctle_dc_offset_cal1_pos_tran_enabled] Starts CTLE
DC-Offset Calibration 1 on positive transition |
|
|
0 |
RUN_CTLE_OFFSET_CAL0_USER |
Starts CTLE DC-Offset calibration on positive transition. |
RW |
0 |
|
|
|
0 |
[run_ctle_dc_offset_cal0_pos_tran_disabled] Disables starting starting CTLE DC-Offset
Calibration 0 on positive transition |
|
|
|
|
1 |
[run_ctle_dc_offset_cal0_pos_tran_enabled] Starts CTLE
DC-Offset Calibration 0 on positive transition |
|
Address offset |
0x0E0 |
||
Physical address |
0x0108 40E0 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 80E0 |
serdes_2_PMA_LANE3 |
||
0x0108 20E0 |
serdes_1_PMA_LANE1 |
||
0x0120 80E0 |
serdes_3_PMA_LANE3 |
||
0x0104 40E0 |
serdes_0_PMA_LANE2 |
||
0x0120 20E0 |
serdes_3_PMA_LANE1 |
||
0x0108 10E0 |
serdes_1_PMA_LANE0 |
||
0x0104 20E0 |
serdes_0_PMA_LANE1 |
||
0x0110 10E0 |
serdes_2_PMA_LANE0 |
||
0x0110 40E0 |
serdes_2_PMA_LANE2 |
||
0x0104 80E0 |
serdes_0_PMA_LANE3 |
||
0x0110 20E0 |
serdes_2_PMA_LANE1 |
||
0x0108 80E0 |
serdes_1_PMA_LANE3 |
||
0x0120 40E0 |
serdes_3_PMA_LANE2 |
||
0x0104 10E0 |
serdes_0_PMA_LANE0 |
||
0x0120 10E0 |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer DFE
Calibration |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
|
31:22 |
Reserved |
|
RO |
0x000 |
|
21 |
SEL_LOCK_OVERRIDE |
Select LOCK_OVERRIDE register value. |
RW |
0 |
|
|
|
0 |
[lock_override_core_value_sel]
Selects LOCK_OVERRIDE value from core |
|
|
|
|
1 |
[lock_override_register_value_sel]
Selects LOCK_OVERRIDE value from register |
|
|
20 |
SEL_SLIP_DES_EM |
Select SLIP_DES_EM register value. |
RW |
0 |
|
|
|
0 |
[slip_des_em_core_value_sel]
Selects SLIP_DES_EM value from core |
|
|
|
|
1 |
[slip_des_em_register_value_sel]
Selects SLIP_DES_EM value from register |
|
|
19 |
SEL_RUN_EYEMONITOR_COMPARISON |
Select RUN_EYEMONITOR_COMPARISON reigster
value. |
RW |
0 |
|
|
|
0 |
[run_em_comparison_core_value_sel]
Selects RUN_EYEMONITOR_COMPARISON value from core |
|
|
|
|
1 |
[run_em_comparison_register_value_sel]
Selects RUN_EYEMONITOR_COMPARISON value from register |
|
|
18 |
SEL_RST2_DFEEM |
Select RST2_DFEEM register value. |
RW |
0 |
|
|
|
0 |
[rst2_dfeem_core_value_sel] Selects RST2_DFEEM value from
core |
|
|
|
|
1 |
[rst2_dfeem_register_value_sel] Selects RST2_DFEEM value
from register |
|
|
17 |
SEL_RST1_DFEEM |
Select RST1_DFEEM register value. |
RW |
0 |
|
|
|
0 |
[rst1_dfeem_core_value_sel] Selects RST1_DFEEM value from
core |
|
|
|
|
1 |
[rst1_dfeem_register_value_sel] Selects RST1_DFEEM value
from register |
|
|
16 |
SEL_RCVEN |
Select RCVEN register value. |
RW |
0 |
|
|
|
0 |
[rcven_core_value_sel] Selects
RCVEN value from core |
|
|
|
|
1 |
[rcven_register_value_sel]
Selects RCVEN value from register |
|
|
15 |
SEL_PHICTRL_EM |
Select register values of PHICTRL_GRAY_EM and
PHICTRL_TH_EM. |
RW |
0 |
|
|
|
0 |
[phictrl_em_core_value_sel]
Selects PHICTRL_GRAY_EM and PHICTRL_EM_EM values from core |
|
|
|
|
1 |
[phictrl_em_register_value_sel]
Selects PHICTRL_GRAY_EM and PHICTRL_EM_EM values from register |
|
|
14 |
SEL_PHICTRL_DFE |
Select register values of PHICTRL_GRAY_DFE and
PHICTRL_EM_DFE. |
RW |
0 |
|
|
|
0 |
[phictrl_dfe_core_value_sel] Selects
PHICTRL_GRAY_DFE and PHICTRL_EM_DFE values from core |
|
|
|
|
1 |
[phictrl_dfe_register_value_sel]
Selects PHICTRL_GRAY_DFE and PHICTRL_EM_DFE values from register |
|
|
13 |
SEL_CTLEEN_EM |
Select CTLEEN_EM register value. |
RW |
0 |
|
|
|
0 |
[ctleen_em_core_value_sel]
Selects CTLEEN_EM value from core |
|
|
|
|
1 |
[ctleen_em_register_value_sel]
Selects CTLEEN_EM value from register |
|
|
12 |
SEL_CTLEEN_DFE |
Select CTLEEN_DFE register value. |
RW |
0 |
|
|
|
0 |
[ctleen_dfe_core_value_sel]
Selects CTLEEN_DFE value from core |
|
|
|
|
1 |
[ctleen_dfe_register_value_sel]
Selects CTLEEN_DFE value from register |
|
|
11 |
SEL_CST2_DFEEM |
Select CST2_DFEEM register value. |
RW |
0 |
|
|
|
0 |
[cst2_dfeem_core_value_sel] Selects CST2_DFEEM value from
core |
|
|
|
|
1 |
[cst2_dfeem_register_value_sel] Selects CST2_DFEEM value
from register |
|
|
10 |
SEL_CST1_DFEEM |
Select CST1_DFEEM register value. |
RW |
0 |
|
|
|
0 |
[cst1_dfeem_core_value_sel] Selects CST1_DFEEM value from
core |
|
|
|
|
1 |
[cst1_dfeem_register_value_sel] Selects CST1_DFEEM value
from register |
|
|
9 |
SEL_CDRCTLE |
Select register values of CST1_CDR, CST2_CDR, RST1_CDR and
RST2_CDR. |
RW |
0 |
|
|
|
0 |
[cdrctle_core_value_sel] Selects
CST1_CDR, CST2_CDR, RST1_CDR and RST2_CDR values from core |
|
|
|
|
1 |
[cdrctle_register_value_sel]
Selects CST1_CDR, CST2_CDR, RST1_CDR and RST2_CDR values from register |
|
|
8 |
SEL_CALIBRATION_CLK_EN |
Select CALIBRATION_CLK_EN register value. |
RW |
0 |
|
|
|
0 |
[cal_clk_en_core_value_sel]
Selects CALIBRATION_CLK_EN value from core |
|
|
|
|
1 |
[cal_clk_en_register_value_sel] Selects
CALIBRATION_CLK_EN value from register |
|
|
7 |
SEL_H5 |
Select H5 register value. |
RW |
0 |
|
|
|
0 |
[h5_core_value_sel] Selects H5 value from core |
|
|
|
|
1 |
[h5_register_value_sel] Selects H5 value from register |
|
|
6 |
SEL_H4 |
Select H4 register value. |
RW |
0 |
|
|
|
0 |
[h4_core_value_sel] Selects H4 value from core |
|
|
|
|
1 |
[h4_register_value_sel] Selects H4 value from register |
|
|
5 |
SEL_H3 |
Select H3 register value. |
RW |
0 |
|
|
|
0 |
[h3_core_value_sel] Selects H3 value from core |
|
|
|
|
1 |
[h3_register_value_sel] Selects H3 value from register |
|
|
4 |
SEL_H2 |
Select H2 register value. |
RW |
0 |
|
|
|
0 |
[h2_core_value_sel] Selects H2 value from core |
|
|
|
|
1 |
[h2_register_value_sel] Selects H2 value from register |
|
|
3 |
SEL_H1 |
Select H1 register value. |
RW |
0 |
|
|
|
0 |
[h1_core_value_sel] Selects H1 value from core |
|
|
|
|
1 |
[h1_register_value_sel] Selects H1 value from register |
|
|
2 |
SEL_H0EM |
Select H0EM register value. |
RW |
0 |
|
|
|
0 |
[h0em_core_value_sel] Selects H0EM value from core |
|
|
|
|
1 |
[h0em_register_value_sel] Selects H0EM value from register
|
|
|
1 |
SEL_H0DFE |
Select H0DFE register value. |
RW |
0 |
|
|
|
0 |
[h0dfe_core_value_sel] Selects H0DFE value from core |
|
|
|
|
1 |
[h0dfe_register_value_sel] Selects H0DFE value from
register |
|
|
0 |
SEL_H0CDR |
Select H0CDR register value. |
RW |
0 |
|
|
|
0 |
[h0cdr_core_value_sel] Selects H0CDR value from core |
|
|
|
|
1 |
[h0cdr_register_value_sel] Selects H0CDR value from
register |
|
Address offset |
0x0E4 |
||
Physical address |
0x0108 40E4 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 80E4 |
serdes_2_PMA_LANE3 |
||
0x0108 20E4 |
serdes_1_PMA_LANE1 |
||
0x0120 80E4 |
serdes_3_PMA_LANE3 |
||
0x0104 40E4 |
serdes_0_PMA_LANE2 |
||
0x0120 20E4 |
serdes_3_PMA_LANE1 |
||
0x0108 10E4 |
serdes_1_PMA_LANE0 |
||
0x0104 20E4 |
serdes_0_PMA_LANE1 |
||
0x0110 10E4 |
serdes_2_PMA_LANE0 |
||
0x0110 40E4 |
serdes_2_PMA_LANE2 |
||
0x0104 80E4 |
serdes_0_PMA_LANE3 |
||
0x0110 20E4 |
serdes_2_PMA_LANE1 |
||
0x0108 80E4 |
serdes_1_PMA_LANE3 |
||
0x0120 40E4 |
serdes_3_PMA_LANE2 |
||
0x0104 10E4 |
serdes_0_PMA_LANE0 |
||
0x0120 10E4 |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer DFE
Calibration |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:29 |
Reserved |
|
RO |
0x0 |
28:24 |
EYE_HEIGHT |
Height of Eye openning. |
RO |
0x00 |
23:22 |
Reserved |
|
RO |
0x0 |
21:16 |
EYE_WIDTH |
Width of Eye openning. |
RO |
0x00 |
15:13 |
Reserved |
|
RO |
0x0 |
12:8 |
EYE_CENTER_VERTICAL |
Vertical (DC-offset) center of the Eye openning.
|
RO |
0x00 |
7:6 |
Reserved |
|
RO |
0x0 |
5:0 |
EYE_CENTER_HORIZONTAL |
Horizontal (Phase) center of the Eye openning.
|
RO |
0x00 |
Address offset |
0x0E8 |
||
Physical address |
0x0108 40E8 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 80E8 |
serdes_2_PMA_LANE3 |
||
0x0108 20E8 |
serdes_1_PMA_LANE1 |
||
0x0120 80E8 |
serdes_3_PMA_LANE3 |
||
0x0104 40E8 |
serdes_0_PMA_LANE2 |
||
0x0120 20E8 |
serdes_3_PMA_LANE1 |
||
0x0108 10E8 |
serdes_1_PMA_LANE0 |
||
0x0104 20E8 |
serdes_0_PMA_LANE1 |
||
0x0110 10E8 |
serdes_2_PMA_LANE0 |
||
0x0110 40E8 |
serdes_2_PMA_LANE2 |
||
0x0104 80E8 |
serdes_0_PMA_LANE3 |
||
0x0110 20E8 |
serdes_2_PMA_LANE1 |
||
0x0108 80E8 |
serdes_1_PMA_LANE3 |
||
0x0120 40E8 |
serdes_3_PMA_LANE2 |
||
0x0104 10E8 |
serdes_0_PMA_LANE0 |
||
0x0120 10E8 |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer DFE
Calibration |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:29 |
Reserved |
|
RO |
0x0 |
28:24 |
H0CDR3_MON |
Monitor output of H0CDR3 |
RO |
0x00 |
23:21 |
Reserved |
|
RO |
0x0 |
20:16 |
H0CDR2_MON |
Monitor output of H0CDR2 |
RO |
0x00 |
15:13 |
Reserved |
|
RO |
0x0 |
12:8 |
H0CDR1_MON |
Monitor output of H0CDR1 |
RO |
0x00 |
7:5 |
Reserved |
|
RO |
0x0 |
4:0 |
H0CDR0_MON |
Monitor output of H0CDR0 |
RO |
0x00 |
Address offset |
0x0EC |
||
Physical address |
0x0108 40EC |
Instance |
serdes_1_PMA_LANE2 |
0x0110 80EC |
serdes_2_PMA_LANE3 |
||
0x0108 20EC |
serdes_1_PMA_LANE1 |
||
0x0120 80EC |
serdes_3_PMA_LANE3 |
||
0x0104 40EC |
serdes_0_PMA_LANE2 |
||
0x0120 20EC |
serdes_3_PMA_LANE1 |
||
0x0108 10EC |
serdes_1_PMA_LANE0 |
||
0x0104 20EC |
serdes_0_PMA_LANE1 |
||
0x0110 10EC |
serdes_2_PMA_LANE0 |
||
0x0110 40EC |
serdes_2_PMA_LANE2 |
||
0x0104 80EC |
serdes_0_PMA_LANE3 |
||
0x0110 20EC |
serdes_2_PMA_LANE1 |
||
0x0108 80EC |
serdes_1_PMA_LANE3 |
||
0x0120 40EC |
serdes_3_PMA_LANE2 |
||
0x0104 10EC |
serdes_0_PMA_LANE0 |
||
0x0120 10EC |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer DFE
Calibration |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:29 |
Reserved |
|
RO |
0x0 |
28:24 |
H4_MON |
Monitor output of H4 |
RO |
0x00 |
23:21 |
Reserved |
|
RO |
0x0 |
20:16 |
H3_MON |
Monitor output of H3 |
RO |
0x00 |
15:13 |
Reserved |
|
RO |
0x0 |
12:8 |
H2_MON |
Monitor output of H2 |
RO |
0x00 |
7:5 |
Reserved |
|
RO |
0x0 |
4:0 |
H1_MON |
Monitor output of H1 |
RO |
0x00 |
Address offset |
0x0F0 |
||
Physical address |
0x0108 40F0 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 80F0 |
serdes_2_PMA_LANE3 |
||
0x0108 20F0 |
serdes_1_PMA_LANE1 |
||
0x0120 80F0 |
serdes_3_PMA_LANE3 |
||
0x0104 40F0 |
serdes_0_PMA_LANE2 |
||
0x0120 20F0 |
serdes_3_PMA_LANE1 |
||
0x0108 10F0 |
serdes_1_PMA_LANE0 |
||
0x0104 20F0 |
serdes_0_PMA_LANE1 |
||
0x0110 10F0 |
serdes_2_PMA_LANE0 |
||
0x0110 40F0 |
serdes_2_PMA_LANE2 |
||
0x0104 80F0 |
serdes_0_PMA_LANE3 |
||
0x0110 20F0 |
serdes_2_PMA_LANE1 |
||
0x0108 80F0 |
serdes_1_PMA_LANE3 |
||
0x0120 40F0 |
serdes_3_PMA_LANE2 |
||
0x0104 10F0 |
serdes_0_PMA_LANE0 |
||
0x0120 10F0 |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer DFE
Calibration |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:5 |
Reserved |
|
RO |
0x000 0000 |
4:0 |
H5_MON |
Monitor output of H5 |
RO |
0x00 |
Address offset |
0x0F4 |
||
Physical address |
0x0108 40F4 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 80F4 |
serdes_2_PMA_LANE3 |
||
0x0108 20F4 |
serdes_1_PMA_LANE1 |
||
0x0120 80F4 |
serdes_3_PMA_LANE3 |
||
0x0104 40F4 |
serdes_0_PMA_LANE2 |
||
0x0120 20F4 |
serdes_3_PMA_LANE1 |
||
0x0108 10F4 |
serdes_1_PMA_LANE0 |
||
0x0104 20F4 |
serdes_0_PMA_LANE1 |
||
0x0110 10F4 |
serdes_2_PMA_LANE0 |
||
0x0110 40F4 |
serdes_2_PMA_LANE2 |
||
0x0104 80F4 |
serdes_0_PMA_LANE3 |
||
0x0110 20F4 |
serdes_2_PMA_LANE1 |
||
0x0108 80F4 |
serdes_1_PMA_LANE3 |
||
0x0120 40F4 |
serdes_3_PMA_LANE2 |
||
0x0104 10F4 |
serdes_0_PMA_LANE0 |
||
0x0120 10F4 |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer DFE
Calibration |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:29 |
Reserved |
|
RO |
0x0 |
28:24 |
OFFSET_EM1 |
DC Calibration offset for the EM CTLE. |
RO |
0x00 |
23:21 |
Reserved |
|
RO |
0x0 |
20:16 |
OFFSET_EM0 |
DC Calibration offset for the EM CTLE. |
RO |
0x00 |
15:13 |
Reserved |
|
RO |
0x0 |
12:8 |
OFFSET_DFE1 |
DC Calibration offset for the DFE CTLE. |
RO |
0x00 |
7:5 |
Reserved |
|
RO |
0x0 |
4:0 |
OFFSET_DFE0 |
DC Calibration offset for the DFE CTLE. |
RO |
0x00 |
Address offset |
0x0F8 |
||
Physical address |
0x0108 40F8 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 80F8 |
serdes_2_PMA_LANE3 |
||
0x0108 20F8 |
serdes_1_PMA_LANE1 |
||
0x0120 80F8 |
serdes_3_PMA_LANE3 |
||
0x0104 40F8 |
serdes_0_PMA_LANE2 |
||
0x0120 20F8 |
serdes_3_PMA_LANE1 |
||
0x0108 10F8 |
serdes_1_PMA_LANE0 |
||
0x0104 20F8 |
serdes_0_PMA_LANE1 |
||
0x0110 10F8 |
serdes_2_PMA_LANE0 |
||
0x0110 40F8 |
serdes_2_PMA_LANE2 |
||
0x0104 80F8 |
serdes_0_PMA_LANE3 |
||
0x0110 20F8 |
serdes_2_PMA_LANE1 |
||
0x0108 80F8 |
serdes_1_PMA_LANE3 |
||
0x0120 40F8 |
serdes_3_PMA_LANE2 |
||
0x0104 10F8 |
serdes_0_PMA_LANE0 |
||
0x0120 10F8 |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer DFE
Calibration |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:9 |
Reserved |
|
RO |
0x00 0000 |
8 |
CHOICE_DFECOEFF |
Look-up table index for the DFE Coefficients chosen by FE
Calibration. |
RO |
0 |
7 |
Reserved |
|
RO |
0 |
6:4 |
CHOICE_DFEEM |
Look-up table index for the CDR CTLE setting chosen by FE
Calibration. |
RO |
0x0 |
3 |
Reserved |
|
RO |
0 |
2:0 |
CHOICE_CDR |
Look-up table index for the CDR CTLE setting chosen by FE
Calibration. |
RO |
0x0 |
Address offset |
0x0FC |
||
Physical address |
0x0108 40FC |
Instance |
serdes_1_PMA_LANE2 |
0x0110 80FC |
serdes_2_PMA_LANE3 |
||
0x0108 20FC |
serdes_1_PMA_LANE1 |
||
0x0120 80FC |
serdes_3_PMA_LANE3 |
||
0x0104 40FC |
serdes_0_PMA_LANE2 |
||
0x0120 20FC |
serdes_3_PMA_LANE1 |
||
0x0108 10FC |
serdes_1_PMA_LANE0 |
||
0x0104 20FC |
serdes_0_PMA_LANE1 |
||
0x0110 10FC |
serdes_2_PMA_LANE0 |
||
0x0110 40FC |
serdes_2_PMA_LANE2 |
||
0x0104 80FC |
serdes_0_PMA_LANE3 |
||
0x0110 20FC |
serdes_2_PMA_LANE1 |
||
0x0108 80FC |
serdes_1_PMA_LANE3 |
||
0x0120 40FC |
serdes_3_PMA_LANE2 |
||
0x0104 10FC |
serdes_0_PMA_LANE0 |
||
0x0120 10FC |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer DFE
Calibration |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:26 |
Reserved |
|
RO |
0x00 |
25:16 |
EYE_AREA |
Area of the Eye openning. |
RO |
0x000 |
15:14 |
Reserved |
|
RO |
0x0 |
13:8 |
PHASE_EM |
Phase of the sampling clock in the EM receiver. |
RO |
0x00 |
7:6 |
Reserved |
|
RO |
0x0 |
5:0 |
PHASE_DFE |
Phase of the sampling clock in the DFE receiver. |
RO |
0x00 |
Address offset |
0x100 |
||
Physical address |
0x0108 4100 |
Instance |
serdes_1_PMA_LANE2 |
0x0110 8100 |
serdes_2_PMA_LANE3 |
||
0x0108 2100 |
serdes_1_PMA_LANE1 |
||
0x0120 8100 |
serdes_3_PMA_LANE3 |
||
0x0104 4100 |
serdes_0_PMA_LANE2 |
||
0x0120 2100 |
serdes_3_PMA_LANE1 |
||
0x0108 1100 |
serdes_1_PMA_LANE0 |
||
0x0104 2100 |
serdes_0_PMA_LANE1 |
||
0x0110 1100 |
serdes_2_PMA_LANE0 |
||
0x0110 4100 |
serdes_2_PMA_LANE2 |
||
0x0104 8100 |
serdes_0_PMA_LANE3 |
||
0x0110 2100 |
serdes_2_PMA_LANE1 |
||
0x0108 8100 |
serdes_1_PMA_LANE3 |
||
0x0120 4100 |
serdes_3_PMA_LANE2 |
||
0x0104 1100 |
serdes_0_PMA_LANE0 |
||
0x0120 1100 |
serdes_3_PMA_LANE0 |
||
Description |
Desirializer DFE
Calibration |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:26 |
Reserved |
|
RO |
0x00 |
25 |
LOCK_IS_GOOD |
Flag set by the Good-lock test after completion. |
RO |
0 |
24 |
DFE_CAL_SUCCESS_ALIGN |
Flag set by the Channel Alignment process after
completion. |
RO |
0 |
23 |
DONE_PHASE_EM |
Done flag indicating that a process is inactive or has
completed its task. |
RO |
0 |
22 |
DONE_PHASE_DFE |
Done flag indicating that a process is inactive or has
completed its task. |
RO |
0 |
21 |
DONE_GOOD_LOCK |
Done flag indicating that a process is inactive or has
completed its task. |
RO |
0 |
20 |
DONE_FULL_CAL |
Done flag indicating that a process is inactive or has
completed its task. |
RO |
0 |
19 |
DONE_FE_CALIBRATION |
Done flag indicating that a process is inactive or has
completed its task. |
RO |
0 |
18 |
DONE_DFECAL |
Done flag indicating that a process is inactive or has
completed its task. |
RO |
0 |
17 |
DONE_ROTATE_EM_EM |
Done flag indicating that a process is inactive or has
completed its task. |
RO |
0 |
16 |
DONE_ROTATE_EM_DFE |
Done flag indicating that a process is inactive or has
completed its task. |
RO |
0 |
15 |
DONE_ROTATE_EM_AREA_COMPUTE |
Done flag indicating that a process is inactive or has
completed its task. |
RO |
0 |
14 |
DONE_ROTATE_DFE_AREA_COMPUTE |
Done flag indicating that a process is inactive or has
completed its task. |
RO |
0 |
13 |
DONE_VERTICAL_COMB |
Done flag indicating that a process is inactive or has
completed its task. |
RO |
0 |
12 |
DONE_VERTICAL_EM |
Done flag indicating that a process is inactive or has
completed its task. |
RO |
0 |
11 |
DONE_HORIZONTAL_COMB |
Done flag indicating that a process is inactive or has
completed its task. |
RO |
0 |
10 |
DONE_HORIZONTAL_EM |
Done flag indicating that a process is inactive or has
completed its task. |
RO |
0 |
9 |
DONE_CHANNEL_ALIGN |
Done flag indicating that a process is inactive or has
completed its task. |
RO |
0 |
8 |
DONE_AREA_COMPUTE |
Done flag indicating that a process is inactive or has
completed its task. |
RO |
0 |
7 |
DONE_CTLE_OFFSET_CAL7 |
Done flag indicating that a process is inactive or has
completed its task. |
RO |
0 |
6 |
DONE_CTLE_OFFSET_CAL6 |
Done flag indicating that a process is inactive or has
completed its task. |
RO |
0 |
5 |
DONE_CTLE_OFFSET_CAL5 |
Done flag indicating that a process is inactive or has
completed its task. |
RO |
0 |
4 |
DONE_CTLE_OFFSET_CAL4 |
Done flag indicating that a process is inactive or has
completed its task. |
RO |
0 |
3 |
DONE_CTLE_OFFSET_CAL3 |
Done flag indicating that a process is inactive or has
completed its task. |
RO |
0 |
2 |
DONE_CTLE_OFFSET_CAL2 |
Done flag indicating that a process is inactive or has
completed its task. |
RO |
0 |
1 |
DONE_CTLE_OFFSET_CAL1 |
Done flag indicating that a process is inactive or has
completed its task. |
RO |
0 |
0 |
DONE_CTLE_OFFSET_CAL0 |
Done flag indicating that a process is inactive or has
completed its task. |
RO |
0 |
PMA_LANE has no common memories.