This section
provides information on the ATHENA Module Instance. Each of the module
registers is described below.
|
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
|
RW |
32 |
0x0000 0000 |
0x6000 |
0x2200 6000 |
|
|
RW |
32 |
0x0000 0000 |
0x6004 |
0x2200 6004 |
|
|
RW |
32 |
0x0000 0000 |
0x6008 |
0x2200 6008 |
|
|
RW |
32 |
0x0000 0000 |
0x600C |
0x2200 600C |
|
|
RO |
32 |
0x0000 0000 |
0x6010 |
0x2200 6010 |
|
|
RW |
32 |
0x0000 0000 |
0x6014 |
0x2200 6014 |
|
|
RW |
32 |
0x0000 0000 |
0x6018 |
0x2200 6018 |
|
Address offset |
0x6000 |
||
|
Physical address |
0x2200 6000 |
Instance |
ATHENA |
|
Description |
Main CSR |
||
|
Type |
RW |
||
|
Bits |
Field Name |
Description |
Type |
Reset |
|
31:19 |
Reserved |
Reserved. When
writing the CSR, write 0 for future compatibility |
RO |
0x0000 |
|
18:8 |
LIRA |
LIR start address |
RW |
0x000 |
|
7 |
PARITYE |
Parity error |
RO |
0 |
|
6 |
ECDIS |
Elliptic curve instruction disable bit (E5200/6400 only) |
RO |
0 |
|
5 |
PURGE |
Soft purge command bit |
RW |
0 |
|
4 |
GO |
Start computation command bit |
WO |
0 |
|
3 |
BUSY |
Busy status bit |
RO |
0 |
|
2 |
CMPLT |
Computation complete status bit |
RO |
0 |
|
1 |
CCMPLT |
Write-only clear CMPLT flag bit |
WO |
0 |
|
0 |
RESET |
Soft reset command bit |
RW |
0 |
|
Address offset |
0x6004 |
||
|
Physical address |
0x2200 6004 |
Instance |
ATHENA |
|
Description |
|||
|
Type |
RW |
||
|
Bits |
Field Name |
Description |
Type |
Reset |
|
31:0 |
Reserved |
|
RW |
0x0000 0000 |
|
Address offset |
0x6008 |
||
|
Physical address |
0x2200 6008 |
Instance |
ATHENA |
|
Description |
|||
|
Type |
RW |
||
|
Bits |
Field Name |
Description |
Type |
Reset |
|
31:0 |
Reserved |
|
RW |
0x0000 0000 |
|
Address offset |
0x600C |
||
|
Physical address |
0x2200 600C |
Instance |
ATHENA |
|
Description |
Memory error status register |
||
|
Type |
RW |
||
|
Bits |
Field Name |
Description |
Type |
Reset |
|
31:30 |
PARITY |
Parity capability field |
RO |
0x0 |
|
29:26 |
Reserved |
|
RO |
0x0 |
|
25 |
SEC |
LIR/FPR/TSR/MMR/BER single error correct status flag |
RW |
0 |
|
24 |
DED |
LIR/FPR/TSR/MMR/BER double error detect status flag |
RO |
0 |
|
23:14 |
Reserved |
|
RO |
0x000 |
|
13:0 |
MERRA |
Memory error word address |
RO |
0x0000 |
|
Address offset |
0x6010 |
||
|
Physical address |
0x2200 6010 |
Instance |
ATHENA |
|
Description |
Memory error value register |
||
|
Type |
RO |
||
|
Bits |
Field Name |
Description |
Type |
Reset |
|
31:0 |
CSRMERRV |
The CSRMERRV is a single 32-bit read-only register that
provides the error correction mask output of the ECC logic when either SEC or
DED is asserted by the ECC logic if present (PARITYC equal to 102 or 112). If
ECC logic is not present (PARITYC equal to 012 or 002), then this field will
always be zero. |
RO |
0x0000 0000 |
|
Address offset |
0x6014 |
||
|
Physical address |
0x2200 6014 |
Instance |
ATHENA |
|
Description |
Memory Error Handling Test Register |
||
|
Type |
RW |
||
|
Bits |
Field Name |
Description |
Type |
Reset |
|
31:0 |
CSRMERRT0 |
The CSRMERRT0-1 memory error handling test register is a
read-write register that is used to inject errors into memory writes in order
to enable testing of error detection and/or correction logic |
RW |
0x0000 0000 |
|
Address offset |
0x6018 |
||
|
Physical address |
0x2200 6018 |
Instance |
ATHENA |
|
Description |
Memory Error Handling Test Register |
||
|
Type |
RW |
||
|
Bits |
Field Name |
Description |
Type |
Reset |
|
31:0 |
CSRMERRT1 |
The CSRMERRT0-1 memory error handling test register is a
read-write register that is used to inject errors into memory writes in order
to enable testing of error detection and/or correction logic |
RW |
0x0000 0000 |
ATHENA has no
common memories.