This section
provides information on the CAN Module Instance. Each of the module registers
is described below.
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
RW |
32 |
0x0000 0000 |
0x000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
|
RO |
32 |
0x0000 0000 |
0x008 |
|
RO |
32 |
0x0000 0000 |
0x00C |
|
RO |
32 |
0x0000 0000 |
0x010 |
|
RW |
32 |
0x3000 0000 |
0x014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
|
RW |
32 |
0b0000
0000 0000 000x xxxx xxxx xx00 0000 |
0x01C |
|
RW |
32 |
0x0080 0000 |
0x020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
|
RW |
32 |
0x0080 0000 |
0x030 |
|
RW |
32 |
0x0000 0000 |
0x034 |
|
RW |
32 |
0x0000 0000 |
0x038 |
|
RW |
32 |
0x0000 0000 |
0x03C |
|
RW |
32 |
0x0080 0000 |
0x040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
|
RW |
32 |
0x0000 0000 |
0x048 |
|
RW |
32 |
0x0000 0000 |
0x04C |
|
RW |
32 |
0x0080 0000 |
0x050 |
|
RW |
32 |
0x0000 0000 |
0x054 |
|
RW |
32 |
0x0000 0000 |
0x058 |
|
RW |
32 |
0x0000 0000 |
0x05C |
|
RW |
32 |
0x0080 0000 |
0x060 |
|
RW |
32 |
0x0000 0000 |
0x064 |
|
RW |
32 |
0x0000 0000 |
0x068 |
|
RW |
32 |
0x0000 0000 |
0x06C |
|
RW |
32 |
0x0080 0000 |
0x070 |
|
RW |
32 |
0x0000 0000 |
0x074 |
|
RW |
32 |
0x0000 0000 |
0x078 |
|
RW |
32 |
0x0000 0000 |
0x07C |
|
RW |
32 |
0x0080 0000 |
0x080 |
|
RW |
32 |
0x0000 0000 |
0x084 |
|
RW |
32 |
0x0000 0000 |
0x088 |
|
RW |
32 |
0x0000 0000 |
0x08C |
|
RW |
32 |
0x0080 0000 |
0x090 |
|
RW |
32 |
0x0000 0000 |
0x094 |
|
RW |
32 |
0x0000 0000 |
0x098 |
|
RW |
32 |
0x0000 0000 |
0x09C |
|
RW |
32 |
0x0080 0000 |
0x0A0 |
|
RW |
32 |
0x0000 0000 |
0x0A4 |
|
RW |
32 |
0x0000 0000 |
0x0A8 |
|
RW |
32 |
0x0000 0000 |
0x0AC |
|
RW |
32 |
0x0080 0000 |
0x0B0 |
|
RW |
32 |
0x0000 0000 |
0x0B4 |
|
RW |
32 |
0x0000 0000 |
0x0B8 |
|
RW |
32 |
0x0000 0000 |
0x0BC |
|
RW |
32 |
0x0080 0000 |
0x0C0 |
|
RW |
32 |
0x0000 0000 |
0x0C4 |
|
RW |
32 |
0x0000 0000 |
0x0C8 |
|
RW |
32 |
0x0000 0000 |
0x0CC |
|
RW |
32 |
0x0080 0000 |
0x0D0 |
|
RW |
32 |
0x0000 0000 |
0x0D4 |
|
RW |
32 |
0x0000 0000 |
0x0D8 |
|
RW |
32 |
0x0000 0000 |
0x0DC |
|
RW |
32 |
0x0080 0000 |
0x0E0 |
|
RW |
32 |
0x0000 0000 |
0x0E4 |
|
RW |
32 |
0x0000 0000 |
0x0E8 |
|
RW |
32 |
0x0000 0000 |
0x0EC |
|
RW |
32 |
0x0080 0000 |
0x0F0 |
|
RW |
32 |
0x0000 0000 |
0x0F4 |
|
RW |
32 |
0x0000 0000 |
0x0F8 |
|
RW |
32 |
0x0000 0000 |
0x0FC |
|
RW |
32 |
0x0080 0000 |
0x100 |
|
RW |
32 |
0x0000 0000 |
0x104 |
|
RW |
32 |
0x0000 0000 |
0x108 |
|
RW |
32 |
0x0000 0000 |
0x10C |
|
RW |
32 |
0x0080 0000 |
0x110 |
|
RW |
32 |
0x0000 0000 |
0x114 |
|
RW |
32 |
0x0000 0000 |
0x118 |
|
RW |
32 |
0x0000 0000 |
0x11C |
|
RW |
32 |
0x0080 0000 |
0x120 |
|
RW |
32 |
0x0000 0000 |
0x124 |
|
RW |
32 |
0x0000 0000 |
0x128 |
|
RW |
32 |
0x0000 0000 |
0x12C |
|
RW |
32 |
0x0080 0000 |
0x130 |
|
RW |
32 |
0x0000 0000 |
0x134 |
|
RW |
32 |
0x0000 0000 |
0x138 |
|
RW |
32 |
0x0000 0000 |
0x13C |
|
RW |
32 |
0x0080 0000 |
0x140 |
|
RW |
32 |
0x0000 0000 |
0x144 |
|
RW |
32 |
0x0000 0000 |
0x148 |
|
RW |
32 |
0x0000 0000 |
0x14C |
|
RW |
32 |
0x0080 0000 |
0x150 |
|
RW |
32 |
0x0000 0000 |
0x154 |
|
RW |
32 |
0x0000 0000 |
0x158 |
|
RW |
32 |
0x0000 0000 |
0x15C |
|
RW |
32 |
0x0080 0000 |
0x160 |
|
RW |
32 |
0x0000 0000 |
0x164 |
|
RW |
32 |
0x0000 0000 |
0x168 |
|
RW |
32 |
0x0000 0000 |
0x16C |
|
RW |
32 |
0x0080 0000 |
0x170 |
|
RW |
32 |
0x0000 0000 |
0x174 |
|
RW |
32 |
0x0000 0000 |
0x178 |
|
RW |
32 |
0x0000 0000 |
0x17C |
|
RW |
32 |
0x0080 0000 |
0x180 |
|
RW |
32 |
0x0000 0000 |
0x184 |
|
RW |
32 |
0x0000 0000 |
0x188 |
|
RW |
32 |
0x0000 0000 |
0x18C |
|
RW |
32 |
0x0080 0000 |
0x190 |
|
RW |
32 |
0x0000 0000 |
0x194 |
|
RW |
32 |
0x0000 0000 |
0x198 |
|
RW |
32 |
0x0000 0000 |
0x19C |
|
RW |
32 |
0x0080 0000 |
0x1A0 |
|
RW |
32 |
0x0000 0000 |
0x1A4 |
|
RW |
32 |
0x0000 0000 |
0x1A8 |
|
RW |
32 |
0x0000 0000 |
0x1AC |
|
RW |
32 |
0x0080 0000 |
0x1B0 |
|
RW |
32 |
0x0000 0000 |
0x1B4 |
|
RW |
32 |
0x0000 0000 |
0x1B8 |
|
RW |
32 |
0x0000 0000 |
0x1BC |
|
RW |
32 |
0x0080 0000 |
0x1C0 |
|
RW |
32 |
0x0000 0000 |
0x1C4 |
|
RW |
32 |
0x0000 0000 |
0x1C8 |
|
RW |
32 |
0x0000 0000 |
0x1CC |
|
RW |
32 |
0x0080 0000 |
0x1D0 |
|
RW |
32 |
0x0000 0000 |
0x1D4 |
|
RW |
32 |
0x0000 0000 |
0x1D8 |
|
RW |
32 |
0x0000 0000 |
0x1DC |
|
RW |
32 |
0x0080 0000 |
0x1E0 |
|
RW |
32 |
0x0000 0000 |
0x1E4 |
|
RW |
32 |
0x0000 0000 |
0x1E8 |
|
RW |
32 |
0x0000 0000 |
0x1EC |
|
RW |
32 |
0x0080 0000 |
0x1F0 |
|
RW |
32 |
0x0000 0000 |
0x1F4 |
|
RW |
32 |
0x0000 0000 |
0x1F8 |
|
RW |
32 |
0x0000 0000 |
0x1FC |
|
RW |
32 |
0x0080 0000 |
0x200 |
|
RW |
32 |
0x0000 0000 |
0x204 |
|
RW |
32 |
0x0000 0000 |
0x208 |
|
RW |
32 |
0x0000 0000 |
0x20C |
|
RW |
32 |
0x0080 0000 |
0x210 |
|
RW |
32 |
0x0000 0000 |
0x214 |
|
RW |
32 |
0x0000 0000 |
0x218 |
|
RW |
32 |
0x0000 0000 |
0x21C |
|
RW |
32 |
0x0080 0000 |
0x220 |
|
RW |
32 |
0x0000 0000 |
0x224 |
|
RW |
32 |
0x0000 0000 |
0x228 |
|
RW |
32 |
0x0000 0000 |
0x22C |
|
RW |
32 |
0x0000 0000 |
0x230 |
|
RW |
32 |
0x0000 0000 |
0x234 |
|
RW |
32 |
0x0000 0000 |
0x238 |
|
RW |
32 |
0x0000 0000 |
0x23C |
|
RW |
32 |
0x0080 0000 |
0x240 |
|
RW |
32 |
0x0000 0000 |
0x244 |
|
RW |
32 |
0x0000 0000 |
0x248 |
|
RW |
32 |
0x0000 0000 |
0x24C |
|
RW |
32 |
0x0000 0000 |
0x250 |
|
RW |
32 |
0x0000 0000 |
0x254 |
|
RW |
32 |
0x0000 0000 |
0x258 |
|
RW |
32 |
0x0000 0000 |
0x25C |
|
RW |
32 |
0x0080 0000 |
0x260 |
|
RW |
32 |
0x0000 0000 |
0x264 |
|
RW |
32 |
0x0000 0000 |
0x268 |
|
RW |
32 |
0x0000 0000 |
0x26C |
|
RW |
32 |
0x0000 0000 |
0x270 |
|
RW |
32 |
0x0000 0000 |
0x274 |
|
RW |
32 |
0x0000 0000 |
0x278 |
|
RW |
32 |
0x0000 0000 |
0x27C |
|
RW |
32 |
0x0080 0000 |
0x280 |
|
RW |
32 |
0x0000 0000 |
0x284 |
|
RW |
32 |
0x0000 0000 |
0x288 |
|
RW |
32 |
0x0000 0000 |
0x28C |
|
RW |
32 |
0x0000 0000 |
0x290 |
|
RW |
32 |
0x0000 0000 |
0x294 |
|
RW |
32 |
0x0000 0000 |
0x298 |
|
RW |
32 |
0x0000 0000 |
0x29C |
|
RW |
32 |
0x0080 0000 |
0x2A0 |
|
RW |
32 |
0x0000 0000 |
0x2A4 |
|
RW |
32 |
0x0000 0000 |
0x2A8 |
|
RW |
32 |
0x0000 0000 |
0x2AC |
|
RW |
32 |
0x0000 0000 |
0x2B0 |
|
RW |
32 |
0x0000 0000 |
0x2B4 |
|
RW |
32 |
0x0000 0000 |
0x2B8 |
|
RW |
32 |
0x0000 0000 |
0x2BC |
|
RW |
32 |
0x0080 0000 |
0x2C0 |
|
RW |
32 |
0x0000 0000 |
0x2C4 |
|
RW |
32 |
0x0000 0000 |
0x2C8 |
|
RW |
32 |
0x0000 0000 |
0x2CC |
|
RW |
32 |
0x0000 0000 |
0x2D0 |
|
RW |
32 |
0x0000 0000 |
0x2D4 |
|
RW |
32 |
0x0000 0000 |
0x2D8 |
|
RW |
32 |
0x0000 0000 |
0x2DC |
|
RW |
32 |
0x0080 0000 |
0x2E0 |
|
RW |
32 |
0x0000 0000 |
0x2E4 |
|
RW |
32 |
0x0000 0000 |
0x2E8 |
|
RW |
32 |
0x0000 0000 |
0x2EC |
|
RW |
32 |
0x0000 0000 |
0x2F0 |
|
RW |
32 |
0x0000 0000 |
0x2F4 |
|
RW |
32 |
0x0000 0000 |
0x2F8 |
|
RW |
32 |
0x0000 0000 |
0x2FC |
|
RW |
32 |
0x0080 0000 |
0x300 |
|
RW |
32 |
0x0000 0000 |
0x304 |
|
RW |
32 |
0x0000 0000 |
0x308 |
|
RW |
32 |
0x0000 0000 |
0x30C |
|
RW |
32 |
0x0000 0000 |
0x310 |
|
RW |
32 |
0x0000 0000 |
0x314 |
|
RW |
32 |
0x0000 0000 |
0x318 |
|
RW |
32 |
0x0000 0000 |
0x31C |
|
RW |
32 |
0x0080 0000 |
0x320 |
|
RW |
32 |
0x0000 0000 |
0x324 |
|
RW |
32 |
0x0000 0000 |
0x328 |
|
RW |
32 |
0x0000 0000 |
0x32C |
|
RW |
32 |
0x0000 0000 |
0x330 |
|
RW |
32 |
0x0000 0000 |
0x334 |
|
RW |
32 |
0x0000 0000 |
0x338 |
|
RW |
32 |
0x0000 0000 |
0x33C |
|
RW |
32 |
0x0080 0000 |
0x340 |
|
RW |
32 |
0x0000 0000 |
0x344 |
|
RW |
32 |
0x0000 0000 |
0x348 |
|
RW |
32 |
0x0000 0000 |
0x34C |
|
RW |
32 |
0x0000 0000 |
0x350 |
|
RW |
32 |
0x0000 0000 |
0x354 |
|
RW |
32 |
0x0000 0000 |
0x358 |
|
RW |
32 |
0x0000 0000 |
0x35C |
|
RW |
32 |
0x0080 0000 |
0x360 |
|
RW |
32 |
0x0000 0000 |
0x364 |
|
RW |
32 |
0x0000 0000 |
0x368 |
|
RW |
32 |
0x0000 0000 |
0x36C |
|
RW |
32 |
0x0000 0000 |
0x370 |
|
RW |
32 |
0x0000 0000 |
0x374 |
|
RW |
32 |
0x0000 0000 |
0x378 |
|
RW |
32 |
0x0000 0000 |
0x37C |
|
RW |
32 |
0x0080 0000 |
0x380 |
|
RW |
32 |
0x0000 0000 |
0x384 |
|
RW |
32 |
0x0000 0000 |
0x388 |
|
RW |
32 |
0x0000 0000 |
0x38C |
|
RW |
32 |
0x0000 0000 |
0x390 |
|
RW |
32 |
0x0000 0000 |
0x394 |
|
RW |
32 |
0x0000 0000 |
0x398 |
|
RW |
32 |
0x0000 0000 |
0x39C |
|
RW |
32 |
0x0080 0000 |
0x3A0 |
|
RW |
32 |
0x0000 0000 |
0x3A4 |
|
RW |
32 |
0x0000 0000 |
0x3A8 |
|
RW |
32 |
0x0000 0000 |
0x3AC |
|
RW |
32 |
0x0000 0000 |
0x3B0 |
|
RW |
32 |
0x0000 0000 |
0x3B4 |
|
RW |
32 |
0x0000 0000 |
0x3B8 |
|
RW |
32 |
0x0000 0000 |
0x3BC |
|
RW |
32 |
0x0080 0000 |
0x3C0 |
|
RW |
32 |
0x0000 0000 |
0x3C4 |
|
RW |
32 |
0x0000 0000 |
0x3C8 |
|
RW |
32 |
0x0000 0000 |
0x3CC |
|
RW |
32 |
0x0000 0000 |
0x3D0 |
|
RW |
32 |
0x0000 0000 |
0x3D4 |
|
RW |
32 |
0x0000 0000 |
0x3D8 |
|
RW |
32 |
0x0000 0000 |
0x3DC |
|
RW |
32 |
0x0080 0000 |
0x3E0 |
|
RW |
32 |
0x0000 0000 |
0x3E4 |
|
RW |
32 |
0x0000 0000 |
0x3E8 |
|
RW |
32 |
0x0000 0000 |
0x3EC |
|
RW |
32 |
0x0000 0000 |
0x3F0 |
|
RW |
32 |
0x0000 0000 |
0x3F4 |
|
RW |
32 |
0x0000 0000 |
0x3F8 |
|
RW |
32 |
0x0000 0000 |
0x3FC |
|
RW |
32 |
0x0080 0000 |
0x400 |
|
RW |
32 |
0x0000 0000 |
0x404 |
|
RW |
32 |
0x0000 0000 |
0x408 |
|
RW |
32 |
0x0000 0000 |
0x40C |
|
RW |
32 |
0x0000 0000 |
0x410 |
|
RW |
32 |
0x0000 0000 |
0x414 |
|
RW |
32 |
0x0000 0000 |
0x418 |
|
RW |
32 |
0x0000 0000 |
0x41C |
|
RW |
32 |
0x0080 0000 |
0x420 |
|
RW |
32 |
0x0000 0000 |
0x424 |
|
RW |
32 |
0x0000 0000 |
0x428 |
|
RW |
32 |
0x0000 0000 |
0x42C |
|
RW |
32 |
0x0000 0000 |
0x430 |
|
RW |
32 |
0x0000 0000 |
0x434 |
|
RW |
32 |
0x0000 0000 |
0x438 |
|
RW |
32 |
0x0000 0000 |
0x43C |
|
RW |
32 |
0x0080 0000 |
0x440 |
|
RW |
32 |
0x0000 0000 |
0x444 |
|
RW |
32 |
0x0000 0000 |
0x448 |
|
RW |
32 |
0x0000 0000 |
0x44C |
|
RW |
32 |
0x0000 0000 |
0x450 |
|
RW |
32 |
0x0000 0000 |
0x454 |
|
RW |
32 |
0x0000 0000 |
0x458 |
|
RW |
32 |
0x0000 0000 |
0x45C |
|
RW |
32 |
0x0080 0000 |
0x460 |
|
RW |
32 |
0x0000 0000 |
0x464 |
|
RW |
32 |
0x0000 0000 |
0x468 |
|
RW |
32 |
0x0000 0000 |
0x46C |
|
RW |
32 |
0x0000 0000 |
0x470 |
|
RW |
32 |
0x0000 0000 |
0x474 |
|
RW |
32 |
0x0000 0000 |
0x478 |
|
RW |
32 |
0x0000 0000 |
0x47C |
|
RW |
32 |
0x0080 0000 |
0x480 |
|
RW |
32 |
0x0000 0000 |
0x484 |
|
RW |
32 |
0x0000 0000 |
0x488 |
|
RW |
32 |
0x0000 0000 |
0x48C |
|
RW |
32 |
0x0000 0000 |
0x490 |
|
RW |
32 |
0x0000 0000 |
0x494 |
|
RW |
32 |
0x0000 0000 |
0x498 |
|
RW |
32 |
0x0000 0000 |
0x49C |
|
RW |
32 |
0x0080 0000 |
0x4A0 |
|
RW |
32 |
0x0000 0000 |
0x4A4 |
|
RW |
32 |
0x0000 0000 |
0x4A8 |
|
RW |
32 |
0x0000 0000 |
0x4AC |
|
RW |
32 |
0x0000 0000 |
0x4B0 |
|
RW |
32 |
0x0000 0000 |
0x4B4 |
|
RW |
32 |
0x0000 0000 |
0x4B8 |
|
RW |
32 |
0x0000 0000 |
0x4BC |
|
RW |
32 |
0x0080 0000 |
0x4C0 |
|
RW |
32 |
0x0000 0000 |
0x4C4 |
|
RW |
32 |
0x0000 0000 |
0x4C8 |
|
RW |
32 |
0x0000 0000 |
0x4CC |
|
RW |
32 |
0x0000 0000 |
0x4D0 |
|
RW |
32 |
0x0000 0000 |
0x4D4 |
|
RW |
32 |
0x0000 0000 |
0x4D8 |
|
RW |
32 |
0x0000 0000 |
0x4DC |
|
RW |
32 |
0x0080 0000 |
0x4E0 |
|
RW |
32 |
0x0000 0000 |
0x4E4 |
|
RW |
32 |
0x0000 0000 |
0x4E8 |
|
RW |
32 |
0x0000 0000 |
0x4EC |
|
RW |
32 |
0x0000 0000 |
0x4F0 |
|
RW |
32 |
0x0000 0000 |
0x4F4 |
|
RW |
32 |
0x0000 0000 |
0x4F8 |
|
RW |
32 |
0x0000 0000 |
0x4FC |
|
RW |
32 |
0x0080 0000 |
0x500 |
|
RW |
32 |
0x0000 0000 |
0x504 |
|
RW |
32 |
0x0000 0000 |
0x508 |
|
RW |
32 |
0x0000 0000 |
0x50C |
|
RW |
32 |
0x0000 0000 |
0x510 |
|
RW |
32 |
0x0000 0000 |
0x514 |
|
RW |
32 |
0x0000 0000 |
0x518 |
|
RW |
32 |
0x0000 0000 |
0x51C |
|
RW |
32 |
0x0080 0000 |
0x520 |
|
RW |
32 |
0x0000 0000 |
0x524 |
|
RW |
32 |
0x0000 0000 |
0x528 |
|
RW |
32 |
0x0000 0000 |
0x52C |
|
RW |
32 |
0x0000 0000 |
0x530 |
|
RW |
32 |
0x0000 0000 |
0x534 |
|
RW |
32 |
0x0000 0000 |
0x538 |
|
RW |
32 |
0x0000 0000 |
0x53C |
|
RW |
32 |
0x0080 0000 |
0x540 |
|
RW |
32 |
0x0000 0000 |
0x544 |
|
RW |
32 |
0x0000 0000 |
0x548 |
|
RW |
32 |
0x0000 0000 |
0x54C |
|
RW |
32 |
0x0000 0000 |
0x550 |
|
RW |
32 |
0x0000 0000 |
0x554 |
|
RW |
32 |
0x0000 0000 |
0x558 |
|
RW |
32 |
0x0000 0000 |
0x55C |
|
RW |
32 |
0x0080 0000 |
0x560 |
|
RW |
32 |
0x0000 0000 |
0x564 |
|
RW |
32 |
0x0000 0000 |
0x568 |
|
RW |
32 |
0x0000 0000 |
0x56C |
|
RW |
32 |
0x0000 0000 |
0x570 |
|
RW |
32 |
0x0000 0000 |
0x574 |
|
RW |
32 |
0x0000 0000 |
0x578 |
|
RW |
32 |
0x0000 0000 |
0x57C |
|
RW |
32 |
0x0080 0000 |
0x580 |
|
RW |
32 |
0x0000 0000 |
0x584 |
|
RW |
32 |
0x0000 0000 |
0x588 |
|
RW |
32 |
0x0000 0000 |
0x58C |
|
RW |
32 |
0x0000 0000 |
0x590 |
|
RW |
32 |
0x0000 0000 |
0x594 |
|
RW |
32 |
0x0000 0000 |
0x598 |
|
RW |
32 |
0x0000 0000 |
0x59C |
|
RW |
32 |
0x0080 0000 |
0x5A0 |
|
RW |
32 |
0x0000 0000 |
0x5A4 |
|
RW |
32 |
0x0000 0000 |
0x5A8 |
|
RW |
32 |
0x0000 0000 |
0x5AC |
|
RW |
32 |
0x0000 0000 |
0x5B0 |
|
RW |
32 |
0x0000 0000 |
0x5B4 |
|
RW |
32 |
0x0000 0000 |
0x5B8 |
|
RW |
32 |
0x0000 0000 |
0x5BC |
|
RW |
32 |
0x0080 0000 |
0x5C0 |
|
RW |
32 |
0x0000 0000 |
0x5C4 |
|
RW |
32 |
0x0000 0000 |
0x5C8 |
|
RW |
32 |
0x0000 0000 |
0x5CC |
|
RW |
32 |
0x0000 0000 |
0x5D0 |
|
RW |
32 |
0x0000 0000 |
0x5D4 |
|
RW |
32 |
0x0000 0000 |
0x5D8 |
|
RW |
32 |
0x0000 0000 |
0x5DC |
|
RW |
32 |
0x0080 0000 |
0x5E0 |
|
RW |
32 |
0x0000 0000 |
0x5E4 |
|
RW |
32 |
0x0000 0000 |
0x5E8 |
|
RW |
32 |
0x0000 0000 |
0x5EC |
|
RW |
32 |
0x0000 0000 |
0x5F0 |
|
RW |
32 |
0x0000 0000 |
0x5F4 |
|
RW |
32 |
0x0000 0000 |
0x5F8 |
|
RW |
32 |
0x0000 0000 |
0x5FC |
|
RW |
32 |
0x0080 0000 |
0x600 |
|
RW |
32 |
0x0000 0000 |
0x604 |
|
RW |
32 |
0x0000 0000 |
0x608 |
|
RW |
32 |
0x0000 0000 |
0x60C |
|
RW |
32 |
0x0000 0000 |
0x610 |
|
RW |
32 |
0x0000 0000 |
0x614 |
|
RW |
32 |
0x0000 0000 |
0x618 |
|
RW |
32 |
0x0000 0000 |
0x61C |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x2010 C000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x2010 C004 |
|
RO |
32 |
0x0000 0000 |
0x008 |
0x2010 C008 |
|
RO |
32 |
0x0000 0000 |
0x00C |
0x2010 C00C |
|
RO |
32 |
0x0000 0000 |
0x010 |
0x2010 C010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x2010 C014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x2010 C018 |
|
RW |
32 |
0x0000 0000 |
0x01C |
0x2010 C01C |
|
RW |
32 |
0x0080 0000 |
0x020 |
0x2010 C020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x2010 C024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x2010 C028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
0x2010 C02C |
|
RW |
32 |
0x0080 0000 |
0x030 |
0x2010 C030 |
|
RW |
32 |
0x0000 0000 |
0x034 |
0x2010 C034 |
|
RW |
32 |
0x0000 0000 |
0x038 |
0x2010 C038 |
|
RW |
32 |
0x0000 0000 |
0x03C |
0x2010 C03C |
|
RW |
32 |
0x0080 0000 |
0x040 |
0x2010 C040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
0x2010 C044 |
|
RW |
32 |
0x0000 0000 |
0x048 |
0x2010 C048 |
|
RW |
32 |
0x0000 0000 |
0x04C |
0x2010 C04C |
|
RW |
32 |
0x0080 0000 |
0x050 |
0x2010 C050 |
|
RW |
32 |
0x0000 0000 |
0x054 |
0x2010 C054 |
|
RW |
32 |
0x0000 0000 |
0x058 |
0x2010 C058 |
|
RW |
32 |
0x0000 0000 |
0x05C |
0x2010 C05C |
|
RW |
32 |
0x0080 0000 |
0x060 |
0x2010 C060 |
|
RW |
32 |
0x0000 0000 |
0x064 |
0x2010 C064 |
|
RW |
32 |
0x0000 0000 |
0x068 |
0x2010 C068 |
|
RW |
32 |
0x0000 0000 |
0x06C |
0x2010 C06C |
|
RW |
32 |
0x0080 0000 |
0x070 |
0x2010 C070 |
|
RW |
32 |
0x0000 0000 |
0x074 |
0x2010 C074 |
|
RW |
32 |
0x0000 0000 |
0x078 |
0x2010 C078 |
|
RW |
32 |
0x0000 0000 |
0x07C |
0x2010 C07C |
|
RW |
32 |
0x0080 0000 |
0x080 |
0x2010 C080 |
|
RW |
32 |
0x0000 0000 |
0x084 |
0x2010 C084 |
|
RW |
32 |
0x0000 0000 |
0x088 |
0x2010 C088 |
|
RW |
32 |
0x0000 0000 |
0x08C |
0x2010 C08C |
|
RW |
32 |
0x0080 0000 |
0x090 |
0x2010 C090 |
|
RW |
32 |
0x0000 0000 |
0x094 |
0x2010 C094 |
|
RW |
32 |
0x0000 0000 |
0x098 |
0x2010 C098 |
|
RW |
32 |
0x0000 0000 |
0x09C |
0x2010 C09C |
|
RW |
32 |
0x0080 0000 |
0x0A0 |
0x2010 C0A0 |
|
RW |
32 |
0x0000 0000 |
0x0A4 |
0x2010 C0A4 |
|
RW |
32 |
0x0000 0000 |
0x0A8 |
0x2010 C0A8 |
|
RW |
32 |
0x0000 0000 |
0x0AC |
0x2010 C0AC |
|
RW |
32 |
0x0080 0000 |
0x0B0 |
0x2010 C0B0 |
|
RW |
32 |
0x0000 0000 |
0x0B4 |
0x2010 C0B4 |
|
RW |
32 |
0x0000 0000 |
0x0B8 |
0x2010 C0B8 |
|
RW |
32 |
0x0000 0000 |
0x0BC |
0x2010 C0BC |
|
RW |
32 |
0x0080 0000 |
0x0C0 |
0x2010 C0C0 |
|
RW |
32 |
0x0000 0000 |
0x0C4 |
0x2010 C0C4 |
|
RW |
32 |
0x0000 0000 |
0x0C8 |
0x2010 C0C8 |
|
RW |
32 |
0x0000 0000 |
0x0CC |
0x2010 C0CC |
|
RW |
32 |
0x0080 0000 |
0x0D0 |
0x2010 C0D0 |
|
RW |
32 |
0x0000 0000 |
0x0D4 |
0x2010 C0D4 |
|
RW |
32 |
0x0000 0000 |
0x0D8 |
0x2010 C0D8 |
|
RW |
32 |
0x0000 0000 |
0x0DC |
0x2010 C0DC |
|
RW |
32 |
0x0080 0000 |
0x0E0 |
0x2010 C0E0 |
|
RW |
32 |
0x0000 0000 |
0x0E4 |
0x2010 C0E4 |
|
RW |
32 |
0x0000 0000 |
0x0E8 |
0x2010 C0E8 |
|
RW |
32 |
0x0000 0000 |
0x0EC |
0x2010 C0EC |
|
RW |
32 |
0x0080 0000 |
0x0F0 |
0x2010 C0F0 |
|
RW |
32 |
0x0000 0000 |
0x0F4 |
0x2010 C0F4 |
|
RW |
32 |
0x0000 0000 |
0x0F8 |
0x2010 C0F8 |
|
RW |
32 |
0x0000 0000 |
0x0FC |
0x2010 C0FC |
|
RW |
32 |
0x0080 0000 |
0x100 |
0x2010 C100 |
|
RW |
32 |
0x0000 0000 |
0x104 |
0x2010 C104 |
|
RW |
32 |
0x0000 0000 |
0x108 |
0x2010 C108 |
|
RW |
32 |
0x0000 0000 |
0x10C |
0x2010 C10C |
|
RW |
32 |
0x0080 0000 |
0x110 |
0x2010 C110 |
|
RW |
32 |
0x0000 0000 |
0x114 |
0x2010 C114 |
|
RW |
32 |
0x0000 0000 |
0x118 |
0x2010 C118 |
|
RW |
32 |
0x0000 0000 |
0x11C |
0x2010 C11C |
|
RW |
32 |
0x0080 0000 |
0x120 |
0x2010 C120 |
|
RW |
32 |
0x0000 0000 |
0x124 |
0x2010 C124 |
|
RW |
32 |
0x0000 0000 |
0x128 |
0x2010 C128 |
|
RW |
32 |
0x0000 0000 |
0x12C |
0x2010 C12C |
|
RW |
32 |
0x0080 0000 |
0x130 |
0x2010 C130 |
|
RW |
32 |
0x0000 0000 |
0x134 |
0x2010 C134 |
|
RW |
32 |
0x0000 0000 |
0x138 |
0x2010 C138 |
|
RW |
32 |
0x0000 0000 |
0x13C |
0x2010 C13C |
|
RW |
32 |
0x0080 0000 |
0x140 |
0x2010 C140 |
|
RW |
32 |
0x0000 0000 |
0x144 |
0x2010 C144 |
|
RW |
32 |
0x0000 0000 |
0x148 |
0x2010 C148 |
|
RW |
32 |
0x0000 0000 |
0x14C |
0x2010 C14C |
|
RW |
32 |
0x0080 0000 |
0x150 |
0x2010 C150 |
|
RW |
32 |
0x0000 0000 |
0x154 |
0x2010 C154 |
|
RW |
32 |
0x0000 0000 |
0x158 |
0x2010 C158 |
|
RW |
32 |
0x0000 0000 |
0x15C |
0x2010 C15C |
|
RW |
32 |
0x0080 0000 |
0x160 |
0x2010 C160 |
|
RW |
32 |
0x0000 0000 |
0x164 |
0x2010 C164 |
|
RW |
32 |
0x0000 0000 |
0x168 |
0x2010 C168 |
|
RW |
32 |
0x0000 0000 |
0x16C |
0x2010 C16C |
|
RW |
32 |
0x0080 0000 |
0x170 |
0x2010 C170 |
|
RW |
32 |
0x0000 0000 |
0x174 |
0x2010 C174 |
|
RW |
32 |
0x0000 0000 |
0x178 |
0x2010 C178 |
|
RW |
32 |
0x0000 0000 |
0x17C |
0x2010 C17C |
|
RW |
32 |
0x0080 0000 |
0x180 |
0x2010 C180 |
|
RW |
32 |
0x0000 0000 |
0x184 |
0x2010 C184 |
|
RW |
32 |
0x0000 0000 |
0x188 |
0x2010 C188 |
|
RW |
32 |
0x0000 0000 |
0x18C |
0x2010 C18C |
|
RW |
32 |
0x0080 0000 |
0x190 |
0x2010 C190 |
|
RW |
32 |
0x0000 0000 |
0x194 |
0x2010 C194 |
|
RW |
32 |
0x0000 0000 |
0x198 |
0x2010 C198 |
|
RW |
32 |
0x0000 0000 |
0x19C |
0x2010 C19C |
|
RW |
32 |
0x0080 0000 |
0x1A0 |
0x2010 C1A0 |
|
RW |
32 |
0x0000 0000 |
0x1A4 |
0x2010 C1A4 |
|
RW |
32 |
0x0000 0000 |
0x1A8 |
0x2010 C1A8 |
|
RW |
32 |
0x0000 0000 |
0x1AC |
0x2010 C1AC |
|
RW |
32 |
0x0080 0000 |
0x1B0 |
0x2010 C1B0 |
|
RW |
32 |
0x0000 0000 |
0x1B4 |
0x2010 C1B4 |
|
RW |
32 |
0x0000 0000 |
0x1B8 |
0x2010 C1B8 |
|
RW |
32 |
0x0000 0000 |
0x1BC |
0x2010 C1BC |
|
RW |
32 |
0x0080 0000 |
0x1C0 |
0x2010 C1C0 |
|
RW |
32 |
0x0000 0000 |
0x1C4 |
0x2010 C1C4 |
|
RW |
32 |
0x0000 0000 |
0x1C8 |
0x2010 C1C8 |
|
RW |
32 |
0x0000 0000 |
0x1CC |
0x2010 C1CC |
|
RW |
32 |
0x0080 0000 |
0x1D0 |
0x2010 C1D0 |
|
RW |
32 |
0x0000 0000 |
0x1D4 |
0x2010 C1D4 |
|
RW |
32 |
0x0000 0000 |
0x1D8 |
0x2010 C1D8 |
|
RW |
32 |
0x0000 0000 |
0x1DC |
0x2010 C1DC |
|
RW |
32 |
0x0080 0000 |
0x1E0 |
0x2010 C1E0 |
|
RW |
32 |
0x0000 0000 |
0x1E4 |
0x2010 C1E4 |
|
RW |
32 |
0x0000 0000 |
0x1E8 |
0x2010 C1E8 |
|
RW |
32 |
0x0000 0000 |
0x1EC |
0x2010 C1EC |
|
RW |
32 |
0x0080 0000 |
0x1F0 |
0x2010 C1F0 |
|
RW |
32 |
0x0000 0000 |
0x1F4 |
0x2010 C1F4 |
|
RW |
32 |
0x0000 0000 |
0x1F8 |
0x2010 C1F8 |
|
RW |
32 |
0x0000 0000 |
0x1FC |
0x2010 C1FC |
|
RW |
32 |
0x0080 0000 |
0x200 |
0x2010 C200 |
|
RW |
32 |
0x0000 0000 |
0x204 |
0x2010 C204 |
|
RW |
32 |
0x0000 0000 |
0x208 |
0x2010 C208 |
|
RW |
32 |
0x0000 0000 |
0x20C |
0x2010 C20C |
|
RW |
32 |
0x0080 0000 |
0x210 |
0x2010 C210 |
|
RW |
32 |
0x0000 0000 |
0x214 |
0x2010 C214 |
|
RW |
32 |
0x0000 0000 |
0x218 |
0x2010 C218 |
|
RW |
32 |
0x0000 0000 |
0x21C |
0x2010 C21C |
|
RW |
32 |
0x0080 0000 |
0x220 |
0x2010 C220 |
|
RW |
32 |
0x0000 0000 |
0x224 |
0x2010 C224 |
|
RW |
32 |
0x0000 0000 |
0x228 |
0x2010 C228 |
|
RW |
32 |
0x0000 0000 |
0x22C |
0x2010 C22C |
|
RW |
32 |
0x0000 0000 |
0x230 |
0x2010 C230 |
|
RW |
32 |
0x0000 0000 |
0x234 |
0x2010 C234 |
|
RW |
32 |
0x0000 0000 |
0x238 |
0x2010 C238 |
|
RW |
32 |
0x0000 0000 |
0x23C |
0x2010 C23C |
|
RW |
32 |
0x0080 0000 |
0x240 |
0x2010 C240 |
|
RW |
32 |
0x0000 0000 |
0x244 |
0x2010 C244 |
|
RW |
32 |
0x0000 0000 |
0x248 |
0x2010 C248 |
|
RW |
32 |
0x0000 0000 |
0x24C |
0x2010 C24C |
|
RW |
32 |
0x0000 0000 |
0x250 |
0x2010 C250 |
|
RW |
32 |
0x0000 0000 |
0x254 |
0x2010 C254 |
|
RW |
32 |
0x0000 0000 |
0x258 |
0x2010 C258 |
|
RW |
32 |
0x0000 0000 |
0x25C |
0x2010 C25C |
|
RW |
32 |
0x0080 0000 |
0x260 |
0x2010 C260 |
|
RW |
32 |
0x0000 0000 |
0x264 |
0x2010 C264 |
|
RW |
32 |
0x0000 0000 |
0x268 |
0x2010 C268 |
|
RW |
32 |
0x0000 0000 |
0x26C |
0x2010 C26C |
|
RW |
32 |
0x0000 0000 |
0x270 |
0x2010 C270 |
|
RW |
32 |
0x0000 0000 |
0x274 |
0x2010 C274 |
|
RW |
32 |
0x0000 0000 |
0x278 |
0x2010 C278 |
|
RW |
32 |
0x0000 0000 |
0x27C |
0x2010 C27C |
|
RW |
32 |
0x0080 0000 |
0x280 |
0x2010 C280 |
|
RW |
32 |
0x0000 0000 |
0x284 |
0x2010 C284 |
|
RW |
32 |
0x0000 0000 |
0x288 |
0x2010 C288 |
|
RW |
32 |
0x0000 0000 |
0x28C |
0x2010 C28C |
|
RW |
32 |
0x0000 0000 |
0x290 |
0x2010 C290 |
|
RW |
32 |
0x0000 0000 |
0x294 |
0x2010 C294 |
|
RW |
32 |
0x0000 0000 |
0x298 |
0x2010 C298 |
|
RW |
32 |
0x0000 0000 |
0x29C |
0x2010 C29C |
|
RW |
32 |
0x0080 0000 |
0x2A0 |
0x2010 C2A0 |
|
RW |
32 |
0x0000 0000 |
0x2A4 |
0x2010 C2A4 |
|
RW |
32 |
0x0000 0000 |
0x2A8 |
0x2010 C2A8 |
|
RW |
32 |
0x0000 0000 |
0x2AC |
0x2010 C2AC |
|
RW |
32 |
0x0000 0000 |
0x2B0 |
0x2010 C2B0 |
|
RW |
32 |
0x0000 0000 |
0x2B4 |
0x2010 C2B4 |
|
RW |
32 |
0x0000 0000 |
0x2B8 |
0x2010 C2B8 |
|
RW |
32 |
0x0000 0000 |
0x2BC |
0x2010 C2BC |
|
RW |
32 |
0x0080 0000 |
0x2C0 |
0x2010 C2C0 |
|
RW |
32 |
0x0000 0000 |
0x2C4 |
0x2010 C2C4 |
|
RW |
32 |
0x0000 0000 |
0x2C8 |
0x2010 C2C8 |
|
RW |
32 |
0x0000 0000 |
0x2CC |
0x2010 C2CC |
|
RW |
32 |
0x0000 0000 |
0x2D0 |
0x2010 C2D0 |
|
RW |
32 |
0x0000 0000 |
0x2D4 |
0x2010 C2D4 |
|
RW |
32 |
0x0000 0000 |
0x2D8 |
0x2010 C2D8 |
|
RW |
32 |
0x0000 0000 |
0x2DC |
0x2010 C2DC |
|
RW |
32 |
0x0080 0000 |
0x2E0 |
0x2010 C2E0 |
|
RW |
32 |
0x0000 0000 |
0x2E4 |
0x2010 C2E4 |
|
RW |
32 |
0x0000 0000 |
0x2E8 |
0x2010 C2E8 |
|
RW |
32 |
0x0000 0000 |
0x2EC |
0x2010 C2EC |
|
RW |
32 |
0x0000 0000 |
0x2F0 |
0x2010 C2F0 |
|
RW |
32 |
0x0000 0000 |
0x2F4 |
0x2010 C2F4 |
|
RW |
32 |
0x0000 0000 |
0x2F8 |
0x2010 C2F8 |
|
RW |
32 |
0x0000 0000 |
0x2FC |
0x2010 C2FC |
|
RW |
32 |
0x0080 0000 |
0x300 |
0x2010 C300 |
|
RW |
32 |
0x0000 0000 |
0x304 |
0x2010 C304 |
|
RW |
32 |
0x0000 0000 |
0x308 |
0x2010 C308 |
|
RW |
32 |
0x0000 0000 |
0x30C |
0x2010 C30C |
|
RW |
32 |
0x0000 0000 |
0x310 |
0x2010 C310 |
|
RW |
32 |
0x0000 0000 |
0x314 |
0x2010 C314 |
|
RW |
32 |
0x0000 0000 |
0x318 |
0x2010 C318 |
|
RW |
32 |
0x0000 0000 |
0x31C |
0x2010 C31C |
|
RW |
32 |
0x0080 0000 |
0x320 |
0x2010 C320 |
|
RW |
32 |
0x0000 0000 |
0x324 |
0x2010 C324 |
|
RW |
32 |
0x0000 0000 |
0x328 |
0x2010 C328 |
|
RW |
32 |
0x0000 0000 |
0x32C |
0x2010 C32C |
|
RW |
32 |
0x0000 0000 |
0x330 |
0x2010 C330 |
|
RW |
32 |
0x0000 0000 |
0x334 |
0x2010 C334 |
|
RW |
32 |
0x0000 0000 |
0x338 |
0x2010 C338 |
|
RW |
32 |
0x0000 0000 |
0x33C |
0x2010 C33C |
|
RW |
32 |
0x0080 0000 |
0x340 |
0x2010 C340 |
|
RW |
32 |
0x0000 0000 |
0x344 |
0x2010 C344 |
|
RW |
32 |
0x0000 0000 |
0x348 |
0x2010 C348 |
|
RW |
32 |
0x0000 0000 |
0x34C |
0x2010 C34C |
|
RW |
32 |
0x0000 0000 |
0x350 |
0x2010 C350 |
|
RW |
32 |
0x0000 0000 |
0x354 |
0x2010 C354 |
|
RW |
32 |
0x0000 0000 |
0x358 |
0x2010 C358 |
|
RW |
32 |
0x0000 0000 |
0x35C |
0x2010 C35C |
|
RW |
32 |
0x0080 0000 |
0x360 |
0x2010 C360 |
|
RW |
32 |
0x0000 0000 |
0x364 |
0x2010 C364 |
|
RW |
32 |
0x0000 0000 |
0x368 |
0x2010 C368 |
|
RW |
32 |
0x0000 0000 |
0x36C |
0x2010 C36C |
|
RW |
32 |
0x0000 0000 |
0x370 |
0x2010 C370 |
|
RW |
32 |
0x0000 0000 |
0x374 |
0x2010 C374 |
|
RW |
32 |
0x0000 0000 |
0x378 |
0x2010 C378 |
|
RW |
32 |
0x0000 0000 |
0x37C |
0x2010 C37C |
|
RW |
32 |
0x0080 0000 |
0x380 |
0x2010 C380 |
|
RW |
32 |
0x0000 0000 |
0x384 |
0x2010 C384 |
|
RW |
32 |
0x0000 0000 |
0x388 |
0x2010 C388 |
|
RW |
32 |
0x0000 0000 |
0x38C |
0x2010 C38C |
|
RW |
32 |
0x0000 0000 |
0x390 |
0x2010 C390 |
|
RW |
32 |
0x0000 0000 |
0x394 |
0x2010 C394 |
|
RW |
32 |
0x0000 0000 |
0x398 |
0x2010 C398 |
|
RW |
32 |
0x0000 0000 |
0x39C |
0x2010 C39C |
|
RW |
32 |
0x0080 0000 |
0x3A0 |
0x2010 C3A0 |
|
RW |
32 |
0x0000 0000 |
0x3A4 |
0x2010 C3A4 |
|
RW |
32 |
0x0000 0000 |
0x3A8 |
0x2010 C3A8 |
|
RW |
32 |
0x0000 0000 |
0x3AC |
0x2010 C3AC |
|
RW |
32 |
0x0000 0000 |
0x3B0 |
0x2010 C3B0 |
|
RW |
32 |
0x0000 0000 |
0x3B4 |
0x2010 C3B4 |
|
RW |
32 |
0x0000 0000 |
0x3B8 |
0x2010 C3B8 |
|
RW |
32 |
0x0000 0000 |
0x3BC |
0x2010 C3BC |
|
RW |
32 |
0x0080 0000 |
0x3C0 |
0x2010 C3C0 |
|
RW |
32 |
0x0000 0000 |
0x3C4 |
0x2010 C3C4 |
|
RW |
32 |
0x0000 0000 |
0x3C8 |
0x2010 C3C8 |
|
RW |
32 |
0x0000 0000 |
0x3CC |
0x2010 C3CC |
|
RW |
32 |
0x0000 0000 |
0x3D0 |
0x2010 C3D0 |
|
RW |
32 |
0x0000 0000 |
0x3D4 |
0x2010 C3D4 |
|
RW |
32 |
0x0000 0000 |
0x3D8 |
0x2010 C3D8 |
|
RW |
32 |
0x0000 0000 |
0x3DC |
0x2010 C3DC |
|
RW |
32 |
0x0080 0000 |
0x3E0 |
0x2010 C3E0 |
|
RW |
32 |
0x0000 0000 |
0x3E4 |
0x2010 C3E4 |
|
RW |
32 |
0x0000 0000 |
0x3E8 |
0x2010 C3E8 |
|
RW |
32 |
0x0000 0000 |
0x3EC |
0x2010 C3EC |
|
RW |
32 |
0x0000 0000 |
0x3F0 |
0x2010 C3F0 |
|
RW |
32 |
0x0000 0000 |
0x3F4 |
0x2010 C3F4 |
|
RW |
32 |
0x0000 0000 |
0x3F8 |
0x2010 C3F8 |
|
RW |
32 |
0x0000 0000 |
0x3FC |
0x2010 C3FC |
|
RW |
32 |
0x0080 0000 |
0x400 |
0x2010 C400 |
|
RW |
32 |
0x0000 0000 |
0x404 |
0x2010 C404 |
|
RW |
32 |
0x0000 0000 |
0x408 |
0x2010 C408 |
|
RW |
32 |
0x0000 0000 |
0x40C |
0x2010 C40C |
|
RW |
32 |
0x0000 0000 |
0x410 |
0x2010 C410 |
|
RW |
32 |
0x0000 0000 |
0x414 |
0x2010 C414 |
|
RW |
32 |
0x0000 0000 |
0x418 |
0x2010 C418 |
|
RW |
32 |
0x0000 0000 |
0x41C |
0x2010 C41C |
|
RW |
32 |
0x0080 0000 |
0x420 |
0x2010 C420 |
|
RW |
32 |
0x0000 0000 |
0x424 |
0x2010 C424 |
|
RW |
32 |
0x0000 0000 |
0x428 |
0x2010 C428 |
|
RW |
32 |
0x0000 0000 |
0x42C |
0x2010 C42C |
|
RW |
32 |
0x0000 0000 |
0x430 |
0x2010 C430 |
|
RW |
32 |
0x0000 0000 |
0x434 |
0x2010 C434 |
|
RW |
32 |
0x0000 0000 |
0x438 |
0x2010 C438 |
|
RW |
32 |
0x0000 0000 |
0x43C |
0x2010 C43C |
|
RW |
32 |
0x0080 0000 |
0x440 |
0x2010 C440 |
|
RW |
32 |
0x0000 0000 |
0x444 |
0x2010 C444 |
|
RW |
32 |
0x0000 0000 |
0x448 |
0x2010 C448 |
|
RW |
32 |
0x0000 0000 |
0x44C |
0x2010 C44C |
|
RW |
32 |
0x0000 0000 |
0x450 |
0x2010 C450 |
|
RW |
32 |
0x0000 0000 |
0x454 |
0x2010 C454 |
|
RW |
32 |
0x0000 0000 |
0x458 |
0x2010 C458 |
|
RW |
32 |
0x0000 0000 |
0x45C |
0x2010 C45C |
|
RW |
32 |
0x0080 0000 |
0x460 |
0x2010 C460 |
|
RW |
32 |
0x0000 0000 |
0x464 |
0x2010 C464 |
|
RW |
32 |
0x0000 0000 |
0x468 |
0x2010 C468 |
|
RW |
32 |
0x0000 0000 |
0x46C |
0x2010 C46C |
|
RW |
32 |
0x0000 0000 |
0x470 |
0x2010 C470 |
|
RW |
32 |
0x0000 0000 |
0x474 |
0x2010 C474 |
|
RW |
32 |
0x0000 0000 |
0x478 |
0x2010 C478 |
|
RW |
32 |
0x0000 0000 |
0x47C |
0x2010 C47C |
|
RW |
32 |
0x0080 0000 |
0x480 |
0x2010 C480 |
|
RW |
32 |
0x0000 0000 |
0x484 |
0x2010 C484 |
|
RW |
32 |
0x0000 0000 |
0x488 |
0x2010 C488 |
|
RW |
32 |
0x0000 0000 |
0x48C |
0x2010 C48C |
|
RW |
32 |
0x0000 0000 |
0x490 |
0x2010 C490 |
|
RW |
32 |
0x0000 0000 |
0x494 |
0x2010 C494 |
|
RW |
32 |
0x0000 0000 |
0x498 |
0x2010 C498 |
|
RW |
32 |
0x0000 0000 |
0x49C |
0x2010 C49C |
|
RW |
32 |
0x0080 0000 |
0x4A0 |
0x2010 C4A0 |
|
RW |
32 |
0x0000 0000 |
0x4A4 |
0x2010 C4A4 |
|
RW |
32 |
0x0000 0000 |
0x4A8 |
0x2010 C4A8 |
|
RW |
32 |
0x0000 0000 |
0x4AC |
0x2010 C4AC |
|
RW |
32 |
0x0000 0000 |
0x4B0 |
0x2010 C4B0 |
|
RW |
32 |
0x0000 0000 |
0x4B4 |
0x2010 C4B4 |
|
RW |
32 |
0x0000 0000 |
0x4B8 |
0x2010 C4B8 |
|
RW |
32 |
0x0000 0000 |
0x4BC |
0x2010 C4BC |
|
RW |
32 |
0x0080 0000 |
0x4C0 |
0x2010 C4C0 |
|
RW |
32 |
0x0000 0000 |
0x4C4 |
0x2010 C4C4 |
|
RW |
32 |
0x0000 0000 |
0x4C8 |
0x2010 C4C8 |
|
RW |
32 |
0x0000 0000 |
0x4CC |
0x2010 C4CC |
|
RW |
32 |
0x0000 0000 |
0x4D0 |
0x2010 C4D0 |
|
RW |
32 |
0x0000 0000 |
0x4D4 |
0x2010 C4D4 |
|
RW |
32 |
0x0000 0000 |
0x4D8 |
0x2010 C4D8 |
|
RW |
32 |
0x0000 0000 |
0x4DC |
0x2010 C4DC |
|
RW |
32 |
0x0080 0000 |
0x4E0 |
0x2010 C4E0 |
|
RW |
32 |
0x0000 0000 |
0x4E4 |
0x2010 C4E4 |
|
RW |
32 |
0x0000 0000 |
0x4E8 |
0x2010 C4E8 |
|
RW |
32 |
0x0000 0000 |
0x4EC |
0x2010 C4EC |
|
RW |
32 |
0x0000 0000 |
0x4F0 |
0x2010 C4F0 |
|
RW |
32 |
0x0000 0000 |
0x4F4 |
0x2010 C4F4 |
|
RW |
32 |
0x0000 0000 |
0x4F8 |
0x2010 C4F8 |
|
RW |
32 |
0x0000 0000 |
0x4FC |
0x2010 C4FC |
|
RW |
32 |
0x0080 0000 |
0x500 |
0x2010 C500 |
|
RW |
32 |
0x0000 0000 |
0x504 |
0x2010 C504 |
|
RW |
32 |
0x0000 0000 |
0x508 |
0x2010 C508 |
|
RW |
32 |
0x0000 0000 |
0x50C |
0x2010 C50C |
|
RW |
32 |
0x0000 0000 |
0x510 |
0x2010 C510 |
|
RW |
32 |
0x0000 0000 |
0x514 |
0x2010 C514 |
|
RW |
32 |
0x0000 0000 |
0x518 |
0x2010 C518 |
|
RW |
32 |
0x0000 0000 |
0x51C |
0x2010 C51C |
|
RW |
32 |
0x0080 0000 |
0x520 |
0x2010 C520 |
|
RW |
32 |
0x0000 0000 |
0x524 |
0x2010 C524 |
|
RW |
32 |
0x0000 0000 |
0x528 |
0x2010 C528 |
|
RW |
32 |
0x0000 0000 |
0x52C |
0x2010 C52C |
|
RW |
32 |
0x0000 0000 |
0x530 |
0x2010 C530 |
|
RW |
32 |
0x0000 0000 |
0x534 |
0x2010 C534 |
|
RW |
32 |
0x0000 0000 |
0x538 |
0x2010 C538 |
|
RW |
32 |
0x0000 0000 |
0x53C |
0x2010 C53C |
|
RW |
32 |
0x0080 0000 |
0x540 |
0x2010 C540 |
|
RW |
32 |
0x0000 0000 |
0x544 |
0x2010 C544 |
|
RW |
32 |
0x0000 0000 |
0x548 |
0x2010 C548 |
|
RW |
32 |
0x0000 0000 |
0x54C |
0x2010 C54C |
|
RW |
32 |
0x0000 0000 |
0x550 |
0x2010 C550 |
|
RW |
32 |
0x0000 0000 |
0x554 |
0x2010 C554 |
|
RW |
32 |
0x0000 0000 |
0x558 |
0x2010 C558 |
|
RW |
32 |
0x0000 0000 |
0x55C |
0x2010 C55C |
|
RW |
32 |
0x0080 0000 |
0x560 |
0x2010 C560 |
|
RW |
32 |
0x0000 0000 |
0x564 |
0x2010 C564 |
|
RW |
32 |
0x0000 0000 |
0x568 |
0x2010 C568 |
|
RW |
32 |
0x0000 0000 |
0x56C |
0x2010 C56C |
|
RW |
32 |
0x0000 0000 |
0x570 |
0x2010 C570 |
|
RW |
32 |
0x0000 0000 |
0x574 |
0x2010 C574 |
|
RW |
32 |
0x0000 0000 |
0x578 |
0x2010 C578 |
|
RW |
32 |
0x0000 0000 |
0x57C |
0x2010 C57C |
|
RW |
32 |
0x0080 0000 |
0x580 |
0x2010 C580 |
|
RW |
32 |
0x0000 0000 |
0x584 |
0x2010 C584 |
|
RW |
32 |
0x0000 0000 |
0x588 |
0x2010 C588 |
|
RW |
32 |
0x0000 0000 |
0x58C |
0x2010 C58C |
|
RW |
32 |
0x0000 0000 |
0x590 |
0x2010 C590 |
|
RW |
32 |
0x0000 0000 |
0x594 |
0x2010 C594 |
|
RW |
32 |
0x0000 0000 |
0x598 |
0x2010 C598 |
|
RW |
32 |
0x0000 0000 |
0x59C |
0x2010 C59C |
|
RW |
32 |
0x0080 0000 |
0x5A0 |
0x2010 C5A0 |
|
RW |
32 |
0x0000 0000 |
0x5A4 |
0x2010 C5A4 |
|
RW |
32 |
0x0000 0000 |
0x5A8 |
0x2010 C5A8 |
|
RW |
32 |
0x0000 0000 |
0x5AC |
0x2010 C5AC |
|
RW |
32 |
0x0000 0000 |
0x5B0 |
0x2010 C5B0 |
|
RW |
32 |
0x0000 0000 |
0x5B4 |
0x2010 C5B4 |
|
RW |
32 |
0x0000 0000 |
0x5B8 |
0x2010 C5B8 |
|
RW |
32 |
0x0000 0000 |
0x5BC |
0x2010 C5BC |
|
RW |
32 |
0x0080 0000 |
0x5C0 |
0x2010 C5C0 |
|
RW |
32 |
0x0000 0000 |
0x5C4 |
0x2010 C5C4 |
|
RW |
32 |
0x0000 0000 |
0x5C8 |
0x2010 C5C8 |
|
RW |
32 |
0x0000 0000 |
0x5CC |
0x2010 C5CC |
|
RW |
32 |
0x0000 0000 |
0x5D0 |
0x2010 C5D0 |
|
RW |
32 |
0x0000 0000 |
0x5D4 |
0x2010 C5D4 |
|
RW |
32 |
0x0000 0000 |
0x5D8 |
0x2010 C5D8 |
|
RW |
32 |
0x0000 0000 |
0x5DC |
0x2010 C5DC |
|
RW |
32 |
0x0080 0000 |
0x5E0 |
0x2010 C5E0 |
|
RW |
32 |
0x0000 0000 |
0x5E4 |
0x2010 C5E4 |
|
RW |
32 |
0x0000 0000 |
0x5E8 |
0x2010 C5E8 |
|
RW |
32 |
0x0000 0000 |
0x5EC |
0x2010 C5EC |
|
RW |
32 |
0x0000 0000 |
0x5F0 |
0x2010 C5F0 |
|
RW |
32 |
0x0000 0000 |
0x5F4 |
0x2010 C5F4 |
|
RW |
32 |
0x0000 0000 |
0x5F8 |
0x2010 C5F8 |
|
RW |
32 |
0x0000 0000 |
0x5FC |
0x2010 C5FC |
|
RW |
32 |
0x0080 0000 |
0x600 |
0x2010 C600 |
|
RW |
32 |
0x0000 0000 |
0x604 |
0x2010 C604 |
|
RW |
32 |
0x0000 0000 |
0x608 |
0x2010 C608 |
|
RW |
32 |
0x0000 0000 |
0x60C |
0x2010 C60C |
|
RW |
32 |
0x0000 0000 |
0x610 |
0x2010 C610 |
|
RW |
32 |
0x0000 0000 |
0x614 |
0x2010 C614 |
|
RW |
32 |
0x0000 0000 |
0x618 |
0x2010 C618 |
|
RW |
32 |
0x0000 0000 |
0x61C |
0x2010 C61C |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x2010 D000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x2010 D004 |
|
RO |
32 |
0x0000 0000 |
0x008 |
0x2010 D008 |
|
RO |
32 |
0x0000 0000 |
0x00C |
0x2010 D00C |
|
RO |
32 |
0x0000 0000 |
0x010 |
0x2010 D010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x2010 D014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x2010 D018 |
|
RW |
32 |
0x0000 0000 |
0x01C |
0x2010 D01C |
|
RW |
32 |
0x0080 0000 |
0x020 |
0x2010 D020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x2010 D024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x2010 D028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
0x2010 D02C |
|
RW |
32 |
0x0080 0000 |
0x030 |
0x2010 D030 |
|
RW |
32 |
0x0000 0000 |
0x034 |
0x2010 D034 |
|
RW |
32 |
0x0000 0000 |
0x038 |
0x2010 D038 |
|
RW |
32 |
0x0000 0000 |
0x03C |
0x2010 D03C |
|
RW |
32 |
0x0080 0000 |
0x040 |
0x2010 D040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
0x2010 D044 |
|
RW |
32 |
0x0000 0000 |
0x048 |
0x2010 D048 |
|
RW |
32 |
0x0000 0000 |
0x04C |
0x2010 D04C |
|
RW |
32 |
0x0080 0000 |
0x050 |
0x2010 D050 |
|
RW |
32 |
0x0000 0000 |
0x054 |
0x2010 D054 |
|
RW |
32 |
0x0000 0000 |
0x058 |
0x2010 D058 |
|
RW |
32 |
0x0000 0000 |
0x05C |
0x2010 D05C |
|
RW |
32 |
0x0080 0000 |
0x060 |
0x2010 D060 |
|
RW |
32 |
0x0000 0000 |
0x064 |
0x2010 D064 |
|
RW |
32 |
0x0000 0000 |
0x068 |
0x2010 D068 |
|
RW |
32 |
0x0000 0000 |
0x06C |
0x2010 D06C |
|
RW |
32 |
0x0080 0000 |
0x070 |
0x2010 D070 |
|
RW |
32 |
0x0000 0000 |
0x074 |
0x2010 D074 |
|
RW |
32 |
0x0000 0000 |
0x078 |
0x2010 D078 |
|
RW |
32 |
0x0000 0000 |
0x07C |
0x2010 D07C |
|
RW |
32 |
0x0080 0000 |
0x080 |
0x2010 D080 |
|
RW |
32 |
0x0000 0000 |
0x084 |
0x2010 D084 |
|
RW |
32 |
0x0000 0000 |
0x088 |
0x2010 D088 |
|
RW |
32 |
0x0000 0000 |
0x08C |
0x2010 D08C |
|
RW |
32 |
0x0080 0000 |
0x090 |
0x2010 D090 |
|
RW |
32 |
0x0000 0000 |
0x094 |
0x2010 D094 |
|
RW |
32 |
0x0000 0000 |
0x098 |
0x2010 D098 |
|
RW |
32 |
0x0000 0000 |
0x09C |
0x2010 D09C |
|
RW |
32 |
0x0080 0000 |
0x0A0 |
0x2010 D0A0 |
|
RW |
32 |
0x0000 0000 |
0x0A4 |
0x2010 D0A4 |
|
RW |
32 |
0x0000 0000 |
0x0A8 |
0x2010 D0A8 |
|
RW |
32 |
0x0000 0000 |
0x0AC |
0x2010 D0AC |
|
RW |
32 |
0x0080 0000 |
0x0B0 |
0x2010 D0B0 |
|
RW |
32 |
0x0000 0000 |
0x0B4 |
0x2010 D0B4 |
|
RW |
32 |
0x0000 0000 |
0x0B8 |
0x2010 D0B8 |
|
RW |
32 |
0x0000 0000 |
0x0BC |
0x2010 D0BC |
|
RW |
32 |
0x0080 0000 |
0x0C0 |
0x2010 D0C0 |
|
RW |
32 |
0x0000 0000 |
0x0C4 |
0x2010 D0C4 |
|
RW |
32 |
0x0000 0000 |
0x0C8 |
0x2010 D0C8 |
|
RW |
32 |
0x0000 0000 |
0x0CC |
0x2010 D0CC |
|
RW |
32 |
0x0080 0000 |
0x0D0 |
0x2010 D0D0 |
|
RW |
32 |
0x0000 0000 |
0x0D4 |
0x2010 D0D4 |
|
RW |
32 |
0x0000 0000 |
0x0D8 |
0x2010 D0D8 |
|
RW |
32 |
0x0000 0000 |
0x0DC |
0x2010 D0DC |
|
RW |
32 |
0x0080 0000 |
0x0E0 |
0x2010 D0E0 |
|
RW |
32 |
0x0000 0000 |
0x0E4 |
0x2010 D0E4 |
|
RW |
32 |
0x0000 0000 |
0x0E8 |
0x2010 D0E8 |
|
RW |
32 |
0x0000 0000 |
0x0EC |
0x2010 D0EC |
|
RW |
32 |
0x0080 0000 |
0x0F0 |
0x2010 D0F0 |
|
RW |
32 |
0x0000 0000 |
0x0F4 |
0x2010 D0F4 |
|
RW |
32 |
0x0000 0000 |
0x0F8 |
0x2010 D0F8 |
|
RW |
32 |
0x0000 0000 |
0x0FC |
0x2010 D0FC |
|
RW |
32 |
0x0080 0000 |
0x100 |
0x2010 D100 |
|
RW |
32 |
0x0000 0000 |
0x104 |
0x2010 D104 |
|
RW |
32 |
0x0000 0000 |
0x108 |
0x2010 D108 |
|
RW |
32 |
0x0000 0000 |
0x10C |
0x2010 D10C |
|
RW |
32 |
0x0080 0000 |
0x110 |
0x2010 D110 |
|
RW |
32 |
0x0000 0000 |
0x114 |
0x2010 D114 |
|
RW |
32 |
0x0000 0000 |
0x118 |
0x2010 D118 |
|
RW |
32 |
0x0000 0000 |
0x11C |
0x2010 D11C |
|
RW |
32 |
0x0080 0000 |
0x120 |
0x2010 D120 |
|
RW |
32 |
0x0000 0000 |
0x124 |
0x2010 D124 |
|
RW |
32 |
0x0000 0000 |
0x128 |
0x2010 D128 |
|
RW |
32 |
0x0000 0000 |
0x12C |
0x2010 D12C |
|
RW |
32 |
0x0080 0000 |
0x130 |
0x2010 D130 |
|
RW |
32 |
0x0000 0000 |
0x134 |
0x2010 D134 |
|
RW |
32 |
0x0000 0000 |
0x138 |
0x2010 D138 |
|
RW |
32 |
0x0000 0000 |
0x13C |
0x2010 D13C |
|
RW |
32 |
0x0080 0000 |
0x140 |
0x2010 D140 |
|
RW |
32 |
0x0000 0000 |
0x144 |
0x2010 D144 |
|
RW |
32 |
0x0000 0000 |
0x148 |
0x2010 D148 |
|
RW |
32 |
0x0000 0000 |
0x14C |
0x2010 D14C |
|
RW |
32 |
0x0080 0000 |
0x150 |
0x2010 D150 |
|
RW |
32 |
0x0000 0000 |
0x154 |
0x2010 D154 |
|
RW |
32 |
0x0000 0000 |
0x158 |
0x2010 D158 |
|
RW |
32 |
0x0000 0000 |
0x15C |
0x2010 D15C |
|
RW |
32 |
0x0080 0000 |
0x160 |
0x2010 D160 |
|
RW |
32 |
0x0000 0000 |
0x164 |
0x2010 D164 |
|
RW |
32 |
0x0000 0000 |
0x168 |
0x2010 D168 |
|
RW |
32 |
0x0000 0000 |
0x16C |
0x2010 D16C |
|
RW |
32 |
0x0080 0000 |
0x170 |
0x2010 D170 |
|
RW |
32 |
0x0000 0000 |
0x174 |
0x2010 D174 |
|
RW |
32 |
0x0000 0000 |
0x178 |
0x2010 D178 |
|
RW |
32 |
0x0000 0000 |
0x17C |
0x2010 D17C |
|
RW |
32 |
0x0080 0000 |
0x180 |
0x2010 D180 |
|
RW |
32 |
0x0000 0000 |
0x184 |
0x2010 D184 |
|
RW |
32 |
0x0000 0000 |
0x188 |
0x2010 D188 |
|
RW |
32 |
0x0000 0000 |
0x18C |
0x2010 D18C |
|
RW |
32 |
0x0080 0000 |
0x190 |
0x2010 D190 |
|
RW |
32 |
0x0000 0000 |
0x194 |
0x2010 D194 |
|
RW |
32 |
0x0000 0000 |
0x198 |
0x2010 D198 |
|
RW |
32 |
0x0000 0000 |
0x19C |
0x2010 D19C |
|
RW |
32 |
0x0080 0000 |
0x1A0 |
0x2010 D1A0 |
|
RW |
32 |
0x0000 0000 |
0x1A4 |
0x2010 D1A4 |
|
RW |
32 |
0x0000 0000 |
0x1A8 |
0x2010 D1A8 |
|
RW |
32 |
0x0000 0000 |
0x1AC |
0x2010 D1AC |
|
RW |
32 |
0x0080 0000 |
0x1B0 |
0x2010 D1B0 |
|
RW |
32 |
0x0000 0000 |
0x1B4 |
0x2010 D1B4 |
|
RW |
32 |
0x0000 0000 |
0x1B8 |
0x2010 D1B8 |
|
RW |
32 |
0x0000 0000 |
0x1BC |
0x2010 D1BC |
|
RW |
32 |
0x0080 0000 |
0x1C0 |
0x2010 D1C0 |
|
RW |
32 |
0x0000 0000 |
0x1C4 |
0x2010 D1C4 |
|
RW |
32 |
0x0000 0000 |
0x1C8 |
0x2010 D1C8 |
|
RW |
32 |
0x0000 0000 |
0x1CC |
0x2010 D1CC |
|
RW |
32 |
0x0080 0000 |
0x1D0 |
0x2010 D1D0 |
|
RW |
32 |
0x0000 0000 |
0x1D4 |
0x2010 D1D4 |
|
RW |
32 |
0x0000 0000 |
0x1D8 |
0x2010 D1D8 |
|
RW |
32 |
0x0000 0000 |
0x1DC |
0x2010 D1DC |
|
RW |
32 |
0x0080 0000 |
0x1E0 |
0x2010 D1E0 |
|
RW |
32 |
0x0000 0000 |
0x1E4 |
0x2010 D1E4 |
|
RW |
32 |
0x0000 0000 |
0x1E8 |
0x2010 D1E8 |
|
RW |
32 |
0x0000 0000 |
0x1EC |
0x2010 D1EC |
|
RW |
32 |
0x0080 0000 |
0x1F0 |
0x2010 D1F0 |
|
RW |
32 |
0x0000 0000 |
0x1F4 |
0x2010 D1F4 |
|
RW |
32 |
0x0000 0000 |
0x1F8 |
0x2010 D1F8 |
|
RW |
32 |
0x0000 0000 |
0x1FC |
0x2010 D1FC |
|
RW |
32 |
0x0080 0000 |
0x200 |
0x2010 D200 |
|
RW |
32 |
0x0000 0000 |
0x204 |
0x2010 D204 |
|
RW |
32 |
0x0000 0000 |
0x208 |
0x2010 D208 |
|
RW |
32 |
0x0000 0000 |
0x20C |
0x2010 D20C |
|
RW |
32 |
0x0080 0000 |
0x210 |
0x2010 D210 |
|
RW |
32 |
0x0000 0000 |
0x214 |
0x2010 D214 |
|
RW |
32 |
0x0000 0000 |
0x218 |
0x2010 D218 |
|
RW |
32 |
0x0000 0000 |
0x21C |
0x2010 D21C |
|
RW |
32 |
0x0080 0000 |
0x220 |
0x2010 D220 |
|
RW |
32 |
0x0000 0000 |
0x224 |
0x2010 D224 |
|
RW |
32 |
0x0000 0000 |
0x228 |
0x2010 D228 |
|
RW |
32 |
0x0000 0000 |
0x22C |
0x2010 D22C |
|
RW |
32 |
0x0000 0000 |
0x230 |
0x2010 D230 |
|
RW |
32 |
0x0000 0000 |
0x234 |
0x2010 D234 |
|
RW |
32 |
0x0000 0000 |
0x238 |
0x2010 D238 |
|
RW |
32 |
0x0000 0000 |
0x23C |
0x2010 D23C |
|
RW |
32 |
0x0080 0000 |
0x240 |
0x2010 D240 |
|
RW |
32 |
0x0000 0000 |
0x244 |
0x2010 D244 |
|
RW |
32 |
0x0000 0000 |
0x248 |
0x2010 D248 |
|
RW |
32 |
0x0000 0000 |
0x24C |
0x2010 D24C |
|
RW |
32 |
0x0000 0000 |
0x250 |
0x2010 D250 |
|
RW |
32 |
0x0000 0000 |
0x254 |
0x2010 D254 |
|
RW |
32 |
0x0000 0000 |
0x258 |
0x2010 D258 |
|
RW |
32 |
0x0000 0000 |
0x25C |
0x2010 D25C |
|
RW |
32 |
0x0080 0000 |
0x260 |
0x2010 D260 |
|
RW |
32 |
0x0000 0000 |
0x264 |
0x2010 D264 |
|
RW |
32 |
0x0000 0000 |
0x268 |
0x2010 D268 |
|
RW |
32 |
0x0000 0000 |
0x26C |
0x2010 D26C |
|
RW |
32 |
0x0000 0000 |
0x270 |
0x2010 D270 |
|
RW |
32 |
0x0000 0000 |
0x274 |
0x2010 D274 |
|
RW |
32 |
0x0000 0000 |
0x278 |
0x2010 D278 |
|
RW |
32 |
0x0000 0000 |
0x27C |
0x2010 D27C |
|
RW |
32 |
0x0080 0000 |
0x280 |
0x2010 D280 |
|
RW |
32 |
0x0000 0000 |
0x284 |
0x2010 D284 |
|
RW |
32 |
0x0000 0000 |
0x288 |
0x2010 D288 |
|
RW |
32 |
0x0000 0000 |
0x28C |
0x2010 D28C |
|
RW |
32 |
0x0000 0000 |
0x290 |
0x2010 D290 |
|
RW |
32 |
0x0000 0000 |
0x294 |
0x2010 D294 |
|
RW |
32 |
0x0000 0000 |
0x298 |
0x2010 D298 |
|
RW |
32 |
0x0000 0000 |
0x29C |
0x2010 D29C |
|
RW |
32 |
0x0080 0000 |
0x2A0 |
0x2010 D2A0 |
|
RW |
32 |
0x0000 0000 |
0x2A4 |
0x2010 D2A4 |
|
RW |
32 |
0x0000 0000 |
0x2A8 |
0x2010 D2A8 |
|
RW |
32 |
0x0000 0000 |
0x2AC |
0x2010 D2AC |
|
RW |
32 |
0x0000 0000 |
0x2B0 |
0x2010 D2B0 |
|
RW |
32 |
0x0000 0000 |
0x2B4 |
0x2010 D2B4 |
|
RW |
32 |
0x0000 0000 |
0x2B8 |
0x2010 D2B8 |
|
RW |
32 |
0x0000 0000 |
0x2BC |
0x2010 D2BC |
|
RW |
32 |
0x0080 0000 |
0x2C0 |
0x2010 D2C0 |
|
RW |
32 |
0x0000 0000 |
0x2C4 |
0x2010 D2C4 |
|
RW |
32 |
0x0000 0000 |
0x2C8 |
0x2010 D2C8 |
|
RW |
32 |
0x0000 0000 |
0x2CC |
0x2010 D2CC |
|
RW |
32 |
0x0000 0000 |
0x2D0 |
0x2010 D2D0 |
|
RW |
32 |
0x0000 0000 |
0x2D4 |
0x2010 D2D4 |
|
RW |
32 |
0x0000 0000 |
0x2D8 |
0x2010 D2D8 |
|
RW |
32 |
0x0000 0000 |
0x2DC |
0x2010 D2DC |
|
RW |
32 |
0x0080 0000 |
0x2E0 |
0x2010 D2E0 |
|
RW |
32 |
0x0000 0000 |
0x2E4 |
0x2010 D2E4 |
|
RW |
32 |
0x0000 0000 |
0x2E8 |
0x2010 D2E8 |
|
RW |
32 |
0x0000 0000 |
0x2EC |
0x2010 D2EC |
|
RW |
32 |
0x0000 0000 |
0x2F0 |
0x2010 D2F0 |
|
RW |
32 |
0x0000 0000 |
0x2F4 |
0x2010 D2F4 |
|
RW |
32 |
0x0000 0000 |
0x2F8 |
0x2010 D2F8 |
|
RW |
32 |
0x0000 0000 |
0x2FC |
0x2010 D2FC |
|
RW |
32 |
0x0080 0000 |
0x300 |
0x2010 D300 |
|
RW |
32 |
0x0000 0000 |
0x304 |
0x2010 D304 |
|
RW |
32 |
0x0000 0000 |
0x308 |
0x2010 D308 |
|
RW |
32 |
0x0000 0000 |
0x30C |
0x2010 D30C |
|
RW |
32 |
0x0000 0000 |
0x310 |
0x2010 D310 |
|
RW |
32 |
0x0000 0000 |
0x314 |
0x2010 D314 |
|
RW |
32 |
0x0000 0000 |
0x318 |
0x2010 D318 |
|
RW |
32 |
0x0000 0000 |
0x31C |
0x2010 D31C |
|
RW |
32 |
0x0080 0000 |
0x320 |
0x2010 D320 |
|
RW |
32 |
0x0000 0000 |
0x324 |
0x2010 D324 |
|
RW |
32 |
0x0000 0000 |
0x328 |
0x2010 D328 |
|
RW |
32 |
0x0000 0000 |
0x32C |
0x2010 D32C |
|
RW |
32 |
0x0000 0000 |
0x330 |
0x2010 D330 |
|
RW |
32 |
0x0000 0000 |
0x334 |
0x2010 D334 |
|
RW |
32 |
0x0000 0000 |
0x338 |
0x2010 D338 |
|
RW |
32 |
0x0000 0000 |
0x33C |
0x2010 D33C |
|
RW |
32 |
0x0080 0000 |
0x340 |
0x2010 D340 |
|
RW |
32 |
0x0000 0000 |
0x344 |
0x2010 D344 |
|
RW |
32 |
0x0000 0000 |
0x348 |
0x2010 D348 |
|
RW |
32 |
0x0000 0000 |
0x34C |
0x2010 D34C |
|
RW |
32 |
0x0000 0000 |
0x350 |
0x2010 D350 |
|
RW |
32 |
0x0000 0000 |
0x354 |
0x2010 D354 |
|
RW |
32 |
0x0000 0000 |
0x358 |
0x2010 D358 |
|
RW |
32 |
0x0000 0000 |
0x35C |
0x2010 D35C |
|
RW |
32 |
0x0080 0000 |
0x360 |
0x2010 D360 |
|
RW |
32 |
0x0000 0000 |
0x364 |
0x2010 D364 |
|
RW |
32 |
0x0000 0000 |
0x368 |
0x2010 D368 |
|
RW |
32 |
0x0000 0000 |
0x36C |
0x2010 D36C |
|
RW |
32 |
0x0000 0000 |
0x370 |
0x2010 D370 |
|
RW |
32 |
0x0000 0000 |
0x374 |
0x2010 D374 |
|
RW |
32 |
0x0000 0000 |
0x378 |
0x2010 D378 |
|
RW |
32 |
0x0000 0000 |
0x37C |
0x2010 D37C |
|
RW |
32 |
0x0080 0000 |
0x380 |
0x2010 D380 |
|
RW |
32 |
0x0000 0000 |
0x384 |
0x2010 D384 |
|
RW |
32 |
0x0000 0000 |
0x388 |
0x2010 D388 |
|
RW |
32 |
0x0000 0000 |
0x38C |
0x2010 D38C |
|
RW |
32 |
0x0000 0000 |
0x390 |
0x2010 D390 |
|
RW |
32 |
0x0000 0000 |
0x394 |
0x2010 D394 |
|
RW |
32 |
0x0000 0000 |
0x398 |
0x2010 D398 |
|
RW |
32 |
0x0000 0000 |
0x39C |
0x2010 D39C |
|
RW |
32 |
0x0080 0000 |
0x3A0 |
0x2010 D3A0 |
|
RW |
32 |
0x0000 0000 |
0x3A4 |
0x2010 D3A4 |
|
RW |
32 |
0x0000 0000 |
0x3A8 |
0x2010 D3A8 |
|
RW |
32 |
0x0000 0000 |
0x3AC |
0x2010 D3AC |
|
RW |
32 |
0x0000 0000 |
0x3B0 |
0x2010 D3B0 |
|
RW |
32 |
0x0000 0000 |
0x3B4 |
0x2010 D3B4 |
|
RW |
32 |
0x0000 0000 |
0x3B8 |
0x2010 D3B8 |
|
RW |
32 |
0x0000 0000 |
0x3BC |
0x2010 D3BC |
|
RW |
32 |
0x0080 0000 |
0x3C0 |
0x2010 D3C0 |
|
RW |
32 |
0x0000 0000 |
0x3C4 |
0x2010 D3C4 |
|
RW |
32 |
0x0000 0000 |
0x3C8 |
0x2010 D3C8 |
|
RW |
32 |
0x0000 0000 |
0x3CC |
0x2010 D3CC |
|
RW |
32 |
0x0000 0000 |
0x3D0 |
0x2010 D3D0 |
|
RW |
32 |
0x0000 0000 |
0x3D4 |
0x2010 D3D4 |
|
RW |
32 |
0x0000 0000 |
0x3D8 |
0x2010 D3D8 |
|
RW |
32 |
0x0000 0000 |
0x3DC |
0x2010 D3DC |
|
RW |
32 |
0x0080 0000 |
0x3E0 |
0x2010 D3E0 |
|
RW |
32 |
0x0000 0000 |
0x3E4 |
0x2010 D3E4 |
|
RW |
32 |
0x0000 0000 |
0x3E8 |
0x2010 D3E8 |
|
RW |
32 |
0x0000 0000 |
0x3EC |
0x2010 D3EC |
|
RW |
32 |
0x0000 0000 |
0x3F0 |
0x2010 D3F0 |
|
RW |
32 |
0x0000 0000 |
0x3F4 |
0x2010 D3F4 |
|
RW |
32 |
0x0000 0000 |
0x3F8 |
0x2010 D3F8 |
|
RW |
32 |
0x0000 0000 |
0x3FC |
0x2010 D3FC |
|
RW |
32 |
0x0080 0000 |
0x400 |
0x2010 D400 |
|
RW |
32 |
0x0000 0000 |
0x404 |
0x2010 D404 |
|
RW |
32 |
0x0000 0000 |
0x408 |
0x2010 D408 |
|
RW |
32 |
0x0000 0000 |
0x40C |
0x2010 D40C |
|
RW |
32 |
0x0000 0000 |
0x410 |
0x2010 D410 |
|
RW |
32 |
0x0000 0000 |
0x414 |
0x2010 D414 |
|
RW |
32 |
0x0000 0000 |
0x418 |
0x2010 D418 |
|
RW |
32 |
0x0000 0000 |
0x41C |
0x2010 D41C |
|
RW |
32 |
0x0080 0000 |
0x420 |
0x2010 D420 |
|
RW |
32 |
0x0000 0000 |
0x424 |
0x2010 D424 |
|
RW |
32 |
0x0000 0000 |
0x428 |
0x2010 D428 |
|
RW |
32 |
0x0000 0000 |
0x42C |
0x2010 D42C |
|
RW |
32 |
0x0000 0000 |
0x430 |
0x2010 D430 |
|
RW |
32 |
0x0000 0000 |
0x434 |
0x2010 D434 |
|
RW |
32 |
0x0000 0000 |
0x438 |
0x2010 D438 |
|
RW |
32 |
0x0000 0000 |
0x43C |
0x2010 D43C |
|
RW |
32 |
0x0080 0000 |
0x440 |
0x2010 D440 |
|
RW |
32 |
0x0000 0000 |
0x444 |
0x2010 D444 |
|
RW |
32 |
0x0000 0000 |
0x448 |
0x2010 D448 |
|
RW |
32 |
0x0000 0000 |
0x44C |
0x2010 D44C |
|
RW |
32 |
0x0000 0000 |
0x450 |
0x2010 D450 |
|
RW |
32 |
0x0000 0000 |
0x454 |
0x2010 D454 |
|
RW |
32 |
0x0000 0000 |
0x458 |
0x2010 D458 |
|
RW |
32 |
0x0000 0000 |
0x45C |
0x2010 D45C |
|
RW |
32 |
0x0080 0000 |
0x460 |
0x2010 D460 |
|
RW |
32 |
0x0000 0000 |
0x464 |
0x2010 D464 |
|
RW |
32 |
0x0000 0000 |
0x468 |
0x2010 D468 |
|
RW |
32 |
0x0000 0000 |
0x46C |
0x2010 D46C |
|
RW |
32 |
0x0000 0000 |
0x470 |
0x2010 D470 |
|
RW |
32 |
0x0000 0000 |
0x474 |
0x2010 D474 |
|
RW |
32 |
0x0000 0000 |
0x478 |
0x2010 D478 |
|
RW |
32 |
0x0000 0000 |
0x47C |
0x2010 D47C |
|
RW |
32 |
0x0080 0000 |
0x480 |
0x2010 D480 |
|
RW |
32 |
0x0000 0000 |
0x484 |
0x2010 D484 |
|
RW |
32 |
0x0000 0000 |
0x488 |
0x2010 D488 |
|
RW |
32 |
0x0000 0000 |
0x48C |
0x2010 D48C |
|
RW |
32 |
0x0000 0000 |
0x490 |
0x2010 D490 |
|
RW |
32 |
0x0000 0000 |
0x494 |
0x2010 D494 |
|
RW |
32 |
0x0000 0000 |
0x498 |
0x2010 D498 |
|
RW |
32 |
0x0000 0000 |
0x49C |
0x2010 D49C |
|
RW |
32 |
0x0080 0000 |
0x4A0 |
0x2010 D4A0 |
|
RW |
32 |
0x0000 0000 |
0x4A4 |
0x2010 D4A4 |
|
RW |
32 |
0x0000 0000 |
0x4A8 |
0x2010 D4A8 |
|
RW |
32 |
0x0000 0000 |
0x4AC |
0x2010 D4AC |
|
RW |
32 |
0x0000 0000 |
0x4B0 |
0x2010 D4B0 |
|
RW |
32 |
0x0000 0000 |
0x4B4 |
0x2010 D4B4 |
|
RW |
32 |
0x0000 0000 |
0x4B8 |
0x2010 D4B8 |
|
RW |
32 |
0x0000 0000 |
0x4BC |
0x2010 D4BC |
|
RW |
32 |
0x0080 0000 |
0x4C0 |
0x2010 D4C0 |
|
RW |
32 |
0x0000 0000 |
0x4C4 |
0x2010 D4C4 |
|
RW |
32 |
0x0000 0000 |
0x4C8 |
0x2010 D4C8 |
|
RW |
32 |
0x0000 0000 |
0x4CC |
0x2010 D4CC |
|
RW |
32 |
0x0000 0000 |
0x4D0 |
0x2010 D4D0 |
|
RW |
32 |
0x0000 0000 |
0x4D4 |
0x2010 D4D4 |
|
RW |
32 |
0x0000 0000 |
0x4D8 |
0x2010 D4D8 |
|
RW |
32 |
0x0000 0000 |
0x4DC |
0x2010 D4DC |
|
RW |
32 |
0x0080 0000 |
0x4E0 |
0x2010 D4E0 |
|
RW |
32 |
0x0000 0000 |
0x4E4 |
0x2010 D4E4 |
|
RW |
32 |
0x0000 0000 |
0x4E8 |
0x2010 D4E8 |
|
RW |
32 |
0x0000 0000 |
0x4EC |
0x2010 D4EC |
|
RW |
32 |
0x0000 0000 |
0x4F0 |
0x2010 D4F0 |
|
RW |
32 |
0x0000 0000 |
0x4F4 |
0x2010 D4F4 |
|
RW |
32 |
0x0000 0000 |
0x4F8 |
0x2010 D4F8 |
|
RW |
32 |
0x0000 0000 |
0x4FC |
0x2010 D4FC |
|
RW |
32 |
0x0080 0000 |
0x500 |
0x2010 D500 |
|
RW |
32 |
0x0000 0000 |
0x504 |
0x2010 D504 |
|
RW |
32 |
0x0000 0000 |
0x508 |
0x2010 D508 |
|
RW |
32 |
0x0000 0000 |
0x50C |
0x2010 D50C |
|
RW |
32 |
0x0000 0000 |
0x510 |
0x2010 D510 |
|
RW |
32 |
0x0000 0000 |
0x514 |
0x2010 D514 |
|
RW |
32 |
0x0000 0000 |
0x518 |
0x2010 D518 |
|
RW |
32 |
0x0000 0000 |
0x51C |
0x2010 D51C |
|
RW |
32 |
0x0080 0000 |
0x520 |
0x2010 D520 |
|
RW |
32 |
0x0000 0000 |
0x524 |
0x2010 D524 |
|
RW |
32 |
0x0000 0000 |
0x528 |
0x2010 D528 |
|
RW |
32 |
0x0000 0000 |
0x52C |
0x2010 D52C |
|
RW |
32 |
0x0000 0000 |
0x530 |
0x2010 D530 |
|
RW |
32 |
0x0000 0000 |
0x534 |
0x2010 D534 |
|
RW |
32 |
0x0000 0000 |
0x538 |
0x2010 D538 |
|
RW |
32 |
0x0000 0000 |
0x53C |
0x2010 D53C |
|
RW |
32 |
0x0080 0000 |
0x540 |
0x2010 D540 |
|
RW |
32 |
0x0000 0000 |
0x544 |
0x2010 D544 |
|
RW |
32 |
0x0000 0000 |
0x548 |
0x2010 D548 |
|
RW |
32 |
0x0000 0000 |
0x54C |
0x2010 D54C |
|
RW |
32 |
0x0000 0000 |
0x550 |
0x2010 D550 |
|
RW |
32 |
0x0000 0000 |
0x554 |
0x2010 D554 |
|
RW |
32 |
0x0000 0000 |
0x558 |
0x2010 D558 |
|
RW |
32 |
0x0000 0000 |
0x55C |
0x2010 D55C |
|
RW |
32 |
0x0080 0000 |
0x560 |
0x2010 D560 |
|
RW |
32 |
0x0000 0000 |
0x564 |
0x2010 D564 |
|
RW |
32 |
0x0000 0000 |
0x568 |
0x2010 D568 |
|
RW |
32 |
0x0000 0000 |
0x56C |
0x2010 D56C |
|
RW |
32 |
0x0000 0000 |
0x570 |
0x2010 D570 |
|
RW |
32 |
0x0000 0000 |
0x574 |
0x2010 D574 |
|
RW |
32 |
0x0000 0000 |
0x578 |
0x2010 D578 |
|
RW |
32 |
0x0000 0000 |
0x57C |
0x2010 D57C |
|
RW |
32 |
0x0080 0000 |
0x580 |
0x2010 D580 |
|
RW |
32 |
0x0000 0000 |
0x584 |
0x2010 D584 |
|
RW |
32 |
0x0000 0000 |
0x588 |
0x2010 D588 |
|
RW |
32 |
0x0000 0000 |
0x58C |
0x2010 D58C |
|
RW |
32 |
0x0000 0000 |
0x590 |
0x2010 D590 |
|
RW |
32 |
0x0000 0000 |
0x594 |
0x2010 D594 |
|
RW |
32 |
0x0000 0000 |
0x598 |
0x2010 D598 |
|
RW |
32 |
0x0000 0000 |
0x59C |
0x2010 D59C |
|
RW |
32 |
0x0080 0000 |
0x5A0 |
0x2010 D5A0 |
|
RW |
32 |
0x0000 0000 |
0x5A4 |
0x2010 D5A4 |
|
RW |
32 |
0x0000 0000 |
0x5A8 |
0x2010 D5A8 |
|
RW |
32 |
0x0000 0000 |
0x5AC |
0x2010 D5AC |
|
RW |
32 |
0x0000 0000 |
0x5B0 |
0x2010 D5B0 |
|
RW |
32 |
0x0000 0000 |
0x5B4 |
0x2010 D5B4 |
|
RW |
32 |
0x0000 0000 |
0x5B8 |
0x2010 D5B8 |
|
RW |
32 |
0x0000 0000 |
0x5BC |
0x2010 D5BC |
|
RW |
32 |
0x0080 0000 |
0x5C0 |
0x2010 D5C0 |
|
RW |
32 |
0x0000 0000 |
0x5C4 |
0x2010 D5C4 |
|
RW |
32 |
0x0000 0000 |
0x5C8 |
0x2010 D5C8 |
|
RW |
32 |
0x0000 0000 |
0x5CC |
0x2010 D5CC |
|
RW |
32 |
0x0000 0000 |
0x5D0 |
0x2010 D5D0 |
|
RW |
32 |
0x0000 0000 |
0x5D4 |
0x2010 D5D4 |
|
RW |
32 |
0x0000 0000 |
0x5D8 |
0x2010 D5D8 |
|
RW |
32 |
0x0000 0000 |
0x5DC |
0x2010 D5DC |
|
RW |
32 |
0x0080 0000 |
0x5E0 |
0x2010 D5E0 |
|
RW |
32 |
0x0000 0000 |
0x5E4 |
0x2010 D5E4 |
|
RW |
32 |
0x0000 0000 |
0x5E8 |
0x2010 D5E8 |
|
RW |
32 |
0x0000 0000 |
0x5EC |
0x2010 D5EC |
|
RW |
32 |
0x0000 0000 |
0x5F0 |
0x2010 D5F0 |
|
RW |
32 |
0x0000 0000 |
0x5F4 |
0x2010 D5F4 |
|
RW |
32 |
0x0000 0000 |
0x5F8 |
0x2010 D5F8 |
|
RW |
32 |
0x0000 0000 |
0x5FC |
0x2010 D5FC |
|
RW |
32 |
0x0080 0000 |
0x600 |
0x2010 D600 |
|
RW |
32 |
0x0000 0000 |
0x604 |
0x2010 D604 |
|
RW |
32 |
0x0000 0000 |
0x608 |
0x2010 D608 |
|
RW |
32 |
0x0000 0000 |
0x60C |
0x2010 D60C |
|
RW |
32 |
0x0000 0000 |
0x610 |
0x2010 D610 |
|
RW |
32 |
0x0000 0000 |
0x614 |
0x2010 D614 |
|
RW |
32 |
0x0000 0000 |
0x618 |
0x2010 D618 |
|
RW |
32 |
0x0000 0000 |
0x61C |
0x2010 D61C |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x2810 C000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x2810 C004 |
|
RO |
32 |
0x0000 0000 |
0x008 |
0x2810 C008 |
|
RO |
32 |
0x0000 0000 |
0x00C |
0x2810 C00C |
|
RO |
32 |
0x0000 0000 |
0x010 |
0x2810 C010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x2810 C014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x2810 C018 |
|
RW |
32 |
0x0000 0000 |
0x01C |
0x2810 C01C |
|
RW |
32 |
0x0080 0000 |
0x020 |
0x2810 C020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x2810 C024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x2810 C028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
0x2810 C02C |
|
RW |
32 |
0x0080 0000 |
0x030 |
0x2810 C030 |
|
RW |
32 |
0x0000 0000 |
0x034 |
0x2810 C034 |
|
RW |
32 |
0x0000 0000 |
0x038 |
0x2810 C038 |
|
RW |
32 |
0x0000 0000 |
0x03C |
0x2810 C03C |
|
RW |
32 |
0x0080 0000 |
0x040 |
0x2810 C040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
0x2810 C044 |
|
RW |
32 |
0x0000 0000 |
0x048 |
0x2810 C048 |
|
RW |
32 |
0x0000 0000 |
0x04C |
0x2810 C04C |
|
RW |
32 |
0x0080 0000 |
0x050 |
0x2810 C050 |
|
RW |
32 |
0x0000 0000 |
0x054 |
0x2810 C054 |
|
RW |
32 |
0x0000 0000 |
0x058 |
0x2810 C058 |
|
RW |
32 |
0x0000 0000 |
0x05C |
0x2810 C05C |
|
RW |
32 |
0x0080 0000 |
0x060 |
0x2810 C060 |
|
RW |
32 |
0x0000 0000 |
0x064 |
0x2810 C064 |
|
RW |
32 |
0x0000 0000 |
0x068 |
0x2810 C068 |
|
RW |
32 |
0x0000 0000 |
0x06C |
0x2810 C06C |
|
RW |
32 |
0x0080 0000 |
0x070 |
0x2810 C070 |
|
RW |
32 |
0x0000 0000 |
0x074 |
0x2810 C074 |
|
RW |
32 |
0x0000 0000 |
0x078 |
0x2810 C078 |
|
RW |
32 |
0x0000 0000 |
0x07C |
0x2810 C07C |
|
RW |
32 |
0x0080 0000 |
0x080 |
0x2810 C080 |
|
RW |
32 |
0x0000 0000 |
0x084 |
0x2810 C084 |
|
RW |
32 |
0x0000 0000 |
0x088 |
0x2810 C088 |
|
RW |
32 |
0x0000 0000 |
0x08C |
0x2810 C08C |
|
RW |
32 |
0x0080 0000 |
0x090 |
0x2810 C090 |
|
RW |
32 |
0x0000 0000 |
0x094 |
0x2810 C094 |
|
RW |
32 |
0x0000 0000 |
0x098 |
0x2810 C098 |
|
RW |
32 |
0x0000 0000 |
0x09C |
0x2810 C09C |
|
RW |
32 |
0x0080 0000 |
0x0A0 |
0x2810 C0A0 |
|
RW |
32 |
0x0000 0000 |
0x0A4 |
0x2810 C0A4 |
|
RW |
32 |
0x0000 0000 |
0x0A8 |
0x2810 C0A8 |
|
RW |
32 |
0x0000 0000 |
0x0AC |
0x2810 C0AC |
|
RW |
32 |
0x0080 0000 |
0x0B0 |
0x2810 C0B0 |
|
RW |
32 |
0x0000 0000 |
0x0B4 |
0x2810 C0B4 |
|
RW |
32 |
0x0000 0000 |
0x0B8 |
0x2810 C0B8 |
|
RW |
32 |
0x0000 0000 |
0x0BC |
0x2810 C0BC |
|
RW |
32 |
0x0080 0000 |
0x0C0 |
0x2810 C0C0 |
|
RW |
32 |
0x0000 0000 |
0x0C4 |
0x2810 C0C4 |
|
RW |
32 |
0x0000 0000 |
0x0C8 |
0x2810 C0C8 |
|
RW |
32 |
0x0000 0000 |
0x0CC |
0x2810 C0CC |
|
RW |
32 |
0x0080 0000 |
0x0D0 |
0x2810 C0D0 |
|
RW |
32 |
0x0000 0000 |
0x0D4 |
0x2810 C0D4 |
|
RW |
32 |
0x0000 0000 |
0x0D8 |
0x2810 C0D8 |
|
RW |
32 |
0x0000 0000 |
0x0DC |
0x2810 C0DC |
|
RW |
32 |
0x0080 0000 |
0x0E0 |
0x2810 C0E0 |
|
RW |
32 |
0x0000 0000 |
0x0E4 |
0x2810 C0E4 |
|
RW |
32 |
0x0000 0000 |
0x0E8 |
0x2810 C0E8 |
|
RW |
32 |
0x0000 0000 |
0x0EC |
0x2810 C0EC |
|
RW |
32 |
0x0080 0000 |
0x0F0 |
0x2810 C0F0 |
|
RW |
32 |
0x0000 0000 |
0x0F4 |
0x2810 C0F4 |
|
RW |
32 |
0x0000 0000 |
0x0F8 |
0x2810 C0F8 |
|
RW |
32 |
0x0000 0000 |
0x0FC |
0x2810 C0FC |
|
RW |
32 |
0x0080 0000 |
0x100 |
0x2810 C100 |
|
RW |
32 |
0x0000 0000 |
0x104 |
0x2810 C104 |
|
RW |
32 |
0x0000 0000 |
0x108 |
0x2810 C108 |
|
RW |
32 |
0x0000 0000 |
0x10C |
0x2810 C10C |
|
RW |
32 |
0x0080 0000 |
0x110 |
0x2810 C110 |
|
RW |
32 |
0x0000 0000 |
0x114 |
0x2810 C114 |
|
RW |
32 |
0x0000 0000 |
0x118 |
0x2810 C118 |
|
RW |
32 |
0x0000 0000 |
0x11C |
0x2810 C11C |
|
RW |
32 |
0x0080 0000 |
0x120 |
0x2810 C120 |
|
RW |
32 |
0x0000 0000 |
0x124 |
0x2810 C124 |
|
RW |
32 |
0x0000 0000 |
0x128 |
0x2810 C128 |
|
RW |
32 |
0x0000 0000 |
0x12C |
0x2810 C12C |
|
RW |
32 |
0x0080 0000 |
0x130 |
0x2810 C130 |
|
RW |
32 |
0x0000 0000 |
0x134 |
0x2810 C134 |
|
RW |
32 |
0x0000 0000 |
0x138 |
0x2810 C138 |
|
RW |
32 |
0x0000 0000 |
0x13C |
0x2810 C13C |
|
RW |
32 |
0x0080 0000 |
0x140 |
0x2810 C140 |
|
RW |
32 |
0x0000 0000 |
0x144 |
0x2810 C144 |
|
RW |
32 |
0x0000 0000 |
0x148 |
0x2810 C148 |
|
RW |
32 |
0x0000 0000 |
0x14C |
0x2810 C14C |
|
RW |
32 |
0x0080 0000 |
0x150 |
0x2810 C150 |
|
RW |
32 |
0x0000 0000 |
0x154 |
0x2810 C154 |
|
RW |
32 |
0x0000 0000 |
0x158 |
0x2810 C158 |
|
RW |
32 |
0x0000 0000 |
0x15C |
0x2810 C15C |
|
RW |
32 |
0x0080 0000 |
0x160 |
0x2810 C160 |
|
RW |
32 |
0x0000 0000 |
0x164 |
0x2810 C164 |
|
RW |
32 |
0x0000 0000 |
0x168 |
0x2810 C168 |
|
RW |
32 |
0x0000 0000 |
0x16C |
0x2810 C16C |
|
RW |
32 |
0x0080 0000 |
0x170 |
0x2810 C170 |
|
RW |
32 |
0x0000 0000 |
0x174 |
0x2810 C174 |
|
RW |
32 |
0x0000 0000 |
0x178 |
0x2810 C178 |
|
RW |
32 |
0x0000 0000 |
0x17C |
0x2810 C17C |
|
RW |
32 |
0x0080 0000 |
0x180 |
0x2810 C180 |
|
RW |
32 |
0x0000 0000 |
0x184 |
0x2810 C184 |
|
RW |
32 |
0x0000 0000 |
0x188 |
0x2810 C188 |
|
RW |
32 |
0x0000 0000 |
0x18C |
0x2810 C18C |
|
RW |
32 |
0x0080 0000 |
0x190 |
0x2810 C190 |
|
RW |
32 |
0x0000 0000 |
0x194 |
0x2810 C194 |
|
RW |
32 |
0x0000 0000 |
0x198 |
0x2810 C198 |
|
RW |
32 |
0x0000 0000 |
0x19C |
0x2810 C19C |
|
RW |
32 |
0x0080 0000 |
0x1A0 |
0x2810 C1A0 |
|
RW |
32 |
0x0000 0000 |
0x1A4 |
0x2810 C1A4 |
|
RW |
32 |
0x0000 0000 |
0x1A8 |
0x2810 C1A8 |
|
RW |
32 |
0x0000 0000 |
0x1AC |
0x2810 C1AC |
|
RW |
32 |
0x0080 0000 |
0x1B0 |
0x2810 C1B0 |
|
RW |
32 |
0x0000 0000 |
0x1B4 |
0x2810 C1B4 |
|
RW |
32 |
0x0000 0000 |
0x1B8 |
0x2810 C1B8 |
|
RW |
32 |
0x0000 0000 |
0x1BC |
0x2810 C1BC |
|
RW |
32 |
0x0080 0000 |
0x1C0 |
0x2810 C1C0 |
|
RW |
32 |
0x0000 0000 |
0x1C4 |
0x2810 C1C4 |
|
RW |
32 |
0x0000 0000 |
0x1C8 |
0x2810 C1C8 |
|
RW |
32 |
0x0000 0000 |
0x1CC |
0x2810 C1CC |
|
RW |
32 |
0x0080 0000 |
0x1D0 |
0x2810 C1D0 |
|
RW |
32 |
0x0000 0000 |
0x1D4 |
0x2810 C1D4 |
|
RW |
32 |
0x0000 0000 |
0x1D8 |
0x2810 C1D8 |
|
RW |
32 |
0x0000 0000 |
0x1DC |
0x2810 C1DC |
|
RW |
32 |
0x0080 0000 |
0x1E0 |
0x2810 C1E0 |
|
RW |
32 |
0x0000 0000 |
0x1E4 |
0x2810 C1E4 |
|
RW |
32 |
0x0000 0000 |
0x1E8 |
0x2810 C1E8 |
|
RW |
32 |
0x0000 0000 |
0x1EC |
0x2810 C1EC |
|
RW |
32 |
0x0080 0000 |
0x1F0 |
0x2810 C1F0 |
|
RW |
32 |
0x0000 0000 |
0x1F4 |
0x2810 C1F4 |
|
RW |
32 |
0x0000 0000 |
0x1F8 |
0x2810 C1F8 |
|
RW |
32 |
0x0000 0000 |
0x1FC |
0x2810 C1FC |
|
RW |
32 |
0x0080 0000 |
0x200 |
0x2810 C200 |
|
RW |
32 |
0x0000 0000 |
0x204 |
0x2810 C204 |
|
RW |
32 |
0x0000 0000 |
0x208 |
0x2810 C208 |
|
RW |
32 |
0x0000 0000 |
0x20C |
0x2810 C20C |
|
RW |
32 |
0x0080 0000 |
0x210 |
0x2810 C210 |
|
RW |
32 |
0x0000 0000 |
0x214 |
0x2810 C214 |
|
RW |
32 |
0x0000 0000 |
0x218 |
0x2810 C218 |
|
RW |
32 |
0x0000 0000 |
0x21C |
0x2810 C21C |
|
RW |
32 |
0x0080 0000 |
0x220 |
0x2810 C220 |
|
RW |
32 |
0x0000 0000 |
0x224 |
0x2810 C224 |
|
RW |
32 |
0x0000 0000 |
0x228 |
0x2810 C228 |
|
RW |
32 |
0x0000 0000 |
0x22C |
0x2810 C22C |
|
RW |
32 |
0x0000 0000 |
0x230 |
0x2810 C230 |
|
RW |
32 |
0x0000 0000 |
0x234 |
0x2810 C234 |
|
RW |
32 |
0x0000 0000 |
0x238 |
0x2810 C238 |
|
RW |
32 |
0x0000 0000 |
0x23C |
0x2810 C23C |
|
RW |
32 |
0x0080 0000 |
0x240 |
0x2810 C240 |
|
RW |
32 |
0x0000 0000 |
0x244 |
0x2810 C244 |
|
RW |
32 |
0x0000 0000 |
0x248 |
0x2810 C248 |
|
RW |
32 |
0x0000 0000 |
0x24C |
0x2810 C24C |
|
RW |
32 |
0x0000 0000 |
0x250 |
0x2810 C250 |
|
RW |
32 |
0x0000 0000 |
0x254 |
0x2810 C254 |
|
RW |
32 |
0x0000 0000 |
0x258 |
0x2810 C258 |
|
RW |
32 |
0x0000 0000 |
0x25C |
0x2810 C25C |
|
RW |
32 |
0x0080 0000 |
0x260 |
0x2810 C260 |
|
RW |
32 |
0x0000 0000 |
0x264 |
0x2810 C264 |
|
RW |
32 |
0x0000 0000 |
0x268 |
0x2810 C268 |
|
RW |
32 |
0x0000 0000 |
0x26C |
0x2810 C26C |
|
RW |
32 |
0x0000 0000 |
0x270 |
0x2810 C270 |
|
RW |
32 |
0x0000 0000 |
0x274 |
0x2810 C274 |
|
RW |
32 |
0x0000 0000 |
0x278 |
0x2810 C278 |
|
RW |
32 |
0x0000 0000 |
0x27C |
0x2810 C27C |
|
RW |
32 |
0x0080 0000 |
0x280 |
0x2810 C280 |
|
RW |
32 |
0x0000 0000 |
0x284 |
0x2810 C284 |
|
RW |
32 |
0x0000 0000 |
0x288 |
0x2810 C288 |
|
RW |
32 |
0x0000 0000 |
0x28C |
0x2810 C28C |
|
RW |
32 |
0x0000 0000 |
0x290 |
0x2810 C290 |
|
RW |
32 |
0x0000 0000 |
0x294 |
0x2810 C294 |
|
RW |
32 |
0x0000 0000 |
0x298 |
0x2810 C298 |
|
RW |
32 |
0x0000 0000 |
0x29C |
0x2810 C29C |
|
RW |
32 |
0x0080 0000 |
0x2A0 |
0x2810 C2A0 |
|
RW |
32 |
0x0000 0000 |
0x2A4 |
0x2810 C2A4 |
|
RW |
32 |
0x0000 0000 |
0x2A8 |
0x2810 C2A8 |
|
RW |
32 |
0x0000 0000 |
0x2AC |
0x2810 C2AC |
|
RW |
32 |
0x0000 0000 |
0x2B0 |
0x2810 C2B0 |
|
RW |
32 |
0x0000 0000 |
0x2B4 |
0x2810 C2B4 |
|
RW |
32 |
0x0000 0000 |
0x2B8 |
0x2810 C2B8 |
|
RW |
32 |
0x0000 0000 |
0x2BC |
0x2810 C2BC |
|
RW |
32 |
0x0080 0000 |
0x2C0 |
0x2810 C2C0 |
|
RW |
32 |
0x0000 0000 |
0x2C4 |
0x2810 C2C4 |
|
RW |
32 |
0x0000 0000 |
0x2C8 |
0x2810 C2C8 |
|
RW |
32 |
0x0000 0000 |
0x2CC |
0x2810 C2CC |
|
RW |
32 |
0x0000 0000 |
0x2D0 |
0x2810 C2D0 |
|
RW |
32 |
0x0000 0000 |
0x2D4 |
0x2810 C2D4 |
|
RW |
32 |
0x0000 0000 |
0x2D8 |
0x2810 C2D8 |
|
RW |
32 |
0x0000 0000 |
0x2DC |
0x2810 C2DC |
|
RW |
32 |
0x0080 0000 |
0x2E0 |
0x2810 C2E0 |
|
RW |
32 |
0x0000 0000 |
0x2E4 |
0x2810 C2E4 |
|
RW |
32 |
0x0000 0000 |
0x2E8 |
0x2810 C2E8 |
|
RW |
32 |
0x0000 0000 |
0x2EC |
0x2810 C2EC |
|
RW |
32 |
0x0000 0000 |
0x2F0 |
0x2810 C2F0 |
|
RW |
32 |
0x0000 0000 |
0x2F4 |
0x2810 C2F4 |
|
RW |
32 |
0x0000 0000 |
0x2F8 |
0x2810 C2F8 |
|
RW |
32 |
0x0000 0000 |
0x2FC |
0x2810 C2FC |
|
RW |
32 |
0x0080 0000 |
0x300 |
0x2810 C300 |
|
RW |
32 |
0x0000 0000 |
0x304 |
0x2810 C304 |
|
RW |
32 |
0x0000 0000 |
0x308 |
0x2810 C308 |
|
RW |
32 |
0x0000 0000 |
0x30C |
0x2810 C30C |
|
RW |
32 |
0x0000 0000 |
0x310 |
0x2810 C310 |
|
RW |
32 |
0x0000 0000 |
0x314 |
0x2810 C314 |
|
RW |
32 |
0x0000 0000 |
0x318 |
0x2810 C318 |
|
RW |
32 |
0x0000 0000 |
0x31C |
0x2810 C31C |
|
RW |
32 |
0x0080 0000 |
0x320 |
0x2810 C320 |
|
RW |
32 |
0x0000 0000 |
0x324 |
0x2810 C324 |
|
RW |
32 |
0x0000 0000 |
0x328 |
0x2810 C328 |
|
RW |
32 |
0x0000 0000 |
0x32C |
0x2810 C32C |
|
RW |
32 |
0x0000 0000 |
0x330 |
0x2810 C330 |
|
RW |
32 |
0x0000 0000 |
0x334 |
0x2810 C334 |
|
RW |
32 |
0x0000 0000 |
0x338 |
0x2810 C338 |
|
RW |
32 |
0x0000 0000 |
0x33C |
0x2810 C33C |
|
RW |
32 |
0x0080 0000 |
0x340 |
0x2810 C340 |
|
RW |
32 |
0x0000 0000 |
0x344 |
0x2810 C344 |
|
RW |
32 |
0x0000 0000 |
0x348 |
0x2810 C348 |
|
RW |
32 |
0x0000 0000 |
0x34C |
0x2810 C34C |
|
RW |
32 |
0x0000 0000 |
0x350 |
0x2810 C350 |
|
RW |
32 |
0x0000 0000 |
0x354 |
0x2810 C354 |
|
RW |
32 |
0x0000 0000 |
0x358 |
0x2810 C358 |
|
RW |
32 |
0x0000 0000 |
0x35C |
0x2810 C35C |
|
RW |
32 |
0x0080 0000 |
0x360 |
0x2810 C360 |
|
RW |
32 |
0x0000 0000 |
0x364 |
0x2810 C364 |
|
RW |
32 |
0x0000 0000 |
0x368 |
0x2810 C368 |
|
RW |
32 |
0x0000 0000 |
0x36C |
0x2810 C36C |
|
RW |
32 |
0x0000 0000 |
0x370 |
0x2810 C370 |
|
RW |
32 |
0x0000 0000 |
0x374 |
0x2810 C374 |
|
RW |
32 |
0x0000 0000 |
0x378 |
0x2810 C378 |
|
RW |
32 |
0x0000 0000 |
0x37C |
0x2810 C37C |
|
RW |
32 |
0x0080 0000 |
0x380 |
0x2810 C380 |
|
RW |
32 |
0x0000 0000 |
0x384 |
0x2810 C384 |
|
RW |
32 |
0x0000 0000 |
0x388 |
0x2810 C388 |
|
RW |
32 |
0x0000 0000 |
0x38C |
0x2810 C38C |
|
RW |
32 |
0x0000 0000 |
0x390 |
0x2810 C390 |
|
RW |
32 |
0x0000 0000 |
0x394 |
0x2810 C394 |
|
RW |
32 |
0x0000 0000 |
0x398 |
0x2810 C398 |
|
RW |
32 |
0x0000 0000 |
0x39C |
0x2810 C39C |
|
RW |
32 |
0x0080 0000 |
0x3A0 |
0x2810 C3A0 |
|
RW |
32 |
0x0000 0000 |
0x3A4 |
0x2810 C3A4 |
|
RW |
32 |
0x0000 0000 |
0x3A8 |
0x2810 C3A8 |
|
RW |
32 |
0x0000 0000 |
0x3AC |
0x2810 C3AC |
|
RW |
32 |
0x0000 0000 |
0x3B0 |
0x2810 C3B0 |
|
RW |
32 |
0x0000 0000 |
0x3B4 |
0x2810 C3B4 |
|
RW |
32 |
0x0000 0000 |
0x3B8 |
0x2810 C3B8 |
|
RW |
32 |
0x0000 0000 |
0x3BC |
0x2810 C3BC |
|
RW |
32 |
0x0080 0000 |
0x3C0 |
0x2810 C3C0 |
|
RW |
32 |
0x0000 0000 |
0x3C4 |
0x2810 C3C4 |
|
RW |
32 |
0x0000 0000 |
0x3C8 |
0x2810 C3C8 |
|
RW |
32 |
0x0000 0000 |
0x3CC |
0x2810 C3CC |
|
RW |
32 |
0x0000 0000 |
0x3D0 |
0x2810 C3D0 |
|
RW |
32 |
0x0000 0000 |
0x3D4 |
0x2810 C3D4 |
|
RW |
32 |
0x0000 0000 |
0x3D8 |
0x2810 C3D8 |
|
RW |
32 |
0x0000 0000 |
0x3DC |
0x2810 C3DC |
|
RW |
32 |
0x0080 0000 |
0x3E0 |
0x2810 C3E0 |
|
RW |
32 |
0x0000 0000 |
0x3E4 |
0x2810 C3E4 |
|
RW |
32 |
0x0000 0000 |
0x3E8 |
0x2810 C3E8 |
|
RW |
32 |
0x0000 0000 |
0x3EC |
0x2810 C3EC |
|
RW |
32 |
0x0000 0000 |
0x3F0 |
0x2810 C3F0 |
|
RW |
32 |
0x0000 0000 |
0x3F4 |
0x2810 C3F4 |
|
RW |
32 |
0x0000 0000 |
0x3F8 |
0x2810 C3F8 |
|
RW |
32 |
0x0000 0000 |
0x3FC |
0x2810 C3FC |
|
RW |
32 |
0x0080 0000 |
0x400 |
0x2810 C400 |
|
RW |
32 |
0x0000 0000 |
0x404 |
0x2810 C404 |
|
RW |
32 |
0x0000 0000 |
0x408 |
0x2810 C408 |
|
RW |
32 |
0x0000 0000 |
0x40C |
0x2810 C40C |
|
RW |
32 |
0x0000 0000 |
0x410 |
0x2810 C410 |
|
RW |
32 |
0x0000 0000 |
0x414 |
0x2810 C414 |
|
RW |
32 |
0x0000 0000 |
0x418 |
0x2810 C418 |
|
RW |
32 |
0x0000 0000 |
0x41C |
0x2810 C41C |
|
RW |
32 |
0x0080 0000 |
0x420 |
0x2810 C420 |
|
RW |
32 |
0x0000 0000 |
0x424 |
0x2810 C424 |
|
RW |
32 |
0x0000 0000 |
0x428 |
0x2810 C428 |
|
RW |
32 |
0x0000 0000 |
0x42C |
0x2810 C42C |
|
RW |
32 |
0x0000 0000 |
0x430 |
0x2810 C430 |
|
RW |
32 |
0x0000 0000 |
0x434 |
0x2810 C434 |
|
RW |
32 |
0x0000 0000 |
0x438 |
0x2810 C438 |
|
RW |
32 |
0x0000 0000 |
0x43C |
0x2810 C43C |
|
RW |
32 |
0x0080 0000 |
0x440 |
0x2810 C440 |
|
RW |
32 |
0x0000 0000 |
0x444 |
0x2810 C444 |
|
RW |
32 |
0x0000 0000 |
0x448 |
0x2810 C448 |
|
RW |
32 |
0x0000 0000 |
0x44C |
0x2810 C44C |
|
RW |
32 |
0x0000 0000 |
0x450 |
0x2810 C450 |
|
RW |
32 |
0x0000 0000 |
0x454 |
0x2810 C454 |
|
RW |
32 |
0x0000 0000 |
0x458 |
0x2810 C458 |
|
RW |
32 |
0x0000 0000 |
0x45C |
0x2810 C45C |
|
RW |
32 |
0x0080 0000 |
0x460 |
0x2810 C460 |
|
RW |
32 |
0x0000 0000 |
0x464 |
0x2810 C464 |
|
RW |
32 |
0x0000 0000 |
0x468 |
0x2810 C468 |
|
RW |
32 |
0x0000 0000 |
0x46C |
0x2810 C46C |
|
RW |
32 |
0x0000 0000 |
0x470 |
0x2810 C470 |
|
RW |
32 |
0x0000 0000 |
0x474 |
0x2810 C474 |
|
RW |
32 |
0x0000 0000 |
0x478 |
0x2810 C478 |
|
RW |
32 |
0x0000 0000 |
0x47C |
0x2810 C47C |
|
RW |
32 |
0x0080 0000 |
0x480 |
0x2810 C480 |
|
RW |
32 |
0x0000 0000 |
0x484 |
0x2810 C484 |
|
RW |
32 |
0x0000 0000 |
0x488 |
0x2810 C488 |
|
RW |
32 |
0x0000 0000 |
0x48C |
0x2810 C48C |
|
RW |
32 |
0x0000 0000 |
0x490 |
0x2810 C490 |
|
RW |
32 |
0x0000 0000 |
0x494 |
0x2810 C494 |
|
RW |
32 |
0x0000 0000 |
0x498 |
0x2810 C498 |
|
RW |
32 |
0x0000 0000 |
0x49C |
0x2810 C49C |
|
RW |
32 |
0x0080 0000 |
0x4A0 |
0x2810 C4A0 |
|
RW |
32 |
0x0000 0000 |
0x4A4 |
0x2810 C4A4 |
|
RW |
32 |
0x0000 0000 |
0x4A8 |
0x2810 C4A8 |
|
RW |
32 |
0x0000 0000 |
0x4AC |
0x2810 C4AC |
|
RW |
32 |
0x0000 0000 |
0x4B0 |
0x2810 C4B0 |
|
RW |
32 |
0x0000 0000 |
0x4B4 |
0x2810 C4B4 |
|
RW |
32 |
0x0000 0000 |
0x4B8 |
0x2810 C4B8 |
|
RW |
32 |
0x0000 0000 |
0x4BC |
0x2810 C4BC |
|
RW |
32 |
0x0080 0000 |
0x4C0 |
0x2810 C4C0 |
|
RW |
32 |
0x0000 0000 |
0x4C4 |
0x2810 C4C4 |
|
RW |
32 |
0x0000 0000 |
0x4C8 |
0x2810 C4C8 |
|
RW |
32 |
0x0000 0000 |
0x4CC |
0x2810 C4CC |
|
RW |
32 |
0x0000 0000 |
0x4D0 |
0x2810 C4D0 |
|
RW |
32 |
0x0000 0000 |
0x4D4 |
0x2810 C4D4 |
|
RW |
32 |
0x0000 0000 |
0x4D8 |
0x2810 C4D8 |
|
RW |
32 |
0x0000 0000 |
0x4DC |
0x2810 C4DC |
|
RW |
32 |
0x0080 0000 |
0x4E0 |
0x2810 C4E0 |
|
RW |
32 |
0x0000 0000 |
0x4E4 |
0x2810 C4E4 |
|
RW |
32 |
0x0000 0000 |
0x4E8 |
0x2810 C4E8 |
|
RW |
32 |
0x0000 0000 |
0x4EC |
0x2810 C4EC |
|
RW |
32 |
0x0000 0000 |
0x4F0 |
0x2810 C4F0 |
|
RW |
32 |
0x0000 0000 |
0x4F4 |
0x2810 C4F4 |
|
RW |
32 |
0x0000 0000 |
0x4F8 |
0x2810 C4F8 |
|
RW |
32 |
0x0000 0000 |
0x4FC |
0x2810 C4FC |
|
RW |
32 |
0x0080 0000 |
0x500 |
0x2810 C500 |
|
RW |
32 |
0x0000 0000 |
0x504 |
0x2810 C504 |
|
RW |
32 |
0x0000 0000 |
0x508 |
0x2810 C508 |
|
RW |
32 |
0x0000 0000 |
0x50C |
0x2810 C50C |
|
RW |
32 |
0x0000 0000 |
0x510 |
0x2810 C510 |
|
RW |
32 |
0x0000 0000 |
0x514 |
0x2810 C514 |
|
RW |
32 |
0x0000 0000 |
0x518 |
0x2810 C518 |
|
RW |
32 |
0x0000 0000 |
0x51C |
0x2810 C51C |
|
RW |
32 |
0x0080 0000 |
0x520 |
0x2810 C520 |
|
RW |
32 |
0x0000 0000 |
0x524 |
0x2810 C524 |
|
RW |
32 |
0x0000 0000 |
0x528 |
0x2810 C528 |
|
RW |
32 |
0x0000 0000 |
0x52C |
0x2810 C52C |
|
RW |
32 |
0x0000 0000 |
0x530 |
0x2810 C530 |
|
RW |
32 |
0x0000 0000 |
0x534 |
0x2810 C534 |
|
RW |
32 |
0x0000 0000 |
0x538 |
0x2810 C538 |
|
RW |
32 |
0x0000 0000 |
0x53C |
0x2810 C53C |
|
RW |
32 |
0x0080 0000 |
0x540 |
0x2810 C540 |
|
RW |
32 |
0x0000 0000 |
0x544 |
0x2810 C544 |
|
RW |
32 |
0x0000 0000 |
0x548 |
0x2810 C548 |
|
RW |
32 |
0x0000 0000 |
0x54C |
0x2810 C54C |
|
RW |
32 |
0x0000 0000 |
0x550 |
0x2810 C550 |
|
RW |
32 |
0x0000 0000 |
0x554 |
0x2810 C554 |
|
RW |
32 |
0x0000 0000 |
0x558 |
0x2810 C558 |
|
RW |
32 |
0x0000 0000 |
0x55C |
0x2810 C55C |
|
RW |
32 |
0x0080 0000 |
0x560 |
0x2810 C560 |
|
RW |
32 |
0x0000 0000 |
0x564 |
0x2810 C564 |
|
RW |
32 |
0x0000 0000 |
0x568 |
0x2810 C568 |
|
RW |
32 |
0x0000 0000 |
0x56C |
0x2810 C56C |
|
RW |
32 |
0x0000 0000 |
0x570 |
0x2810 C570 |
|
RW |
32 |
0x0000 0000 |
0x574 |
0x2810 C574 |
|
RW |
32 |
0x0000 0000 |
0x578 |
0x2810 C578 |
|
RW |
32 |
0x0000 0000 |
0x57C |
0x2810 C57C |
|
RW |
32 |
0x0080 0000 |
0x580 |
0x2810 C580 |
|
RW |
32 |
0x0000 0000 |
0x584 |
0x2810 C584 |
|
RW |
32 |
0x0000 0000 |
0x588 |
0x2810 C588 |
|
RW |
32 |
0x0000 0000 |
0x58C |
0x2810 C58C |
|
RW |
32 |
0x0000 0000 |
0x590 |
0x2810 C590 |
|
RW |
32 |
0x0000 0000 |
0x594 |
0x2810 C594 |
|
RW |
32 |
0x0000 0000 |
0x598 |
0x2810 C598 |
|
RW |
32 |
0x0000 0000 |
0x59C |
0x2810 C59C |
|
RW |
32 |
0x0080 0000 |
0x5A0 |
0x2810 C5A0 |
|
RW |
32 |
0x0000 0000 |
0x5A4 |
0x2810 C5A4 |
|
RW |
32 |
0x0000 0000 |
0x5A8 |
0x2810 C5A8 |
|
RW |
32 |
0x0000 0000 |
0x5AC |
0x2810 C5AC |
|
RW |
32 |
0x0000 0000 |
0x5B0 |
0x2810 C5B0 |
|
RW |
32 |
0x0000 0000 |
0x5B4 |
0x2810 C5B4 |
|
RW |
32 |
0x0000 0000 |
0x5B8 |
0x2810 C5B8 |
|
RW |
32 |
0x0000 0000 |
0x5BC |
0x2810 C5BC |
|
RW |
32 |
0x0080 0000 |
0x5C0 |
0x2810 C5C0 |
|
RW |
32 |
0x0000 0000 |
0x5C4 |
0x2810 C5C4 |
|
RW |
32 |
0x0000 0000 |
0x5C8 |
0x2810 C5C8 |
|
RW |
32 |
0x0000 0000 |
0x5CC |
0x2810 C5CC |
|
RW |
32 |
0x0000 0000 |
0x5D0 |
0x2810 C5D0 |
|
RW |
32 |
0x0000 0000 |
0x5D4 |
0x2810 C5D4 |
|
RW |
32 |
0x0000 0000 |
0x5D8 |
0x2810 C5D8 |
|
RW |
32 |
0x0000 0000 |
0x5DC |
0x2810 C5DC |
|
RW |
32 |
0x0080 0000 |
0x5E0 |
0x2810 C5E0 |
|
RW |
32 |
0x0000 0000 |
0x5E4 |
0x2810 C5E4 |
|
RW |
32 |
0x0000 0000 |
0x5E8 |
0x2810 C5E8 |
|
RW |
32 |
0x0000 0000 |
0x5EC |
0x2810 C5EC |
|
RW |
32 |
0x0000 0000 |
0x5F0 |
0x2810 C5F0 |
|
RW |
32 |
0x0000 0000 |
0x5F4 |
0x2810 C5F4 |
|
RW |
32 |
0x0000 0000 |
0x5F8 |
0x2810 C5F8 |
|
RW |
32 |
0x0000 0000 |
0x5FC |
0x2810 C5FC |
|
RW |
32 |
0x0080 0000 |
0x600 |
0x2810 C600 |
|
RW |
32 |
0x0000 0000 |
0x604 |
0x2810 C604 |
|
RW |
32 |
0x0000 0000 |
0x608 |
0x2810 C608 |
|
RW |
32 |
0x0000 0000 |
0x60C |
0x2810 C60C |
|
RW |
32 |
0x0000 0000 |
0x610 |
0x2810 C610 |
|
RW |
32 |
0x0000 0000 |
0x614 |
0x2810 C614 |
|
RW |
32 |
0x0000 0000 |
0x618 |
0x2810 C618 |
|
RW |
32 |
0x0000 0000 |
0x61C |
0x2810 C61C |
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x000 |
0x2810 D000 |
|
RW |
32 |
0x0000 0000 |
0x004 |
0x2810 D004 |
|
RO |
32 |
0x0000 0000 |
0x008 |
0x2810 D008 |
|
RO |
32 |
0x0000 0000 |
0x00C |
0x2810 D00C |
|
RO |
32 |
0x0000 0000 |
0x010 |
0x2810 D010 |
|
RW |
32 |
0x0000 0000 |
0x014 |
0x2810 D014 |
|
RW |
32 |
0x0000 0000 |
0x018 |
0x2810 D018 |
|
RW |
32 |
0x0000 0000 |
0x01C |
0x2810 D01C |
|
RW |
32 |
0x0080 0000 |
0x020 |
0x2810 D020 |
|
RW |
32 |
0x0000 0000 |
0x024 |
0x2810 D024 |
|
RW |
32 |
0x0000 0000 |
0x028 |
0x2810 D028 |
|
RW |
32 |
0x0000 0000 |
0x02C |
0x2810 D02C |
|
RW |
32 |
0x0080 0000 |
0x030 |
0x2810 D030 |
|
RW |
32 |
0x0000 0000 |
0x034 |
0x2810 D034 |
|
RW |
32 |
0x0000 0000 |
0x038 |
0x2810 D038 |
|
RW |
32 |
0x0000 0000 |
0x03C |
0x2810 D03C |
|
RW |
32 |
0x0080 0000 |
0x040 |
0x2810 D040 |
|
RW |
32 |
0x0000 0000 |
0x044 |
0x2810 D044 |
|
RW |
32 |
0x0000 0000 |
0x048 |
0x2810 D048 |
|
RW |
32 |
0x0000 0000 |
0x04C |
0x2810 D04C |
|
RW |
32 |
0x0080 0000 |
0x050 |
0x2810 D050 |
|
RW |
32 |
0x0000 0000 |
0x054 |
0x2810 D054 |
|
RW |
32 |
0x0000 0000 |
0x058 |
0x2810 D058 |
|
RW |
32 |
0x0000 0000 |
0x05C |
0x2810 D05C |
|
RW |
32 |
0x0080 0000 |
0x060 |
0x2810 D060 |
|
RW |
32 |
0x0000 0000 |
0x064 |
0x2810 D064 |
|
RW |
32 |
0x0000 0000 |
0x068 |
0x2810 D068 |
|
RW |
32 |
0x0000 0000 |
0x06C |
0x2810 D06C |
|
RW |
32 |
0x0080 0000 |
0x070 |
0x2810 D070 |
|
RW |
32 |
0x0000 0000 |
0x074 |
0x2810 D074 |
|
RW |
32 |
0x0000 0000 |
0x078 |
0x2810 D078 |
|
RW |
32 |
0x0000 0000 |
0x07C |
0x2810 D07C |
|
RW |
32 |
0x0080 0000 |
0x080 |
0x2810 D080 |
|
RW |
32 |
0x0000 0000 |
0x084 |
0x2810 D084 |
|
RW |
32 |
0x0000 0000 |
0x088 |
0x2810 D088 |
|
RW |
32 |
0x0000 0000 |
0x08C |
0x2810 D08C |
|
RW |
32 |
0x0080 0000 |
0x090 |
0x2810 D090 |
|
RW |
32 |
0x0000 0000 |
0x094 |
0x2810 D094 |
|
RW |
32 |
0x0000 0000 |
0x098 |
0x2810 D098 |
|
RW |
32 |
0x0000 0000 |
0x09C |
0x2810 D09C |
|
RW |
32 |
0x0080 0000 |
0x0A0 |
0x2810 D0A0 |
|
RW |
32 |
0x0000 0000 |
0x0A4 |
0x2810 D0A4 |
|
RW |
32 |
0x0000 0000 |
0x0A8 |
0x2810 D0A8 |
|
RW |
32 |
0x0000 0000 |
0x0AC |
0x2810 D0AC |
|
RW |
32 |
0x0080 0000 |
0x0B0 |
0x2810 D0B0 |
|
RW |
32 |
0x0000 0000 |
0x0B4 |
0x2810 D0B4 |
|
RW |
32 |
0x0000 0000 |
0x0B8 |
0x2810 D0B8 |
|
RW |
32 |
0x0000 0000 |
0x0BC |
0x2810 D0BC |
|
RW |
32 |
0x0080 0000 |
0x0C0 |
0x2810 D0C0 |
|
RW |
32 |
0x0000 0000 |
0x0C4 |
0x2810 D0C4 |
|
RW |
32 |
0x0000 0000 |
0x0C8 |
0x2810 D0C8 |
|
RW |
32 |
0x0000 0000 |
0x0CC |
0x2810 D0CC |
|
RW |
32 |
0x0080 0000 |
0x0D0 |
0x2810 D0D0 |
|
RW |
32 |
0x0000 0000 |
0x0D4 |
0x2810 D0D4 |
|
RW |
32 |
0x0000 0000 |
0x0D8 |
0x2810 D0D8 |
|
RW |
32 |
0x0000 0000 |
0x0DC |
0x2810 D0DC |
|
RW |
32 |
0x0080 0000 |
0x0E0 |
0x2810 D0E0 |
|
RW |
32 |
0x0000 0000 |
0x0E4 |
0x2810 D0E4 |
|
RW |
32 |
0x0000 0000 |
0x0E8 |
0x2810 D0E8 |
|
RW |
32 |
0x0000 0000 |
0x0EC |
0x2810 D0EC |
|
RW |
32 |
0x0080 0000 |
0x0F0 |
0x2810 D0F0 |
|
RW |
32 |
0x0000 0000 |
0x0F4 |
0x2810 D0F4 |
|
RW |
32 |
0x0000 0000 |
0x0F8 |
0x2810 D0F8 |
|
RW |
32 |
0x0000 0000 |
0x0FC |
0x2810 D0FC |
|
RW |
32 |
0x0080 0000 |
0x100 |
0x2810 D100 |
|
RW |
32 |
0x0000 0000 |
0x104 |
0x2810 D104 |
|
RW |
32 |
0x0000 0000 |
0x108 |
0x2810 D108 |
|
RW |
32 |
0x0000 0000 |
0x10C |
0x2810 D10C |
|
RW |
32 |
0x0080 0000 |
0x110 |
0x2810 D110 |
|
RW |
32 |
0x0000 0000 |
0x114 |
0x2810 D114 |
|
RW |
32 |
0x0000 0000 |
0x118 |
0x2810 D118 |
|
RW |
32 |
0x0000 0000 |
0x11C |
0x2810 D11C |
|
RW |
32 |
0x0080 0000 |
0x120 |
0x2810 D120 |
|
RW |
32 |
0x0000 0000 |
0x124 |
0x2810 D124 |
|
RW |
32 |
0x0000 0000 |
0x128 |
0x2810 D128 |
|
RW |
32 |
0x0000 0000 |
0x12C |
0x2810 D12C |
|
RW |
32 |
0x0080 0000 |
0x130 |
0x2810 D130 |
|
RW |
32 |
0x0000 0000 |
0x134 |
0x2810 D134 |
|
RW |
32 |
0x0000 0000 |
0x138 |
0x2810 D138 |
|
RW |
32 |
0x0000 0000 |
0x13C |
0x2810 D13C |
|
RW |
32 |
0x0080 0000 |
0x140 |
0x2810 D140 |
|
RW |
32 |
0x0000 0000 |
0x144 |
0x2810 D144 |
|
RW |
32 |
0x0000 0000 |
0x148 |
0x2810 D148 |
|
RW |
32 |
0x0000 0000 |
0x14C |
0x2810 D14C |
|
RW |
32 |
0x0080 0000 |
0x150 |
0x2810 D150 |
|
RW |
32 |
0x0000 0000 |
0x154 |
0x2810 D154 |
|
RW |
32 |
0x0000 0000 |
0x158 |
0x2810 D158 |
|
RW |
32 |
0x0000 0000 |
0x15C |
0x2810 D15C |
|
RW |
32 |
0x0080 0000 |
0x160 |
0x2810 D160 |
|
RW |
32 |
0x0000 0000 |
0x164 |
0x2810 D164 |
|
RW |
32 |
0x0000 0000 |
0x168 |
0x2810 D168 |
|
RW |
32 |
0x0000 0000 |
0x16C |
0x2810 D16C |
|
RW |
32 |
0x0080 0000 |
0x170 |
0x2810 D170 |
|
RW |
32 |
0x0000 0000 |
0x174 |
0x2810 D174 |
|
RW |
32 |
0x0000 0000 |
0x178 |
0x2810 D178 |
|
RW |
32 |
0x0000 0000 |
0x17C |
0x2810 D17C |
|
RW |
32 |
0x0080 0000 |
0x180 |
0x2810 D180 |
|
RW |
32 |
0x0000 0000 |
0x184 |
0x2810 D184 |
|
RW |
32 |
0x0000 0000 |
0x188 |
0x2810 D188 |
|
RW |
32 |
0x0000 0000 |
0x18C |
0x2810 D18C |
|
RW |
32 |
0x0080 0000 |
0x190 |
0x2810 D190 |
|
RW |
32 |
0x0000 0000 |
0x194 |
0x2810 D194 |
|
RW |
32 |
0x0000 0000 |
0x198 |
0x2810 D198 |
|
RW |
32 |
0x0000 0000 |
0x19C |
0x2810 D19C |
|
RW |
32 |
0x0080 0000 |
0x1A0 |
0x2810 D1A0 |
|
RW |
32 |
0x0000 0000 |
0x1A4 |
0x2810 D1A4 |
|
RW |
32 |
0x0000 0000 |
0x1A8 |
0x2810 D1A8 |
|
RW |
32 |
0x0000 0000 |
0x1AC |
0x2810 D1AC |
|
RW |
32 |
0x0080 0000 |
0x1B0 |
0x2810 D1B0 |
|
RW |
32 |
0x0000 0000 |
0x1B4 |
0x2810 D1B4 |
|
RW |
32 |
0x0000 0000 |
0x1B8 |
0x2810 D1B8 |
|
RW |
32 |
0x0000 0000 |
0x1BC |
0x2810 D1BC |
|
RW |
32 |
0x0080 0000 |
0x1C0 |
0x2810 D1C0 |
|
RW |
32 |
0x0000 0000 |
0x1C4 |
0x2810 D1C4 |
|
RW |
32 |
0x0000 0000 |
0x1C8 |
0x2810 D1C8 |
|
RW |
32 |
0x0000 0000 |
0x1CC |
0x2810 D1CC |
|
RW |
32 |
0x0080 0000 |
0x1D0 |
0x2810 D1D0 |
|
RW |
32 |
0x0000 0000 |
0x1D4 |
0x2810 D1D4 |
|
RW |
32 |
0x0000 0000 |
0x1D8 |
0x2810 D1D8 |
|
RW |
32 |
0x0000 0000 |
0x1DC |
0x2810 D1DC |
|
RW |
32 |
0x0080 0000 |
0x1E0 |
0x2810 D1E0 |
|
RW |
32 |
0x0000 0000 |
0x1E4 |
0x2810 D1E4 |
|
RW |
32 |
0x0000 0000 |
0x1E8 |
0x2810 D1E8 |
|
RW |
32 |
0x0000 0000 |
0x1EC |
0x2810 D1EC |
|
RW |
32 |
0x0080 0000 |
0x1F0 |
0x2810 D1F0 |
|
RW |
32 |
0x0000 0000 |
0x1F4 |
0x2810 D1F4 |
|
RW |
32 |
0x0000 0000 |
0x1F8 |
0x2810 D1F8 |
|
RW |
32 |
0x0000 0000 |
0x1FC |
0x2810 D1FC |
|
RW |
32 |
0x0080 0000 |
0x200 |
0x2810 D200 |
|
RW |
32 |
0x0000 0000 |
0x204 |
0x2810 D204 |
|
RW |
32 |
0x0000 0000 |
0x208 |
0x2810 D208 |
|
RW |
32 |
0x0000 0000 |
0x20C |
0x2810 D20C |
|
RW |
32 |
0x0080 0000 |
0x210 |
0x2810 D210 |
|
RW |
32 |
0x0000 0000 |
0x214 |
0x2810 D214 |
|
RW |
32 |
0x0000 0000 |
0x218 |
0x2810 D218 |
|
RW |
32 |
0x0000 0000 |
0x21C |
0x2810 D21C |
|
RW |
32 |
0x0080 0000 |
0x220 |
0x2810 D220 |
|
RW |
32 |
0x0000 0000 |
0x224 |
0x2810 D224 |
|
RW |
32 |
0x0000 0000 |
0x228 |
0x2810 D228 |
|
RW |
32 |
0x0000 0000 |
0x22C |
0x2810 D22C |
|
RW |
32 |
0x0000 0000 |
0x230 |
0x2810 D230 |
|
RW |
32 |
0x0000 0000 |
0x234 |
0x2810 D234 |
|
RW |
32 |
0x0000 0000 |
0x238 |
0x2810 D238 |
|
RW |
32 |
0x0000 0000 |
0x23C |
0x2810 D23C |
|
RW |
32 |
0x0080 0000 |
0x240 |
0x2810 D240 |
|
RW |
32 |
0x0000 0000 |
0x244 |
0x2810 D244 |
|
RW |
32 |
0x0000 0000 |
0x248 |
0x2810 D248 |
|
RW |
32 |
0x0000 0000 |
0x24C |
0x2810 D24C |
|
RW |
32 |
0x0000 0000 |
0x250 |
0x2810 D250 |
|
RW |
32 |
0x0000 0000 |
0x254 |
0x2810 D254 |
|
RW |
32 |
0x0000 0000 |
0x258 |
0x2810 D258 |
|
RW |
32 |
0x0000 0000 |
0x25C |
0x2810 D25C |
|
RW |
32 |
0x0080 0000 |
0x260 |
0x2810 D260 |
|
RW |
32 |
0x0000 0000 |
0x264 |
0x2810 D264 |
|
RW |
32 |
0x0000 0000 |
0x268 |
0x2810 D268 |
|
RW |
32 |
0x0000 0000 |
0x26C |
0x2810 D26C |
|
RW |
32 |
0x0000 0000 |
0x270 |
0x2810 D270 |
|
RW |
32 |
0x0000 0000 |
0x274 |
0x2810 D274 |
|
RW |
32 |
0x0000 0000 |
0x278 |
0x2810 D278 |
|
RW |
32 |
0x0000 0000 |
0x27C |
0x2810 D27C |
|
RW |
32 |
0x0080 0000 |
0x280 |
0x2810 D280 |
|
RW |
32 |
0x0000 0000 |
0x284 |
0x2810 D284 |
|
RW |
32 |
0x0000 0000 |
0x288 |
0x2810 D288 |
|
RW |
32 |
0x0000 0000 |
0x28C |
0x2810 D28C |
|
RW |
32 |
0x0000 0000 |
0x290 |
0x2810 D290 |
|
RW |
32 |
0x0000 0000 |
0x294 |
0x2810 D294 |
|
RW |
32 |
0x0000 0000 |
0x298 |
0x2810 D298 |
|
RW |
32 |
0x0000 0000 |
0x29C |
0x2810 D29C |
|
RW |
32 |
0x0080 0000 |
0x2A0 |
0x2810 D2A0 |
|
RW |
32 |
0x0000 0000 |
0x2A4 |
0x2810 D2A4 |
|
RW |
32 |
0x0000 0000 |
0x2A8 |
0x2810 D2A8 |
|
RW |
32 |
0x0000 0000 |
0x2AC |
0x2810 D2AC |
|
RW |
32 |
0x0000 0000 |
0x2B0 |
0x2810 D2B0 |
|
RW |
32 |
0x0000 0000 |
0x2B4 |
0x2810 D2B4 |
|
RW |
32 |
0x0000 0000 |
0x2B8 |
0x2810 D2B8 |
|
RW |
32 |
0x0000 0000 |
0x2BC |
0x2810 D2BC |
|
RW |
32 |
0x0080 0000 |
0x2C0 |
0x2810 D2C0 |
|
RW |
32 |
0x0000 0000 |
0x2C4 |
0x2810 D2C4 |
|
RW |
32 |
0x0000 0000 |
0x2C8 |
0x2810 D2C8 |
|
RW |
32 |
0x0000 0000 |
0x2CC |
0x2810 D2CC |
|
RW |
32 |
0x0000 0000 |
0x2D0 |
0x2810 D2D0 |
|
RW |
32 |
0x0000 0000 |
0x2D4 |
0x2810 D2D4 |
|
RW |
32 |
0x0000 0000 |
0x2D8 |
0x2810 D2D8 |
|
RW |
32 |
0x0000 0000 |
0x2DC |
0x2810 D2DC |
|
RW |
32 |
0x0080 0000 |
0x2E0 |
0x2810 D2E0 |
|
RW |
32 |
0x0000 0000 |
0x2E4 |
0x2810 D2E4 |
|
RW |
32 |
0x0000 0000 |
0x2E8 |
0x2810 D2E8 |
|
RW |
32 |
0x0000 0000 |
0x2EC |
0x2810 D2EC |
|
RW |
32 |
0x0000 0000 |
0x2F0 |
0x2810 D2F0 |
|
RW |
32 |
0x0000 0000 |
0x2F4 |
0x2810 D2F4 |
|
RW |
32 |
0x0000 0000 |
0x2F8 |
0x2810 D2F8 |
|
RW |
32 |
0x0000 0000 |
0x2FC |
0x2810 D2FC |
|
RW |
32 |
0x0080 0000 |
0x300 |
0x2810 D300 |
|
RW |
32 |
0x0000 0000 |
0x304 |
0x2810 D304 |
|
RW |
32 |
0x0000 0000 |
0x308 |
0x2810 D308 |
|
RW |
32 |
0x0000 0000 |
0x30C |
0x2810 D30C |
|
RW |
32 |
0x0000 0000 |
0x310 |
0x2810 D310 |
|
RW |
32 |
0x0000 0000 |
0x314 |
0x2810 D314 |
|
RW |
32 |
0x0000 0000 |
0x318 |
0x2810 D318 |
|
RW |
32 |
0x0000 0000 |
0x31C |
0x2810 D31C |
|
RW |
32 |
0x0080 0000 |
0x320 |
0x2810 D320 |
|
RW |
32 |
0x0000 0000 |
0x324 |
0x2810 D324 |
|
RW |
32 |
0x0000 0000 |
0x328 |
0x2810 D328 |
|
RW |
32 |
0x0000 0000 |
0x32C |
0x2810 D32C |
|
RW |
32 |
0x0000 0000 |
0x330 |
0x2810 D330 |
|
RW |
32 |
0x0000 0000 |
0x334 |
0x2810 D334 |
|
RW |
32 |
0x0000 0000 |
0x338 |
0x2810 D338 |
|
RW |
32 |
0x0000 0000 |
0x33C |
0x2810 D33C |
|
RW |
32 |
0x0080 0000 |
0x340 |
0x2810 D340 |
|
RW |
32 |
0x0000 0000 |
0x344 |
0x2810 D344 |
|
RW |
32 |
0x0000 0000 |
0x348 |
0x2810 D348 |
|
RW |
32 |
0x0000 0000 |
0x34C |
0x2810 D34C |
|
RW |
32 |
0x0000 0000 |
0x350 |
0x2810 D350 |
|
RW |
32 |
0x0000 0000 |
0x354 |
0x2810 D354 |
|
RW |
32 |
0x0000 0000 |
0x358 |
0x2810 D358 |
|
RW |
32 |
0x0000 0000 |
0x35C |
0x2810 D35C |
|
RW |
32 |
0x0080 0000 |
0x360 |
0x2810 D360 |
|
RW |
32 |
0x0000 0000 |
0x364 |
0x2810 D364 |
|
RW |
32 |
0x0000 0000 |
0x368 |
0x2810 D368 |
|
RW |
32 |
0x0000 0000 |
0x36C |
0x2810 D36C |
|
RW |
32 |
0x0000 0000 |
0x370 |
0x2810 D370 |
|
RW |
32 |
0x0000 0000 |
0x374 |
0x2810 D374 |
|
RW |
32 |
0x0000 0000 |
0x378 |
0x2810 D378 |
|
RW |
32 |
0x0000 0000 |
0x37C |
0x2810 D37C |
|
RW |
32 |
0x0080 0000 |
0x380 |
0x2810 D380 |
|
RW |
32 |
0x0000 0000 |
0x384 |
0x2810 D384 |
|
RW |
32 |
0x0000 0000 |
0x388 |
0x2810 D388 |
|
RW |
32 |
0x0000 0000 |
0x38C |
0x2810 D38C |
|
RW |
32 |
0x0000 0000 |
0x390 |
0x2810 D390 |
|
RW |
32 |
0x0000 0000 |
0x394 |
0x2810 D394 |
|
RW |
32 |
0x0000 0000 |
0x398 |
0x2810 D398 |
|
RW |
32 |
0x0000 0000 |
0x39C |
0x2810 D39C |
|
RW |
32 |
0x0080 0000 |
0x3A0 |
0x2810 D3A0 |
|
RW |
32 |
0x0000 0000 |
0x3A4 |
0x2810 D3A4 |
|
RW |
32 |
0x0000 0000 |
0x3A8 |
0x2810 D3A8 |
|
RW |
32 |
0x0000 0000 |
0x3AC |
0x2810 D3AC |
|
RW |
32 |
0x0000 0000 |
0x3B0 |
0x2810 D3B0 |
|
RW |
32 |
0x0000 0000 |
0x3B4 |
0x2810 D3B4 |
|
RW |
32 |
0x0000 0000 |
0x3B8 |
0x2810 D3B8 |
|
RW |
32 |
0x0000 0000 |
0x3BC |
0x2810 D3BC |
|
RW |
32 |
0x0080 0000 |
0x3C0 |
0x2810 D3C0 |
|
RW |
32 |
0x0000 0000 |
0x3C4 |
0x2810 D3C4 |
|
RW |
32 |
0x0000 0000 |
0x3C8 |
0x2810 D3C8 |
|
RW |
32 |
0x0000 0000 |
0x3CC |
0x2810 D3CC |
|
RW |
32 |
0x0000 0000 |
0x3D0 |
0x2810 D3D0 |
|
RW |
32 |
0x0000 0000 |
0x3D4 |
0x2810 D3D4 |
|
RW |
32 |
0x0000 0000 |
0x3D8 |
0x2810 D3D8 |
|
RW |
32 |
0x0000 0000 |
0x3DC |
0x2810 D3DC |
|
RW |
32 |
0x0080 0000 |
0x3E0 |
0x2810 D3E0 |
|
RW |
32 |
0x0000 0000 |
0x3E4 |
0x2810 D3E4 |
|
RW |
32 |
0x0000 0000 |
0x3E8 |
0x2810 D3E8 |
|
RW |
32 |
0x0000 0000 |
0x3EC |
0x2810 D3EC |
|
RW |
32 |
0x0000 0000 |
0x3F0 |
0x2810 D3F0 |
|
RW |
32 |
0x0000 0000 |
0x3F4 |
0x2810 D3F4 |
|
RW |
32 |
0x0000 0000 |
0x3F8 |
0x2810 D3F8 |
|
RW |
32 |
0x0000 0000 |
0x3FC |
0x2810 D3FC |
|
RW |
32 |
0x0080 0000 |
0x400 |
0x2810 D400 |
|
RW |
32 |
0x0000 0000 |
0x404 |
0x2810 D404 |
|
RW |
32 |
0x0000 0000 |
0x408 |
0x2810 D408 |
|
RW |
32 |
0x0000 0000 |
0x40C |
0x2810 D40C |
|
RW |
32 |
0x0000 0000 |
0x410 |
0x2810 D410 |
|
RW |
32 |
0x0000 0000 |
0x414 |
0x2810 D414 |
|
RW |
32 |
0x0000 0000 |
0x418 |
0x2810 D418 |
|
RW |
32 |
0x0000 0000 |
0x41C |
0x2810 D41C |
|
RW |
32 |
0x0080 0000 |
0x420 |
0x2810 D420 |
|
RW |
32 |
0x0000 0000 |
0x424 |
0x2810 D424 |
|
RW |
32 |
0x0000 0000 |
0x428 |
0x2810 D428 |
|
RW |
32 |
0x0000 0000 |
0x42C |
0x2810 D42C |
|
RW |
32 |
0x0000 0000 |
0x430 |
0x2810 D430 |
|
RW |
32 |
0x0000 0000 |
0x434 |
0x2810 D434 |
|
RW |
32 |
0x0000 0000 |
0x438 |
0x2810 D438 |
|
RW |
32 |
0x0000 0000 |
0x43C |
0x2810 D43C |
|
RW |
32 |
0x0080 0000 |
0x440 |
0x2810 D440 |
|
RW |
32 |
0x0000 0000 |
0x444 |
0x2810 D444 |
|
RW |
32 |
0x0000 0000 |
0x448 |
0x2810 D448 |
|
RW |
32 |
0x0000 0000 |
0x44C |
0x2810 D44C |
|
RW |
32 |
0x0000 0000 |
0x450 |
0x2810 D450 |
|
RW |
32 |
0x0000 0000 |
0x454 |
0x2810 D454 |
|
RW |
32 |
0x0000 0000 |
0x458 |
0x2810 D458 |
|
RW |
32 |
0x0000 0000 |
0x45C |
0x2810 D45C |
|
RW |
32 |
0x0080 0000 |
0x460 |
0x2810 D460 |
|
RW |
32 |
0x0000 0000 |
0x464 |
0x2810 D464 |
|
RW |
32 |
0x0000 0000 |
0x468 |
0x2810 D468 |
|
RW |
32 |
0x0000 0000 |
0x46C |
0x2810 D46C |
|
RW |
32 |
0x0000 0000 |
0x470 |
0x2810 D470 |
|
RW |
32 |
0x0000 0000 |
0x474 |
0x2810 D474 |
|
RW |
32 |
0x0000 0000 |
0x478 |
0x2810 D478 |
|
RW |
32 |
0x0000 0000 |
0x47C |
0x2810 D47C |
|
RW |
32 |
0x0080 0000 |
0x480 |
0x2810 D480 |
|
RW |
32 |
0x0000 0000 |
0x484 |
0x2810 D484 |
|
RW |
32 |
0x0000 0000 |
0x488 |
0x2810 D488 |
|
RW |
32 |
0x0000 0000 |
0x48C |
0x2810 D48C |
|
RW |
32 |
0x0000 0000 |
0x490 |
0x2810 D490 |
|
RW |
32 |
0x0000 0000 |
0x494 |
0x2810 D494 |
|
RW |
32 |
0x0000 0000 |
0x498 |
0x2810 D498 |
|
RW |
32 |
0x0000 0000 |
0x49C |
0x2810 D49C |
|
RW |
32 |
0x0080 0000 |
0x4A0 |
0x2810 D4A0 |
|
RW |
32 |
0x0000 0000 |
0x4A4 |
0x2810 D4A4 |
|
RW |
32 |
0x0000 0000 |
0x4A8 |
0x2810 D4A8 |
|
RW |
32 |
0x0000 0000 |
0x4AC |
0x2810 D4AC |
|
RW |
32 |
0x0000 0000 |
0x4B0 |
0x2810 D4B0 |
|
RW |
32 |
0x0000 0000 |
0x4B4 |
0x2810 D4B4 |
|
RW |
32 |
0x0000 0000 |
0x4B8 |
0x2810 D4B8 |
|
RW |
32 |
0x0000 0000 |
0x4BC |
0x2810 D4BC |
|
RW |
32 |
0x0080 0000 |
0x4C0 |
0x2810 D4C0 |
|
RW |
32 |
0x0000 0000 |
0x4C4 |
0x2810 D4C4 |
|
RW |
32 |
0x0000 0000 |
0x4C8 |
0x2810 D4C8 |
|
RW |
32 |
0x0000 0000 |
0x4CC |
0x2810 D4CC |
|
RW |
32 |
0x0000 0000 |
0x4D0 |
0x2810 D4D0 |
|
RW |
32 |
0x0000 0000 |
0x4D4 |
0x2810 D4D4 |
|
RW |
32 |
0x0000 0000 |
0x4D8 |
0x2810 D4D8 |
|
RW |
32 |
0x0000 0000 |
0x4DC |
0x2810 D4DC |
|
RW |
32 |
0x0080 0000 |
0x4E0 |
0x2810 D4E0 |
|
RW |
32 |
0x0000 0000 |
0x4E4 |
0x2810 D4E4 |
|
RW |
32 |
0x0000 0000 |
0x4E8 |
0x2810 D4E8 |
|
RW |
32 |
0x0000 0000 |
0x4EC |
0x2810 D4EC |
|
RW |
32 |
0x0000 0000 |
0x4F0 |
0x2810 D4F0 |
|
RW |
32 |
0x0000 0000 |
0x4F4 |
0x2810 D4F4 |
|
RW |
32 |
0x0000 0000 |
0x4F8 |
0x2810 D4F8 |
|
RW |
32 |
0x0000 0000 |
0x4FC |
0x2810 D4FC |
|
RW |
32 |
0x0080 0000 |
0x500 |
0x2810 D500 |
|
RW |
32 |
0x0000 0000 |
0x504 |
0x2810 D504 |
|
RW |
32 |
0x0000 0000 |
0x508 |
0x2810 D508 |
|
RW |
32 |
0x0000 0000 |
0x50C |
0x2810 D50C |
|
RW |
32 |
0x0000 0000 |
0x510 |
0x2810 D510 |
|
RW |
32 |
0x0000 0000 |
0x514 |
0x2810 D514 |
|
RW |
32 |
0x0000 0000 |
0x518 |
0x2810 D518 |
|
RW |
32 |
0x0000 0000 |
0x51C |
0x2810 D51C |
|
RW |
32 |
0x0080 0000 |
0x520 |
0x2810 D520 |
|
RW |
32 |
0x0000 0000 |
0x524 |
0x2810 D524 |
|
RW |
32 |
0x0000 0000 |
0x528 |
0x2810 D528 |
|
RW |
32 |
0x0000 0000 |
0x52C |
0x2810 D52C |
|
RW |
32 |
0x0000 0000 |
0x530 |
0x2810 D530 |
|
RW |
32 |
0x0000 0000 |
0x534 |
0x2810 D534 |
|
RW |
32 |
0x0000 0000 |
0x538 |
0x2810 D538 |
|
RW |
32 |
0x0000 0000 |
0x53C |
0x2810 D53C |
|
RW |
32 |
0x0080 0000 |
0x540 |
0x2810 D540 |
|
RW |
32 |
0x0000 0000 |
0x544 |
0x2810 D544 |
|
RW |
32 |
0x0000 0000 |
0x548 |
0x2810 D548 |
|
RW |
32 |
0x0000 0000 |
0x54C |
0x2810 D54C |
|
RW |
32 |
0x0000 0000 |
0x550 |
0x2810 D550 |
|
RW |
32 |
0x0000 0000 |
0x554 |
0x2810 D554 |
|
RW |
32 |
0x0000 0000 |
0x558 |
0x2810 D558 |
|
RW |
32 |
0x0000 0000 |
0x55C |
0x2810 D55C |
|
RW |
32 |
0x0080 0000 |
0x560 |
0x2810 D560 |
|
RW |
32 |
0x0000 0000 |
0x564 |
0x2810 D564 |
|
RW |
32 |
0x0000 0000 |
0x568 |
0x2810 D568 |
|
RW |
32 |
0x0000 0000 |
0x56C |
0x2810 D56C |
|
RW |
32 |
0x0000 0000 |
0x570 |
0x2810 D570 |
|
RW |
32 |
0x0000 0000 |
0x574 |
0x2810 D574 |
|
RW |
32 |
0x0000 0000 |
0x578 |
0x2810 D578 |
|
RW |
32 |
0x0000 0000 |
0x57C |
0x2810 D57C |
|
RW |
32 |
0x0080 0000 |
0x580 |
0x2810 D580 |
|
RW |
32 |
0x0000 0000 |
0x584 |
0x2810 D584 |
|
RW |
32 |
0x0000 0000 |
0x588 |
0x2810 D588 |
|
RW |
32 |
0x0000 0000 |
0x58C |
0x2810 D58C |
|
RW |
32 |
0x0000 0000 |
0x590 |
0x2810 D590 |
|
RW |
32 |
0x0000 0000 |
0x594 |
0x2810 D594 |
|
RW |
32 |
0x0000 0000 |
0x598 |
0x2810 D598 |
|
RW |
32 |
0x0000 0000 |
0x59C |
0x2810 D59C |
|
RW |
32 |
0x0080 0000 |
0x5A0 |
0x2810 D5A0 |
|
RW |
32 |
0x0000 0000 |
0x5A4 |
0x2810 D5A4 |
|
RW |
32 |
0x0000 0000 |
0x5A8 |
0x2810 D5A8 |
|
RW |
32 |
0x0000 0000 |
0x5AC |
0x2810 D5AC |
|
RW |
32 |
0x0000 0000 |
0x5B0 |
0x2810 D5B0 |
|
RW |
32 |
0x0000 0000 |
0x5B4 |
0x2810 D5B4 |
|
RW |
32 |
0x0000 0000 |
0x5B8 |
0x2810 D5B8 |
|
RW |
32 |
0x0000 0000 |
0x5BC |
0x2810 D5BC |
|
RW |
32 |
0x0080 0000 |
0x5C0 |
0x2810 D5C0 |
|
RW |
32 |
0x0000 0000 |
0x5C4 |
0x2810 D5C4 |
|
RW |
32 |
0x0000 0000 |
0x5C8 |
0x2810 D5C8 |
|
RW |
32 |
0x0000 0000 |
0x5CC |
0x2810 D5CC |
|
RW |
32 |
0x0000 0000 |
0x5D0 |
0x2810 D5D0 |
|
RW |
32 |
0x0000 0000 |
0x5D4 |
0x2810 D5D4 |
|
RW |
32 |
0x0000 0000 |
0x5D8 |
0x2810 D5D8 |
|
RW |
32 |
0x0000 0000 |
0x5DC |
0x2810 D5DC |
|
RW |
32 |
0x0080 0000 |
0x5E0 |
0x2810 D5E0 |
|
RW |
32 |
0x0000 0000 |
0x5E4 |
0x2810 D5E4 |
|
RW |
32 |
0x0000 0000 |
0x5E8 |
0x2810 D5E8 |
|
RW |
32 |
0x0000 0000 |
0x5EC |
0x2810 D5EC |
|
RW |
32 |
0x0000 0000 |
0x5F0 |
0x2810 D5F0 |
|
RW |
32 |
0x0000 0000 |
0x5F4 |
0x2810 D5F4 |
|
RW |
32 |
0x0000 0000 |
0x5F8 |
0x2810 D5F8 |
|
RW |
32 |
0x0000 0000 |
0x5FC |
0x2810 D5FC |
|
RW |
32 |
0x0080 0000 |
0x600 |
0x2810 D600 |
|
RW |
32 |
0x0000 0000 |
0x604 |
0x2810 D604 |
|
RW |
32 |
0x0000 0000 |
0x608 |
0x2810 D608 |
|
RW |
32 |
0x0000 0000 |
0x60C |
0x2810 D60C |
|
RW |
32 |
0x0000 0000 |
0x610 |
0x2810 D610 |
|
RW |
32 |
0x0000 0000 |
0x614 |
0x2810 D614 |
|
RW |
32 |
0x0000 0000 |
0x618 |
0x2810 D618 |
|
RW |
32 |
0x0000 0000 |
0x61C |
0x2810 D61C |
Address offset |
0x000 |
||
Physical address |
0x2010 C000 |
Instance |
CAN_A_LO |
0x2010 D000 |
CAN_B_LO |
||
0x2810 C000 |
CAN_A_HI |
||
0x2810 D000 |
CAN_B_HI |
||
Description |
Interrupt status register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
Reserved |
|
RO |
0x0000 |
15 |
SST_FAILURE |
Single-shot transmission failure 0: Normal operation 1: A buffer
set for single shot transmission experienced an arbitration loss or a bus
error during transmission. |
RW |
0 |
14 |
STUCK_AT_0 |
Stuck at dominant error 0: Normal operation 1: Indicates
if receive (RX) input remains stuck at 0 (dominant level) for more than 11
consecutive bit times. |
RW |
0 |
13 |
RTR_MSG |
RTR auto-reply message sent 0: Normal operation 1:
Indicates that a RTR auto-reply message was sent. |
RW |
0 |
12 |
RX_MSG |
Receive message available 0: Normal operation 1: Indicates
a new message was successfully received and stored in a receive buffer which
has its RxIntEbl flag asserted. |
RW |
0 |
11 |
TX_MSG |
Message transmitted 0: Normal operation 1: Indicates a message
was successfully sent from a transmit buffer which has its TxIntEbl flag
asserted. |
RW |
0 |
10 |
RX_MSG_LOSS |
Received message lost 0: Normal operation 1: Indicates a
newly received message couldn't be stored because the target message buffer
was full (for example.. its MsgAv flag was set). |
RW |
0 |
9 |
BUS_OFF |
Bus Off 0: Normal operation 1: Indicates that the CAN
controller entered the bus-off error state. |
RW |
0 |
8 |
CRC_ERR |
CRC error 0: Normal operation 1: Indicates that a CAN crc
error is detected. |
RW |
0 |
7 |
FORM_ERR |
Format error 0: Normal operation 1: Indicates that a CAN
format error is detected. |
RW |
0 |
6 |
ACK_ERR |
Acknowledge error 0: Normal operation 1: Indicates that a CAN
message acknowledgement error is detected. |
RW |
0 |
5 |
STUFF_ERR |
Bit stuffing error 0: Normal operation 1: Indicates that a
CAN bit stuffing error is detected. |
RW |
0 |
4 |
BIT_ERR |
Bit error 0: Normal operation 1: Indicates that a CAN bit
error is detected. |
RW |
0 |
3 |
OVR_LOAD |
Overload message detected 0: Normal operation 1: Indicates
that a CAN overload message is detected. |
RW |
0 |
2 |
ARB_LOSS |
Arbitration loss 0: Normal operation 1: The message arbitration
was lost while sending a message. The message transmission is retried once
the CAN bus is idle again. |
RW |
0 |
1:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x004 |
||
Physical address |
0x2010 C004 |
Instance |
CAN_A_LO |
0x2010 D004 |
CAN_B_LO |
||
0x2810 C004 |
CAN_A_HI |
||
0x2810 D004 |
CAN_B_HI |
||
Description |
Interrupt enable register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
Reserved |
|
RO |
0x0000 |
15 |
sst_failure_int_enbl |
Single shot transmission failure interrupt enable. |
RW |
0 |
14 |
stuck_at_0_int_enbl |
Stuck at dominant error interrupt enable. |
RW |
0 |
13 |
rtr_msg_int_enbl |
RTR auto-reply message sent interrupt enable. |
RW |
0 |
12 |
rx_msg_int_enbl |
Receive message available interrupt enable. |
RW |
0 |
11 |
tx_msg_int_enbl |
Message transmitted interrupt enable. |
RW |
0 |
10 |
rx_msg_loss_int_enbl |
Received message lost interrupt enable. |
RW |
0 |
9 |
bus_off_int_enbl |
Bus off interrupt enable. |
RW |
0 |
8 |
crc_err_int_enbl |
CRC error interrupt enable. |
RW |
0 |
7 |
form_err_int_enbl |
Format error interrupt enable. |
RW |
0 |
6 |
ack_err_int_enbl |
Acknowledge error interrupt enable. |
RW |
0 |
5 |
stuff_err_int_enbl |
Bit stuffing error interrupt enable. |
RW |
0 |
4 |
bit_err_int_enbl |
Bit error interrupt enable. |
RW |
0 |
3 |
ovr_load_int_enbl |
Overload message detected interrupt enable. |
RW |
0 |
2 |
arb_loss_int_enbl |
Arbitration loss interrupt enable. |
RW |
0 |
1 |
Reserved |
|
RO |
0 |
0 |
Int_enbl |
Global interrupt enable flag. 0: All interrupts are
disabled 1: Enabled interrupt sources are available |
RW |
0 |
Address offset |
0x008 |
||
Physical address |
0x2010 C008 |
Instance |
CAN_A_LO |
0x2010 D008 |
CAN_B_LO |
||
0x2810 C008 |
CAN_A_HI |
||
0x2810 D008 |
CAN_B_HI |
||
Description |
Receive (RX) message buffer status. This bundles message
available (MsgAv) flags from all 32 receive message buffers. |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
RxMessage31 |
Message available in RxMessage buffer 31 |
RO |
0 |
30 |
RxMessage30 |
Message available in RxMessage buffer 30 |
RO |
0 |
29 |
RxMessage29 |
Message available in RxMessage buffer 29 |
RO |
0 |
28 |
RxMessage28 |
Message available in RxMessage buffer 28 |
RO |
0 |
27 |
RxMessage27 |
Message available in RxMessage buffer 27 |
RO |
0 |
26 |
RxMessage26 |
Message available in RxMessage buffer 26 |
RO |
0 |
25 |
RxMessage25 |
Message available in RxMessage buffer 25 |
RO |
0 |
24 |
RxMessage24 |
Message available in RxMessage buffer 24 |
RO |
0 |
23 |
RxMessage23 |
Message available in RxMessage buffer 23 |
RO |
0 |
22 |
RxMessage22 |
Message available in RxMessage buffer 22 |
RO |
0 |
21 |
RxMessage21 |
Message available in RxMessage buffer 21 |
RO |
0 |
20 |
RxMessage20 |
Message available in RxMessage buffer 20 |
RO |
0 |
19 |
RxMessage19 |
Message available in RxMessage buffer 19 |
RO |
0 |
18 |
RxMessage18 |
Message available in RxMessage buffer 18 |
RO |
0 |
17 |
RxMessage17 |
Message available in RxMessage buffer 17 |
RO |
0 |
16 |
RxMessage16 |
Message available in RxMessage buffer 16 |
RO |
0 |
15 |
RxMessage15 |
Message available in RxMessage buffer 15 |
RO |
0 |
14 |
RxMessage14 |
Message available in RxMessage buffer 14 |
RO |
0 |
13 |
RxMessage13 |
Message available in RxMessage buffer 13 |
RO |
0 |
12 |
RxMessage12 |
Message available in RxMessage buffer 12 |
RO |
0 |
11 |
RxMessage11 |
Message available in RxMessage buffer 11 |
RO |
0 |
10 |
RxMessage10 |
Message available in RxMessage buffer 10 |
RO |
0 |
9 |
RxMessage9 |
Message available in RxMessage buffer 9 |
RO |
0 |
8 |
RxMessage8 |
Message available in RxMessage buffer 8 |
RO |
0 |
7 |
RxMessage7 |
Message available in RxMessage buffer 7 |
RO |
0 |
6 |
RxMessage6 |
Message available in RxMessage buffer 6 |
RO |
0 |
5 |
RxMessage5 |
Message available in RxMessage buffer 5 |
RO |
0 |
4 |
RxMessage4 |
Message available in RxMessage buffer 4 |
RO |
0 |
3 |
RxMessage3 |
Message available in RxMessage buffer 3 |
RO |
0 |
2 |
RxMessage2 |
Message available in RxMessage buffer 2 |
RO |
0 |
1 |
RxMessage1 |
Message available in RxMessage buffer 1 |
RO |
0 |
0 |
RxMessage0 |
Message available in RxMessage buffer 0 |
RO |
0 |
Address offset |
0x00C |
||
Physical address |
0x2010 C00C |
Instance |
CAN_A_LO |
0x2010 D00C |
CAN_B_LO |
||
0x2810 C00C |
CAN_A_HI |
||
0x2810 D00C |
CAN_B_HI |
||
Description |
Transmit (TX) message buffer status. |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
TxMessage31 |
Message available in TxMessage buffer 31 |
RO |
0 |
30 |
TxMessage30 |
Message available in TxMessage buffer 30 |
RO |
0 |
29 |
TxMessage29 |
Message available in TxMessage buffer 29 |
RO |
0 |
28 |
TxMessage28 |
Message available in TxMessage buffer 28 |
RO |
0 |
27 |
TxMessage27 |
Message available in TxMessage buffer 27 |
RO |
0 |
26 |
TxMessage26 |
Message available in TxMessage buffer 26 |
RO |
0 |
25 |
TxMessage25 |
Message available in TxMessage buffer 25 |
RO |
0 |
24 |
TxMessage24 |
Message available in TxMessage buffer 24 |
RO |
0 |
23 |
TxMessage23 |
Message available in TxMessage buffer 23 |
RO |
0 |
22 |
TxMessage22 |
Message available in TxMessage buffer 22 |
RO |
0 |
21 |
TxMessage21 |
Message available in TxMessage buffer 21 |
RO |
0 |
20 |
TxMessage20 |
Message available in TxMessage buffer 20 |
RO |
0 |
19 |
TxMessage19 |
Message available in TxMessage buffer 19 |
RO |
0 |
18 |
TxMessage18 |
Message available in TxMessage buffer 18 |
RO |
0 |
17 |
TxMessage17 |
Message available in TxMessage buffer 17 |
RO |
0 |
16 |
TxMessage16 |
Message available in TxMessage buffer 16 |
RO |
0 |
15 |
TxMessage15 |
Message available in TxMessage buffer 15 |
RO |
0 |
14 |
TxMessage14 |
Message available in TxMessage buffer 14 |
RO |
0 |
13 |
TxMessage13 |
Message available in TxMessage buffer 13 |
RO |
0 |
12 |
TxMessage12 |
Message available in TxMessage buffer 12 |
RO |
0 |
11 |
TxMessage11 |
Message available in TxMessage buffer 11 |
RO |
0 |
10 |
TxMessage10 |
Message available in TxMessage buffer 10 |
RO |
0 |
9 |
TxMessage9 |
Message available in TxMessage buffer 9 |
RO |
0 |
8 |
TxMessage8 |
Message available in TxMessage buffer 8 |
RO |
0 |
7 |
TxMessage7 |
Message available in TxMessage buffer 7 |
RO |
0 |
6 |
TxMessage6 |
Message available in TxMessage buffer 6 |
RO |
0 |
5 |
TxMessage5 |
Message available in TxMessage buffer 5 |
RO |
0 |
4 |
TxMessage4 |
Message available in TxMessage buffer 4 |
RO |
0 |
3 |
TxMessage3 |
Message available in TxMessage buffer 3 |
RO |
0 |
2 |
TxMessage2 |
Message available in TxMessage buffer 2 |
RO |
0 |
1 |
TxMessage1 |
Message available in TxMessage buffer 1 |
RO |
0 |
0 |
TxMessage0 |
Message available in TxMessage buffer 0 |
RO |
0 |
Address offset |
0x010 |
||
Physical address |
0x2010 C010 |
Instance |
CAN_A_LO |
0x2010 D010 |
CAN_B_LO |
||
0x2810 C010 |
CAN_A_HI |
||
0x2810 D010 |
CAN_B_HI |
||
Description |
CAN error status indicator register |
||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:20 |
Reserved |
|
RO |
0x000 |
19 |
rxgte96 |
The receive error counter is greater or equal 96 dec. |
RO |
0 |
18 |
txgte96 |
The transmit error counter is greater or equal 96 dec. |
RO |
0 |
17:16 |
error_state |
The error state of the CAN mode: 00: error active (normal
operation) 01: error passive 1x: bus off |
RO |
0x0 |
15:8 |
rx_err_cnt |
The receive error counter as defined in CAN 2.0
specification. When in bus-off state.. this counter is used to count 128
groups of 11 receive bits. |
RO |
0x00 |
7:0 |
tx_err_cnt |
The transmit error counter as defined in CAN 2.0
specification. When it is greater than 255 dec.. it is fixed at 255 dec. |
RO |
0x00 |
Address offset |
0x014 |
||
Physical address |
0x2010 C014 |
Instance |
CAN_A_LO |
0x2010 D014 |
CAN_B_LO |
||
0x2810 C014 |
CAN_A_HI |
||
0x2810 D014 |
CAN_B_HI |
||
Description |
The CAN controller can be used in different operating modes.
By disabling transmitting data.. it is possible to use the CAN in Listen-only
mode.. enabling features such as automatic bit rate detection. Before
starting the CAN controller.. all the CAN configuration registers have to be
set according to the target application. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
Revision_Control |
This field contains the version of the CAN core in the following
format. This is a read-only field. [major version].[minor version].[revision
number] [31:28]: Major version [27:24]: Minor version [23:16]: Revision
number |
RO |
0x0000 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
SRAM_TEST_MODE |
SRAM Test mode 0: Normal operation 1: Enable SRAM Test
mode. |
RW |
0 |
2 |
LOOPBACK_TEST_MODE |
Loopback-test mode 0: Normal operation 1: Loopback mode is
enabled[1]: Listen-only mode. |
RW |
0 |
1 |
LISTEN_ONLY_MODE |
Listen-only mode 0: Active 1: CAN listen only. The output
is held at 'R' level. The CAN controller is only listening. |
RW |
0 |
0 |
RUN_STOP_MODE |
Run/Stop mode 0: Sets the CAN controller into Stop mode. Returns
0 when stopped. 1: Sets the CAN controller into Run mode. Returns 1 when
running. |
RW |
0 |
Address offset |
0x018 |
||
Physical address |
0x2010 C018 |
Instance |
CAN_A_LO |
0x2010 D018 |
CAN_B_LO |
||
0x2810 C018 |
CAN_A_HI |
||
0x2810 D018 |
CAN_B_HI |
||
Description |
CAN configuration register. |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31 |
Reserved |
|
RO |
0 |
30:16 |
CFG_BITRATE |
Configuration bit rate Prescaler for generating the time
quantum which defines the TQ: 0: One time quantum equals 1 clock cycle 1: One
time quantum equals 2 clock cycles 32767: One time quantum equals 32768 clock
cycles |
RW |
0x0000 |
15 |
Reserved |
|
RO |
0 |
14 |
ECR_MODE |
Error-capture mode 0: Free running. The ECR register shows
the current bit position within the CAN frame. 1: Capture mode. The ECR
register shows the bit position and type of the last captured CAN error. |
RW |
0 |
13 |
SWAP_ENDIAN |
The byte position of the CAN receive and transmit data
fields can be modified to match the endian setting of the processor or the
used CAN protocol. 0: CAN data byte position is not swapped (big endian). 1:
CAN data byte position is swapped (little endian). |
RW |
0 |
12 |
CFG_ARBITER |
Transmit buffer arbiter 0: Round robin arbitration. 1:
Fixed priority arbitration. |
RW |
0 |
11:8 |
CFG_TSEG1 |
Time segment 1. Time segment 1 includes the propagation time
Length of the first time segment: tseg1 = CFG_TSEG1+1 CFG_TSEG1 = 0 and
CFG_TSEG1 = 1 are not allowed. |
RW |
0x0 |
7:5 |
CFG_TSEG2 |
Time segment 2 Length of the second time segment: tseg2 =
CFG_TSEG2+1 CFG_TSEG2 = 0 is not allowed. CFG_TSEG2 = 1 is only allowed in
Direct-sampling mode. |
RW |
0x0 |
4 |
AUTO_RESTART |
The CAN can be set to restart either `by hand` or
automatically after a bus-off. 0: After bus-off.. the CAN must be restarted
'by hand'. This is the recommended setting. 1: After bus-off.. the CAN
restarts automatically after 128 groups of 11 recessive bits. |
RW |
0 |
3:2 |
CFG_SJW |
Synchronization Jump Width 1 sjw is less than or equal to
tseg1 and sjw is less than or equal to tseg2 |
RW |
0x0 |
1 |
SAMPLING_MODE |
CAN bus bit sampling 0: One sampling point is used in the
receiver path. 1: Three sampling points with majority decision are used. |
RW |
0 |
0 |
EDGE_MODE |
CAN bus synchronization logic 0: Edge from 'R' to 'D' is
used for synchronization. 1: Both edges are used. |
RW |
0 |
Address offset |
0x01C |
||
Physical address |
0x2010 C01C |
Instance |
CAN_A_LO |
0x2010 D01C |
CAN_B_LO |
||
0x2810 C01C |
CAN_A_HI |
||
0x2810 D01C |
CAN_B_HI |
||
Description |
Error capture register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:17 |
Reserved |
|
RO |
0x0000 |
16:12 |
Field |
This specifies the field of the ECR 0x00: Stopped 0x01:
Synchronize 0x05: Interframe 0x06: Bus idle 0x07: Start of frame 0x08:
Arbitration 0x09: Control 0x0A: Data 0x0B: CRC 0x0C: ACK 0x0D: End of frame
0x10: Error flag 0x11: Error echo 0x12: Error delimiter 0x18: Overload flag
0x19: Overload echo 0x1A: Overload delimiter Others: N/A |
RO |
0x00 |
11:6 |
Bit_number |
Bit number inside of field |
RO |
0x00 |
5 |
Rx_mode |
When asserted.. the CAN controller is the receiver. |
RO |
0 |
4 |
Tx_mode |
When asserted.. the CAN controller is the transmitter. |
WO |
0 |
3:1 |
Error_type |
Specifies different error types 0: Arbitration loss 1: Bit
error 2: Bit stuffing error 3: Acknowledge error 4: Form error 5: CRC error
Others: N/A |
WO |
0x0 |
0 |
Status |
Status of the ECR register 0: The ECR register captured an
error or is in free running mode. 1: The ECR register set to sample the
event. |
WO |
0 |
Address offset |
0x020 |
||
Physical address |
0x2010 C020 |
Instance |
CAN_A_LO |
0x2010 D020 |
CAN_B_LO |
||
0x2810 C020 |
CAN_A_HI |
||
0x2810 D020 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not In case of control flag bit, 0:
Bit[21:16] remain unchanged 1: The write protect is not set and bit[21:16]
are modified.. by default. The read back value of this bit is undefined Note:
Using the WPN flag enables simple retransmission of the same message by only
having to set the TxReq and TxAbort flags without taking care of the special
flags. In case of command flag bit, 0: Default and 1: prohibited |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; Remote bit. control flag bit 0: Standard message 1:
RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are
transmitted as they are.. but the number of data bytes is limited to eight 0:
Message has 0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data
bytes 9:15: Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not. In case of control flag bit, 0: Bit[2]
remains unchanged. 1: The write protect is not set and Bit[2] is modified..
default. In case of Command flag bit, 0:default, 1: prohibited |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x024 |
||
Physical address |
0x2010 C024 |
Instance |
CAN_A_LO |
0x2010 D024 |
CAN_B_LO |
||
0x2810 C024 |
CAN_A_HI |
||
0x2810 D024 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x028 |
||
Physical address |
0x2010 C028 |
Instance |
CAN_A_LO |
0x2010 D028 |
CAN_B_LO |
||
0x2810 C028 |
CAN_A_HI |
||
0x2810 D028 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG0_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x02C |
||
Physical address |
0x2010 C02C |
Instance |
CAN_A_LO |
0x2010 D02C |
CAN_B_LO |
||
0x2810 C02C |
CAN_A_HI |
||
0x2810 D02C |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG0_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]: CAN data byte
6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1 [31:24]: CAN
data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6 [7:0]: CAN data
byte 5 |
RW |
0x0000 0000 |
Address offset |
0x030 |
||
Physical address |
0x2010 C030 |
Instance |
CAN_A_LO |
0x2010 D030 |
CAN_B_LO |
||
0x2810 C030 |
CAN_A_HI |
||
0x2810 D030 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No message
transmit request. 1: Message transmit request Note: The Tx message buffer
must not be changed while TxReq is 1. Read: 0: TxReq completed 1: TxReq
pending |
RW |
0 |
Address offset |
0x034 |
||
Physical address |
0x2010 C034 |
Instance |
CAN_A_LO |
0x2010 D034 |
CAN_B_LO |
||
0x2810 C034 |
CAN_A_HI |
||
0x2810 D034 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x038 |
||
Physical address |
0x2010 C038 |
Instance |
CAN_A_LO |
0x2010 D038 |
CAN_B_LO |
||
0x2810 C038 |
CAN_A_HI |
||
0x2810 D038 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG1_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x03C |
||
Physical address |
0x2010 C03C |
Instance |
CAN_A_LO |
0x2010 D03C |
CAN_B_LO |
||
0x2810 C03C |
CAN_A_HI |
||
0x2810 D03C |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG1_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x040 |
||
Physical address |
0x2010 C040 |
Instance |
CAN_A_LO |
0x2010 D040 |
CAN_B_LO |
||
0x2810 C040 |
CAN_A_HI |
||
0x2810 D040 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x044 |
||
Physical address |
0x2010 C044 |
Instance |
CAN_A_LO |
0x2010 D044 |
CAN_B_LO |
||
0x2810 C044 |
CAN_A_HI |
||
0x2810 D044 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x048 |
||
Physical address |
0x2010 C048 |
Instance |
CAN_A_LO |
0x2010 D048 |
CAN_B_LO |
||
0x2810 C048 |
CAN_A_HI |
||
0x2810 D048 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG2_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x04C |
||
Physical address |
0x2010 C04C |
Instance |
CAN_A_LO |
0x2010 D04C |
CAN_B_LO |
||
0x2810 C04C |
CAN_A_HI |
||
0x2810 D04C |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG2_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x050 |
||
Physical address |
0x2010 C050 |
Instance |
CAN_A_LO |
0x2010 D050 |
CAN_B_LO |
||
0x2810 C050 |
CAN_A_HI |
||
0x2810 D050 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x054 |
||
Physical address |
0x2010 C054 |
Instance |
CAN_A_LO |
0x2010 D054 |
CAN_B_LO |
||
0x2810 C054 |
CAN_A_HI |
||
0x2810 D054 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x058 |
||
Physical address |
0x2010 C058 |
Instance |
CAN_A_LO |
0x2010 D058 |
CAN_B_LO |
||
0x2810 C058 |
CAN_A_HI |
||
0x2810 D058 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG3_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x05C |
||
Physical address |
0x2010 C05C |
Instance |
CAN_A_LO |
0x2010 D05C |
CAN_B_LO |
||
0x2810 C05C |
CAN_A_HI |
||
0x2810 D05C |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG3_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x060 |
||
Physical address |
0x2010 C060 |
Instance |
CAN_A_LO |
0x2010 D060 |
CAN_B_LO |
||
0x2810 C060 |
CAN_A_HI |
||
0x2810 D060 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x064 |
||
Physical address |
0x2010 C064 |
Instance |
CAN_A_LO |
0x2010 D064 |
CAN_B_LO |
||
0x2810 C064 |
CAN_A_HI |
||
0x2810 D064 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x068 |
||
Physical address |
0x2010 C068 |
Instance |
CAN_A_LO |
0x2010 D068 |
CAN_B_LO |
||
0x2810 C068 |
CAN_A_HI |
||
0x2810 D068 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG4_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x06C |
||
Physical address |
0x2010 C06C |
Instance |
CAN_A_LO |
0x2010 D06C |
CAN_B_LO |
||
0x2810 C06C |
CAN_A_HI |
||
0x2810 D06C |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG4_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x070 |
||
Physical address |
0x2010 C070 |
Instance |
CAN_A_LO |
0x2010 D070 |
CAN_B_LO |
||
0x2810 C070 |
CAN_A_HI |
||
0x2810 D070 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x074 |
||
Physical address |
0x2010 C074 |
Instance |
CAN_A_LO |
0x2010 D074 |
CAN_B_LO |
||
0x2810 C074 |
CAN_A_HI |
||
0x2810 D074 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x078 |
||
Physical address |
0x2010 C078 |
Instance |
CAN_A_LO |
0x2010 D078 |
CAN_B_LO |
||
0x2810 C078 |
CAN_A_HI |
||
0x2810 D078 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG5_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x07C |
||
Physical address |
0x2010 C07C |
Instance |
CAN_A_LO |
0x2010 D07C |
CAN_B_LO |
||
0x2810 C07C |
CAN_A_HI |
||
0x2810 D07C |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG5_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x080 |
||
Physical address |
0x2010 C080 |
Instance |
CAN_A_LO |
0x2010 D080 |
CAN_B_LO |
||
0x2810 C080 |
CAN_A_HI |
||
0x2810 D080 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x084 |
||
Physical address |
0x2010 C084 |
Instance |
CAN_A_LO |
0x2010 D084 |
CAN_B_LO |
||
0x2810 C084 |
CAN_A_HI |
||
0x2810 D084 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x088 |
||
Physical address |
0x2010 C088 |
Instance |
CAN_A_LO |
0x2010 D088 |
CAN_B_LO |
||
0x2810 C088 |
CAN_A_HI |
||
0x2810 D088 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG6_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x08C |
||
Physical address |
0x2010 C08C |
Instance |
CAN_A_LO |
0x2010 D08C |
CAN_B_LO |
||
0x2810 C08C |
CAN_A_HI |
||
0x2810 D08C |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG6_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x090 |
||
Physical address |
0x2010 C090 |
Instance |
CAN_A_LO |
0x2010 D090 |
CAN_B_LO |
||
0x2810 C090 |
CAN_A_HI |
||
0x2810 D090 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x094 |
||
Physical address |
0x2010 C094 |
Instance |
CAN_A_LO |
0x2010 D094 |
CAN_B_LO |
||
0x2810 C094 |
CAN_A_HI |
||
0x2810 D094 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x098 |
||
Physical address |
0x2010 C098 |
Instance |
CAN_A_LO |
0x2010 D098 |
CAN_B_LO |
||
0x2810 C098 |
CAN_A_HI |
||
0x2810 D098 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG7_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x09C |
||
Physical address |
0x2010 C09C |
Instance |
CAN_A_LO |
0x2010 D09C |
CAN_B_LO |
||
0x2810 C09C |
CAN_A_HI |
||
0x2810 D09C |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG7_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x0A0 |
||
Physical address |
0x2010 C0A0 |
Instance |
CAN_A_LO |
0x2010 D0A0 |
CAN_B_LO |
||
0x2810 C0A0 |
CAN_A_HI |
||
0x2810 D0A0 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x0A4 |
||
Physical address |
0x2010 C0A4 |
Instance |
CAN_A_LO |
0x2010 D0A4 |
CAN_B_LO |
||
0x2810 C0A4 |
CAN_A_HI |
||
0x2810 D0A4 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x0A8 |
||
Physical address |
0x2010 C0A8 |
Instance |
CAN_A_LO |
0x2010 D0A8 |
CAN_B_LO |
||
0x2810 C0A8 |
CAN_A_HI |
||
0x2810 D0A8 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG8_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x0AC |
||
Physical address |
0x2010 C0AC |
Instance |
CAN_A_LO |
0x2010 D0AC |
CAN_B_LO |
||
0x2810 C0AC |
CAN_A_HI |
||
0x2810 D0AC |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG8_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x0B0 |
||
Physical address |
0x2010 C0B0 |
Instance |
CAN_A_LO |
0x2010 D0B0 |
CAN_B_LO |
||
0x2810 C0B0 |
CAN_A_HI |
||
0x2810 D0B0 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x0B4 |
||
Physical address |
0x2010 C0B4 |
Instance |
CAN_A_LO |
0x2010 D0B4 |
CAN_B_LO |
||
0x2810 C0B4 |
CAN_A_HI |
||
0x2810 D0B4 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x0B8 |
||
Physical address |
0x2010 C0B8 |
Instance |
CAN_A_LO |
0x2010 D0B8 |
CAN_B_LO |
||
0x2810 C0B8 |
CAN_A_HI |
||
0x2810 D0B8 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG9_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x0BC |
||
Physical address |
0x2010 C0BC |
Instance |
CAN_A_LO |
0x2010 D0BC |
CAN_B_LO |
||
0x2810 C0BC |
CAN_A_HI |
||
0x2810 D0BC |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG9_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x0C0 |
||
Physical address |
0x2010 C0C0 |
Instance |
CAN_A_LO |
0x2010 D0C0 |
CAN_B_LO |
||
0x2810 C0C0 |
CAN_A_HI |
||
0x2810 D0C0 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x0C4 |
||
Physical address |
0x2010 C0C4 |
Instance |
CAN_A_LO |
0x2010 D0C4 |
CAN_B_LO |
||
0x2810 C0C4 |
CAN_A_HI |
||
0x2810 D0C4 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x0C8 |
||
Physical address |
0x2010 C0C8 |
Instance |
CAN_A_LO |
0x2010 D0C8 |
CAN_B_LO |
||
0x2810 C0C8 |
CAN_A_HI |
||
0x2810 D0C8 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG10_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x0CC |
||
Physical address |
0x2010 C0CC |
Instance |
CAN_A_LO |
0x2010 D0CC |
CAN_B_LO |
||
0x2810 C0CC |
CAN_A_HI |
||
0x2810 D0CC |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG10_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x0D0 |
||
Physical address |
0x2010 C0D0 |
Instance |
CAN_A_LO |
0x2010 D0D0 |
CAN_B_LO |
||
0x2810 C0D0 |
CAN_A_HI |
||
0x2810 D0D0 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x0D4 |
||
Physical address |
0x2010 C0D4 |
Instance |
CAN_A_LO |
0x2010 D0D4 |
CAN_B_LO |
||
0x2810 C0D4 |
CAN_A_HI |
||
0x2810 D0D4 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x0D8 |
||
Physical address |
0x2010 C0D8 |
Instance |
CAN_A_LO |
0x2010 D0D8 |
CAN_B_LO |
||
0x2810 C0D8 |
CAN_A_HI |
||
0x2810 D0D8 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG11_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x0DC |
||
Physical address |
0x2010 C0DC |
Instance |
CAN_A_LO |
0x2010 D0DC |
CAN_B_LO |
||
0x2810 C0DC |
CAN_A_HI |
||
0x2810 D0DC |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG11_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x0E0 |
||
Physical address |
0x2010 C0E0 |
Instance |
CAN_A_LO |
0x2010 D0E0 |
CAN_B_LO |
||
0x2810 C0E0 |
CAN_A_HI |
||
0x2810 D0E0 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x0E4 |
||
Physical address |
0x2010 C0E4 |
Instance |
CAN_A_LO |
0x2010 D0E4 |
CAN_B_LO |
||
0x2810 C0E4 |
CAN_A_HI |
||
0x2810 D0E4 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x0E8 |
||
Physical address |
0x2010 C0E8 |
Instance |
CAN_A_LO |
0x2010 D0E8 |
CAN_B_LO |
||
0x2810 C0E8 |
CAN_A_HI |
||
0x2810 D0E8 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG12_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x0EC |
||
Physical address |
0x2010 C0EC |
Instance |
CAN_A_LO |
0x2010 D0EC |
CAN_B_LO |
||
0x2810 C0EC |
CAN_A_HI |
||
0x2810 D0EC |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG12_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x0F0 |
||
Physical address |
0x2010 C0F0 |
Instance |
CAN_A_LO |
0x2010 D0F0 |
CAN_B_LO |
||
0x2810 C0F0 |
CAN_A_HI |
||
0x2810 D0F0 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x0F4 |
||
Physical address |
0x2010 C0F4 |
Instance |
CAN_A_LO |
0x2010 D0F4 |
CAN_B_LO |
||
0x2810 C0F4 |
CAN_A_HI |
||
0x2810 D0F4 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x0F8 |
||
Physical address |
0x2010 C0F8 |
Instance |
CAN_A_LO |
0x2010 D0F8 |
CAN_B_LO |
||
0x2810 C0F8 |
CAN_A_HI |
||
0x2810 D0F8 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG13_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x0FC |
||
Physical address |
0x2010 C0FC |
Instance |
CAN_A_LO |
0x2010 D0FC |
CAN_B_LO |
||
0x2810 C0FC |
CAN_A_HI |
||
0x2810 D0FC |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG13_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x100 |
||
Physical address |
0x2010 C100 |
Instance |
CAN_A_LO |
0x2010 D100 |
CAN_B_LO |
||
0x2810 C100 |
CAN_A_HI |
||
0x2810 D100 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x104 |
||
Physical address |
0x2010 C104 |
Instance |
CAN_A_LO |
0x2010 D104 |
CAN_B_LO |
||
0x2810 C104 |
CAN_A_HI |
||
0x2810 D104 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x108 |
||
Physical address |
0x2010 C108 |
Instance |
CAN_A_LO |
0x2010 D108 |
CAN_B_LO |
||
0x2810 C108 |
CAN_A_HI |
||
0x2810 D108 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG14_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x10C |
||
Physical address |
0x2010 C10C |
Instance |
CAN_A_LO |
0x2010 D10C |
CAN_B_LO |
||
0x2810 C10C |
CAN_A_HI |
||
0x2810 D10C |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG14_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x110 |
||
Physical address |
0x2010 C110 |
Instance |
CAN_A_LO |
0x2010 D110 |
CAN_B_LO |
||
0x2810 C110 |
CAN_A_HI |
||
0x2810 D110 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x114 |
||
Physical address |
0x2010 C114 |
Instance |
CAN_A_LO |
0x2010 D114 |
CAN_B_LO |
||
0x2810 C114 |
CAN_A_HI |
||
0x2810 D114 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x118 |
||
Physical address |
0x2010 C118 |
Instance |
CAN_A_LO |
0x2010 D118 |
CAN_B_LO |
||
0x2810 C118 |
CAN_A_HI |
||
0x2810 D118 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG15_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x11C |
||
Physical address |
0x2010 C11C |
Instance |
CAN_A_LO |
0x2010 D11C |
CAN_B_LO |
||
0x2810 C11C |
CAN_A_HI |
||
0x2810 D11C |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG15_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x120 |
||
Physical address |
0x2010 C120 |
Instance |
CAN_A_LO |
0x2010 D120 |
CAN_B_LO |
||
0x2810 C120 |
CAN_A_HI |
||
0x2810 D120 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x124 |
||
Physical address |
0x2010 C124 |
Instance |
CAN_A_LO |
0x2010 D124 |
CAN_B_LO |
||
0x2810 C124 |
CAN_A_HI |
||
0x2810 D124 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x128 |
||
Physical address |
0x2010 C128 |
Instance |
CAN_A_LO |
0x2010 D128 |
CAN_B_LO |
||
0x2810 C128 |
CAN_A_HI |
||
0x2810 D128 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG16_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x12C |
||
Physical address |
0x2010 C12C |
Instance |
CAN_A_LO |
0x2010 D12C |
CAN_B_LO |
||
0x2810 C12C |
CAN_A_HI |
||
0x2810 D12C |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG16_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x130 |
||
Physical address |
0x2010 C130 |
Instance |
CAN_A_LO |
0x2010 D130 |
CAN_B_LO |
||
0x2810 C130 |
CAN_A_HI |
||
0x2810 D130 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x134 |
||
Physical address |
0x2010 C134 |
Instance |
CAN_A_LO |
0x2010 D134 |
CAN_B_LO |
||
0x2810 C134 |
CAN_A_HI |
||
0x2810 D134 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x138 |
||
Physical address |
0x2010 C138 |
Instance |
CAN_A_LO |
0x2010 D138 |
CAN_B_LO |
||
0x2810 C138 |
CAN_A_HI |
||
0x2810 D138 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG17_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x13C |
||
Physical address |
0x2010 C13C |
Instance |
CAN_A_LO |
0x2010 D13C |
CAN_B_LO |
||
0x2810 C13C |
CAN_A_HI |
||
0x2810 D13C |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG17_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x140 |
||
Physical address |
0x2010 C140 |
Instance |
CAN_A_LO |
0x2010 D140 |
CAN_B_LO |
||
0x2810 C140 |
CAN_A_HI |
||
0x2810 D140 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x144 |
||
Physical address |
0x2010 C144 |
Instance |
CAN_A_LO |
0x2010 D144 |
CAN_B_LO |
||
0x2810 C144 |
CAN_A_HI |
||
0x2810 D144 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x148 |
||
Physical address |
0x2010 C148 |
Instance |
CAN_A_LO |
0x2010 D148 |
CAN_B_LO |
||
0x2810 C148 |
CAN_A_HI |
||
0x2810 D148 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG18_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x14C |
||
Physical address |
0x2010 C14C |
Instance |
CAN_A_LO |
0x2010 D14C |
CAN_B_LO |
||
0x2810 C14C |
CAN_A_HI |
||
0x2810 D14C |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG18_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x150 |
||
Physical address |
0x2010 C150 |
Instance |
CAN_A_LO |
0x2010 D150 |
CAN_B_LO |
||
0x2810 C150 |
CAN_A_HI |
||
0x2810 D150 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x154 |
||
Physical address |
0x2010 C154 |
Instance |
CAN_A_LO |
0x2010 D154 |
CAN_B_LO |
||
0x2810 C154 |
CAN_A_HI |
||
0x2810 D154 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x158 |
||
Physical address |
0x2010 C158 |
Instance |
CAN_A_LO |
0x2010 D158 |
CAN_B_LO |
||
0x2810 C158 |
CAN_A_HI |
||
0x2810 D158 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG19_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x15C |
||
Physical address |
0x2010 C15C |
Instance |
CAN_A_LO |
0x2010 D15C |
CAN_B_LO |
||
0x2810 C15C |
CAN_A_HI |
||
0x2810 D15C |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG19_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x160 |
||
Physical address |
0x2010 C160 |
Instance |
CAN_A_LO |
0x2010 D160 |
CAN_B_LO |
||
0x2810 C160 |
CAN_A_HI |
||
0x2810 D160 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x164 |
||
Physical address |
0x2010 C164 |
Instance |
CAN_A_LO |
0x2010 D164 |
CAN_B_LO |
||
0x2810 C164 |
CAN_A_HI |
||
0x2810 D164 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x168 |
||
Physical address |
0x2010 C168 |
Instance |
CAN_A_LO |
0x2010 D168 |
CAN_B_LO |
||
0x2810 C168 |
CAN_A_HI |
||
0x2810 D168 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG20_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x16C |
||
Physical address |
0x2010 C16C |
Instance |
CAN_A_LO |
0x2010 D16C |
CAN_B_LO |
||
0x2810 C16C |
CAN_A_HI |
||
0x2810 D16C |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG20_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x170 |
||
Physical address |
0x2010 C170 |
Instance |
CAN_A_LO |
0x2010 D170 |
CAN_B_LO |
||
0x2810 C170 |
CAN_A_HI |
||
0x2810 D170 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x174 |
||
Physical address |
0x2010 C174 |
Instance |
CAN_A_LO |
0x2010 D174 |
CAN_B_LO |
||
0x2810 C174 |
CAN_A_HI |
||
0x2810 D174 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x178 |
||
Physical address |
0x2010 C178 |
Instance |
CAN_A_LO |
0x2010 D178 |
CAN_B_LO |
||
0x2810 C178 |
CAN_A_HI |
||
0x2810 D178 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG21_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x17C |
||
Physical address |
0x2010 C17C |
Instance |
CAN_A_LO |
0x2010 D17C |
CAN_B_LO |
||
0x2810 C17C |
CAN_A_HI |
||
0x2810 D17C |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG21_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x180 |
||
Physical address |
0x2010 C180 |
Instance |
CAN_A_LO |
0x2010 D180 |
CAN_B_LO |
||
0x2810 C180 |
CAN_A_HI |
||
0x2810 D180 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x184 |
||
Physical address |
0x2010 C184 |
Instance |
CAN_A_LO |
0x2010 D184 |
CAN_B_LO |
||
0x2810 C184 |
CAN_A_HI |
||
0x2810 D184 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x188 |
||
Physical address |
0x2010 C188 |
Instance |
CAN_A_LO |
0x2010 D188 |
CAN_B_LO |
||
0x2810 C188 |
CAN_A_HI |
||
0x2810 D188 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG22_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x18C |
||
Physical address |
0x2010 C18C |
Instance |
CAN_A_LO |
0x2010 D18C |
CAN_B_LO |
||
0x2810 C18C |
CAN_A_HI |
||
0x2810 D18C |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG22_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x190 |
||
Physical address |
0x2010 C190 |
Instance |
CAN_A_LO |
0x2010 D190 |
CAN_B_LO |
||
0x2810 C190 |
CAN_A_HI |
||
0x2810 D190 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x194 |
||
Physical address |
0x2010 C194 |
Instance |
CAN_A_LO |
0x2010 D194 |
CAN_B_LO |
||
0x2810 C194 |
CAN_A_HI |
||
0x2810 D194 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x198 |
||
Physical address |
0x2010 C198 |
Instance |
CAN_A_LO |
0x2010 D198 |
CAN_B_LO |
||
0x2810 C198 |
CAN_A_HI |
||
0x2810 D198 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG23_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x19C |
||
Physical address |
0x2010 C19C |
Instance |
CAN_A_LO |
0x2010 D19C |
CAN_B_LO |
||
0x2810 C19C |
CAN_A_HI |
||
0x2810 D19C |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG23_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x1A0 |
||
Physical address |
0x2010 C1A0 |
Instance |
CAN_A_LO |
0x2010 D1A0 |
CAN_B_LO |
||
0x2810 C1A0 |
CAN_A_HI |
||
0x2810 D1A0 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x1A4 |
||
Physical address |
0x2010 C1A4 |
Instance |
CAN_A_LO |
0x2010 D1A4 |
CAN_B_LO |
||
0x2810 C1A4 |
CAN_A_HI |
||
0x2810 D1A4 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x1A8 |
||
Physical address |
0x2010 C1A8 |
Instance |
CAN_A_LO |
0x2010 D1A8 |
CAN_B_LO |
||
0x2810 C1A8 |
CAN_A_HI |
||
0x2810 D1A8 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG24_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x1AC |
||
Physical address |
0x2010 C1AC |
Instance |
CAN_A_LO |
0x2010 D1AC |
CAN_B_LO |
||
0x2810 C1AC |
CAN_A_HI |
||
0x2810 D1AC |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG24_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x1B0 |
||
Physical address |
0x2010 C1B0 |
Instance |
CAN_A_LO |
0x2010 D1B0 |
CAN_B_LO |
||
0x2810 C1B0 |
CAN_A_HI |
||
0x2810 D1B0 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not. In case of control flag bit, 0:
Bit[21:16] remain unchanged 1: The write protect is not set and bit[21:16]
are modified.. by default. The read back value of this bit is undefined Note:
Using the WPN flag enables simple retransmission of the same message by only
having to set the TxReq and TxAbort flags without taking care of the special
flags. In case of command flag bit, 0: default and 1: prohibited |
RW |
1 |
22 |
Reserved |
Reserved bit |
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are
transmitted as they are.. but the number of data bytes is limited to eight 0:
Message has 0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data
bytes 9:15: Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not. In case of control flag bit, 0: Bit[2]
remains unchanged. 1: The write protect is not set and Bit[2] is modified..
default. In case of command flag bit 0:default and 1: prohibited |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x1B4 |
||
Physical address |
0x2010 C1B4 |
Instance |
CAN_A_LO |
0x2010 D1B4 |
CAN_B_LO |
||
0x2810 C1B4 |
CAN_A_HI |
||
0x2810 D1B4 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer: identifier (29-bit wide).
[31:3]:ID[28:0] |
RW |
0x0000 0000 |
2:0 |
Reserved |
Reserved bits |
RO |
0x0 |
Address offset |
0x1B8 |
||
Physical address |
0x2010 C1B8 |
Instance |
CAN_A_LO |
0x2010 D1B8 |
CAN_B_LO |
||
0x2810 C1B8 |
CAN_A_HI |
||
0x2810 D1B8 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG25_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x1BC |
||
Physical address |
0x2010 C1BC |
Instance |
CAN_A_LO |
0x2010 D1BC |
CAN_B_LO |
||
0x2810 C1BC |
CAN_A_HI |
||
0x2810 D1BC |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG25_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]: CAN data byte
6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1 [31:24]: CAN
data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6 [7:0]: CAN data
byte 5 |
RW |
0x0000 0000 |
Address offset |
0x1C0 |
||
Physical address |
0x2010 C1C0 |
Instance |
CAN_A_LO |
0x2010 D1C0 |
CAN_B_LO |
||
0x2810 C1C0 |
CAN_A_HI |
||
0x2810 D1C0 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x1C4 |
||
Physical address |
0x2010 C1C4 |
Instance |
CAN_A_LO |
0x2010 D1C4 |
CAN_B_LO |
||
0x2810 C1C4 |
CAN_A_HI |
||
0x2810 D1C4 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x1C8 |
||
Physical address |
0x2010 C1C8 |
Instance |
CAN_A_LO |
0x2010 D1C8 |
CAN_B_LO |
||
0x2810 C1C8 |
CAN_A_HI |
||
0x2810 D1C8 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG26_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x1CC |
||
Physical address |
0x2010 C1CC |
Instance |
CAN_A_LO |
0x2010 D1CC |
CAN_B_LO |
||
0x2810 C1CC |
CAN_A_HI |
||
0x2810 D1CC |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG26_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x1D0 |
||
Physical address |
0x2010 C1D0 |
Instance |
CAN_A_LO |
0x2010 D1D0 |
CAN_B_LO |
||
0x2810 C1D0 |
CAN_A_HI |
||
0x2810 D1D0 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x1D4 |
||
Physical address |
0x2010 C1D4 |
Instance |
CAN_A_LO |
0x2010 D1D4 |
CAN_B_LO |
||
0x2810 C1D4 |
CAN_A_HI |
||
0x2810 D1D4 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x1D8 |
||
Physical address |
0x2010 C1D8 |
Instance |
CAN_A_LO |
0x2010 D1D8 |
CAN_B_LO |
||
0x2810 C1D8 |
CAN_A_HI |
||
0x2810 D1D8 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG27_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x1DC |
||
Physical address |
0x2010 C1DC |
Instance |
CAN_A_LO |
0x2010 D1DC |
CAN_B_LO |
||
0x2810 C1DC |
CAN_A_HI |
||
0x2810 D1DC |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG27_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x1E0 |
||
Physical address |
0x2010 C1E0 |
Instance |
CAN_A_LO |
0x2010 D1E0 |
CAN_B_LO |
||
0x2810 C1E0 |
CAN_A_HI |
||
0x2810 D1E0 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x1E4 |
||
Physical address |
0x2010 C1E4 |
Instance |
CAN_A_LO |
0x2010 D1E4 |
CAN_B_LO |
||
0x2810 C1E4 |
CAN_A_HI |
||
0x2810 D1E4 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x1E8 |
||
Physical address |
0x2010 C1E8 |
Instance |
CAN_A_LO |
0x2010 D1E8 |
CAN_B_LO |
||
0x2810 C1E8 |
CAN_A_HI |
||
0x2810 D1E8 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG28_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x1EC |
||
Physical address |
0x2010 C1EC |
Instance |
CAN_A_LO |
0x2010 D1EC |
CAN_B_LO |
||
0x2810 C1EC |
CAN_A_HI |
||
0x2810 D1EC |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG28_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x1F0 |
||
Physical address |
0x2010 C1F0 |
Instance |
CAN_A_LO |
0x2010 D1F0 |
CAN_B_LO |
||
0x2810 C1F0 |
CAN_A_HI |
||
0x2810 D1F0 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x1F4 |
||
Physical address |
0x2010 C1F4 |
Instance |
CAN_A_LO |
0x2010 D1F4 |
CAN_B_LO |
||
0x2810 C1F4 |
CAN_A_HI |
||
0x2810 D1F4 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x1F8 |
||
Physical address |
0x2010 C1F8 |
Instance |
CAN_A_LO |
0x2010 D1F8 |
CAN_B_LO |
||
0x2810 C1F8 |
CAN_A_HI |
||
0x2810 D1F8 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG29_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x1FC |
||
Physical address |
0x2010 C1FC |
Instance |
CAN_A_LO |
0x2010 D1FC |
CAN_B_LO |
||
0x2810 C1FC |
CAN_A_HI |
||
0x2810 D1FC |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG29_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x200 |
||
Physical address |
0x2010 C200 |
Instance |
CAN_A_LO |
0x2010 D200 |
CAN_B_LO |
||
0x2810 C200 |
CAN_A_HI |
||
0x2810 D200 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x204 |
||
Physical address |
0x2010 C204 |
Instance |
CAN_A_LO |
0x2010 D204 |
CAN_B_LO |
||
0x2810 C204 |
CAN_A_HI |
||
0x2810 D204 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x208 |
||
Physical address |
0x2010 C208 |
Instance |
CAN_A_LO |
0x2010 D208 |
CAN_B_LO |
||
0x2810 C208 |
CAN_A_HI |
||
0x2810 D208 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG30_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x20C |
||
Physical address |
0x2010 C20C |
Instance |
CAN_A_LO |
0x2010 D20C |
CAN_B_LO |
||
0x2810 C20C |
CAN_A_HI |
||
0x2810 D20C |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG30_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x210 |
||
Physical address |
0x2010 C210 |
Instance |
CAN_A_LO |
0x2010 D210 |
CAN_B_LO |
||
0x2810 C210 |
CAN_A_HI |
||
0x2810 D210 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer control and command register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPN_B |
Write protect not 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. by default. The read
back value of this bit is undefined Note: Using the WPN flag enables simple
retransmission of the same message by only having to set the TxReq and
TxAbort flags without taking care of the special flags |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR; control flag bit 0: Standard message 1: RTR message |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control flag bit 0: This is a
standard format message 1: This is an extended format message |
RW |
0 |
19:16 |
DLC |
Data length code; Control flag bit Invalid values are transmitted
as they are.. but the number of data bytes is limited to eight 0: Message has
0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9:15:
Message has 8 data bytes |
RW |
0x0 |
15:4 |
Reserved |
|
RO |
0x000 |
3 |
WPN_A |
Write protect not 0: Bit[2] remains unchanged. 1: The
write protect is not set and Bit[2] is modified.. default. |
RW |
0 |
2 |
TxIntEbl |
Tx interrupt enable; Control flag bit 0: Interrupt is
disabled. 1: Interrupt enabled.. successful message transmission sets the
TX_MSG flag in the interrupt controller. |
RW |
0 |
1 |
TxAbort |
Transmit abort request; Command flag bit 0: Idle 1:
Requests removal of a pending message. The message is removed the next time
an arbitration loss happens. The flag is cleared when the message is removed
or when the message wins arbitration. The TxReq flag is cleared at the same
time. |
RW |
0 |
0 |
TxReq |
Transmit request; Command flag bit Write: 0: Idle. No
message transmit request. 1: Message transmit request Note: The Tx message
buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1:
TxReq pending |
RW |
0 |
Address offset |
0x214 |
||
Physical address |
0x2010 C214 |
Instance |
CAN_A_LO |
0x2010 D214 |
CAN_B_LO |
||
0x2810 C214 |
CAN_A_HI |
||
0x2810 D214 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
Transmit message0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x218 |
||
Physical address |
0x2010 C218 |
Instance |
CAN_A_LO |
0x2010 D218 |
CAN_B_LO |
||
0x2810 C218 |
CAN_A_HI |
||
0x2810 D218 |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG31_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x21C |
||
Physical address |
0x2010 C21C |
Instance |
CAN_A_LO |
0x2010 D21C |
CAN_B_LO |
||
0x2810 C21C |
CAN_A_HI |
||
0x2810 D21C |
CAN_B_HI |
||
Description |
Transmit Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
TX_MSG31_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit swap_endian = 0.. default [31:24]: CAN data byte 5 [23:16]:
CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian =
1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x220 |
||
Physical address |
0x2010 C220 |
Instance |
CAN_A_LO |
0x2010 D220 |
CAN_B_LO |
||
0x2810 C220 |
CAN_A_HI |
||
0x2810 D220 |
CAN_B_HI |
||
Description |
Receive Message0 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high. In case of control flag bit, 0:
Bit[21:16] remain unchanged 1: The write protect is not set and bit[21:16]
are modified.. default The read back value of this bit is undefined. In case
of command flag bit, 0:default and 1: prohibited |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit(Remote bit); Control bit 0: This is a regular
message 1: This is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low. In case of control flag bit, 0:
Bits[6:3] remain unchanged 1: This write protect is not set and bits[6:3] are
modified.. default. This bit is always zero for read back. In case of command
flag bit 0:default and 1: prohibited. |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag
is set.. this bit shows if an RTR auto-reply message has been sent..
otherwise it indicates if the buffer contains a valid message. Read 0: Idle
1: New message available (RTRreply = 0).. RTR auto-reply message sent
(RTRreply = 1) Write 0: Idle 1: Acknowledges receipt of new message or
transmission of RTR auto-reply message. Note: Before acknowledging receipt of
a new message.. the message content must be copied into system memory.
Acknowledging a message clears the MsgAv flag. |
RW |
0 |
Address offset |
0x224 |
||
Physical address |
0x2010 C224 |
Instance |
CAN_A_LO |
0x2010 D224 |
CAN_B_LO |
||
0x2810 C224 |
CAN_A_HI |
||
0x2810 D224 |
CAN_B_HI |
||
Description |
Receive Message0 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide).
[31:3]:ID[28:0] |
RW |
0x0000 0000 |
2:0 |
Reserved |
[2:0]: Zeros |
RO |
0x0 |
Address offset |
0x228 |
||
Physical address |
0x2010 C228 |
Instance |
CAN_A_LO |
0x2010 D228 |
CAN_B_LO |
||
0x2810 C228 |
CAN_A_HI |
||
0x2810 D228 |
CAN_B_HI |
||
Description |
Receive Message0 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG0_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default: [31:24]: CAN data byte 1
[23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4
swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN
data byte 2 [7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x22C |
||
Physical address |
0x2010 C22C |
Instance |
CAN_A_LO |
0x2010 D22C |
CAN_B_LO |
||
0x2810 C22C |
CAN_A_HI |
||
0x2810 D22C |
CAN_B_HI |
||
Description |
Receive Message0 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG0_DATA_LOW |
The byte mapping can be set using the CAN swap_endian
configuration bit. swap_endian = 0.. default: [31:24]: CAN data byte 5
[23:16]: CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8
swap_endian = 1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN
data byte 6 [7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x230 |
||
Physical address |
0x2010 C230 |
Instance |
CAN_A_LO |
0x2010 D230 |
CAN_B_LO |
||
0x2810 C230 |
CAN_A_HI |
||
0x2810 D230 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG0_AMR |
Receive Message0 buffer AMR bits.(Accepatnce Mask
Register). [31:3]: Identifier [2]: IDE [1]: RTR [0]: Reserved AMR: 0: The
incoming bit is checked against the respective ACR. The message is not
accepted when the incoming bit does not match with the respective ACR flag.
1: The incoming bit is a "don't care". |
RW |
0x0000 0000 |
Address offset |
0x234 |
||
Physical address |
0x2010 C234 |
Instance |
CAN_A_LO |
0x2010 D234 |
CAN_B_LO |
||
0x2810 C234 |
CAN_A_HI |
||
0x2810 D234 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG0_ACR |
Receive Message0 buffer ACR bits. (Acceptance Code
Register), [31:3]: Identifier [2]: IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x238 |
||
Physical address |
0x2010 C238 |
Instance |
CAN_A_LO |
0x2010 D238 |
CAN_B_LO |
||
0x2810 C238 |
CAN_A_HI |
||
0x2810 D238 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG0_AMR_DATA |
Receive Message0 buffer AMR Data bits.(Acceptance Mask
Register-Data), [15:8]: CAN data byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x23C |
||
Physical address |
0x2010 C23C |
Instance |
CAN_A_LO |
0x2010 D23C |
CAN_B_LO |
||
0x2810 C23C |
CAN_A_HI |
||
0x2810 D23C |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG0_ACR_DATA |
Receive Message0 buffer ACR Data bits. (Acceptance Code
Register-Data): [15:8]: CAN data byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x240 |
||
Physical address |
0x2010 C240 |
Instance |
CAN_A_LO |
0x2010 D240 |
CAN_B_LO |
||
0x2810 C240 |
CAN_A_HI |
||
0x2810 D240 |
CAN_B_HI |
||
Description |
Receive Message1 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1: The
write protect is not set and bit[21:16] are modified.. default The read back
value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x244 |
||
Physical address |
0x2010 C244 |
Instance |
CAN_A_LO |
0x2010 D244 |
CAN_B_LO |
||
0x2810 C244 |
CAN_A_HI |
||
0x2810 D244 |
CAN_B_HI |
||
Description |
Receive Message1 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x248 |
||
Physical address |
0x2010 C248 |
Instance |
CAN_A_LO |
0x2010 D248 |
CAN_B_LO |
||
0x2810 C248 |
CAN_A_HI |
||
0x2810 D248 |
CAN_B_HI |
||
Description |
Receive Message1 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG1_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x24C |
||
Physical address |
0x2010 C24C |
Instance |
CAN_A_LO |
0x2010 D24C |
CAN_B_LO |
||
0x2810 C24C |
CAN_A_HI |
||
0x2810 D24C |
CAN_B_HI |
||
Description |
Receive Message1 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG1_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x250 |
||
Physical address |
0x2010 C250 |
Instance |
CAN_A_LO |
0x2010 D250 |
CAN_B_LO |
||
0x2810 C250 |
CAN_A_HI |
||
0x2810 D250 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG1_AMR |
Receive Message1 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x254 |
||
Physical address |
0x2010 C254 |
Instance |
CAN_A_LO |
0x2010 D254 |
CAN_B_LO |
||
0x2810 C254 |
CAN_A_HI |
||
0x2810 D254 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG1_ACR |
Receive Message1 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x258 |
||
Physical address |
0x2010 C258 |
Instance |
CAN_A_LO |
0x2010 D258 |
CAN_B_LO |
||
0x2810 C258 |
CAN_A_HI |
||
0x2810 D258 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG1_AMR_DATA |
Receive Message1 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x25C |
||
Physical address |
0x2010 C25C |
Instance |
CAN_A_LO |
0x2010 D25C |
CAN_B_LO |
||
0x2810 C25C |
CAN_A_HI |
||
0x2810 D25C |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG1_ACR_DATA |
Receive Message1 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x260 |
||
Physical address |
0x2010 C260 |
Instance |
CAN_A_LO |
0x2010 D260 |
CAN_B_LO |
||
0x2810 C260 |
CAN_A_HI |
||
0x2810 D260 |
CAN_B_HI |
||
Description |
Receive Message2 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x264 |
||
Physical address |
0x2010 C264 |
Instance |
CAN_A_LO |
0x2010 D264 |
CAN_B_LO |
||
0x2810 C264 |
CAN_A_HI |
||
0x2810 D264 |
CAN_B_HI |
||
Description |
Receive Message2 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x268 |
||
Physical address |
0x2010 C268 |
Instance |
CAN_A_LO |
0x2010 D268 |
CAN_B_LO |
||
0x2810 C268 |
CAN_A_HI |
||
0x2810 D268 |
CAN_B_HI |
||
Description |
Receive Message2 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG2_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x26C |
||
Physical address |
0x2010 C26C |
Instance |
CAN_A_LO |
0x2010 D26C |
CAN_B_LO |
||
0x2810 C26C |
CAN_A_HI |
||
0x2810 D26C |
CAN_B_HI |
||
Description |
Receive Message2 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG2_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x270 |
||
Physical address |
0x2010 C270 |
Instance |
CAN_A_LO |
0x2010 D270 |
CAN_B_LO |
||
0x2810 C270 |
CAN_A_HI |
||
0x2810 D270 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG2_AMR |
Receive Message2 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x274 |
||
Physical address |
0x2010 C274 |
Instance |
CAN_A_LO |
0x2010 D274 |
CAN_B_LO |
||
0x2810 C274 |
CAN_A_HI |
||
0x2810 D274 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG2_ACR |
Receive Message2 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x278 |
||
Physical address |
0x2010 C278 |
Instance |
CAN_A_LO |
0x2010 D278 |
CAN_B_LO |
||
0x2810 C278 |
CAN_A_HI |
||
0x2810 D278 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG2_AMR_DATA |
Receive Message2 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x27C |
||
Physical address |
0x2010 C27C |
Instance |
CAN_A_LO |
0x2010 D27C |
CAN_B_LO |
||
0x2810 C27C |
CAN_A_HI |
||
0x2810 D27C |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG2_ACR_DATA |
Receive Message2 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x280 |
||
Physical address |
0x2010 C280 |
Instance |
CAN_A_LO |
0x2010 D280 |
CAN_B_LO |
||
0x2810 C280 |
CAN_A_HI |
||
0x2810 D280 |
CAN_B_HI |
||
Description |
Receive Message3 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x284 |
||
Physical address |
0x2010 C284 |
Instance |
CAN_A_LO |
0x2010 D284 |
CAN_B_LO |
||
0x2810 C284 |
CAN_A_HI |
||
0x2810 D284 |
CAN_B_HI |
||
Description |
Receive Message3 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x288 |
||
Physical address |
0x2010 C288 |
Instance |
CAN_A_LO |
0x2010 D288 |
CAN_B_LO |
||
0x2810 C288 |
CAN_A_HI |
||
0x2810 D288 |
CAN_B_HI |
||
Description |
Receive Message3 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG3_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x28C |
||
Physical address |
0x2010 C28C |
Instance |
CAN_A_LO |
0x2010 D28C |
CAN_B_LO |
||
0x2810 C28C |
CAN_A_HI |
||
0x2810 D28C |
CAN_B_HI |
||
Description |
Receive Message3 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG3_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x290 |
||
Physical address |
0x2010 C290 |
Instance |
CAN_A_LO |
0x2010 D290 |
CAN_B_LO |
||
0x2810 C290 |
CAN_A_HI |
||
0x2810 D290 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG3_AMR |
Receive Message3 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x294 |
||
Physical address |
0x2010 C294 |
Instance |
CAN_A_LO |
0x2010 D294 |
CAN_B_LO |
||
0x2810 C294 |
CAN_A_HI |
||
0x2810 D294 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG3_ACR |
Receive Message3 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x298 |
||
Physical address |
0x2010 C298 |
Instance |
CAN_A_LO |
0x2010 D298 |
CAN_B_LO |
||
0x2810 C298 |
CAN_A_HI |
||
0x2810 D298 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG3_AMR_DATA |
Receive Message3 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x29C |
||
Physical address |
0x2010 C29C |
Instance |
CAN_A_LO |
0x2010 D29C |
CAN_B_LO |
||
0x2810 C29C |
CAN_A_HI |
||
0x2810 D29C |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG3_ACR_DATA |
Receive Message3 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x2A0 |
||
Physical address |
0x2010 C2A0 |
Instance |
CAN_A_LO |
0x2010 D2A0 |
CAN_B_LO |
||
0x2810 C2A0 |
CAN_A_HI |
||
0x2810 D2A0 |
CAN_B_HI |
||
Description |
Receive Message4 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x2A4 |
||
Physical address |
0x2010 C2A4 |
Instance |
CAN_A_LO |
0x2010 D2A4 |
CAN_B_LO |
||
0x2810 C2A4 |
CAN_A_HI |
||
0x2810 D2A4 |
CAN_B_HI |
||
Description |
Receive Message4 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x2A8 |
||
Physical address |
0x2010 C2A8 |
Instance |
CAN_A_LO |
0x2010 D2A8 |
CAN_B_LO |
||
0x2810 C2A8 |
CAN_A_HI |
||
0x2810 D2A8 |
CAN_B_HI |
||
Description |
Receive Message4 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG4_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x2AC |
||
Physical address |
0x2010 C2AC |
Instance |
CAN_A_LO |
0x2010 D2AC |
CAN_B_LO |
||
0x2810 C2AC |
CAN_A_HI |
||
0x2810 D2AC |
CAN_B_HI |
||
Description |
Receive Message4 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG4_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x2B0 |
||
Physical address |
0x2010 C2B0 |
Instance |
CAN_A_LO |
0x2010 D2B0 |
CAN_B_LO |
||
0x2810 C2B0 |
CAN_A_HI |
||
0x2810 D2B0 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG4_AMR |
Receive Message4 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x2B4 |
||
Physical address |
0x2010 C2B4 |
Instance |
CAN_A_LO |
0x2010 D2B4 |
CAN_B_LO |
||
0x2810 C2B4 |
CAN_A_HI |
||
0x2810 D2B4 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG4_ACR |
Receive Message4 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x2B8 |
||
Physical address |
0x2010 C2B8 |
Instance |
CAN_A_LO |
0x2010 D2B8 |
CAN_B_LO |
||
0x2810 C2B8 |
CAN_A_HI |
||
0x2810 D2B8 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG4_AMR_DATA |
Receive Message4 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x2BC |
||
Physical address |
0x2010 C2BC |
Instance |
CAN_A_LO |
0x2010 D2BC |
CAN_B_LO |
||
0x2810 C2BC |
CAN_A_HI |
||
0x2810 D2BC |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG4_ACR_DATA |
Receive Message4 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x2C0 |
||
Physical address |
0x2010 C2C0 |
Instance |
CAN_A_LO |
0x2010 D2C0 |
CAN_B_LO |
||
0x2810 C2C0 |
CAN_A_HI |
||
0x2810 D2C0 |
CAN_B_HI |
||
Description |
Receive Message5 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x2C4 |
||
Physical address |
0x2010 C2C4 |
Instance |
CAN_A_LO |
0x2010 D2C4 |
CAN_B_LO |
||
0x2810 C2C4 |
CAN_A_HI |
||
0x2810 D2C4 |
CAN_B_HI |
||
Description |
Receive Message5 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x2C8 |
||
Physical address |
0x2010 C2C8 |
Instance |
CAN_A_LO |
0x2010 D2C8 |
CAN_B_LO |
||
0x2810 C2C8 |
CAN_A_HI |
||
0x2810 D2C8 |
CAN_B_HI |
||
Description |
Receive Message5 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG5_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x2CC |
||
Physical address |
0x2010 C2CC |
Instance |
CAN_A_LO |
0x2010 D2CC |
CAN_B_LO |
||
0x2810 C2CC |
CAN_A_HI |
||
0x2810 D2CC |
CAN_B_HI |
||
Description |
Receive Message5 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG5_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x2D0 |
||
Physical address |
0x2010 C2D0 |
Instance |
CAN_A_LO |
0x2010 D2D0 |
CAN_B_LO |
||
0x2810 C2D0 |
CAN_A_HI |
||
0x2810 D2D0 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG5_AMR |
Receive Message5 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x2D4 |
||
Physical address |
0x2010 C2D4 |
Instance |
CAN_A_LO |
0x2010 D2D4 |
CAN_B_LO |
||
0x2810 C2D4 |
CAN_A_HI |
||
0x2810 D2D4 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG5_ACR |
Receive Message5 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x2D8 |
||
Physical address |
0x2010 C2D8 |
Instance |
CAN_A_LO |
0x2010 D2D8 |
CAN_B_LO |
||
0x2810 C2D8 |
CAN_A_HI |
||
0x2810 D2D8 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG5_AMR_DATA |
Receive Message5 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x2DC |
||
Physical address |
0x2010 C2DC |
Instance |
CAN_A_LO |
0x2010 D2DC |
CAN_B_LO |
||
0x2810 C2DC |
CAN_A_HI |
||
0x2810 D2DC |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG5_ACR_DATA |
Receive Message5 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x2E0 |
||
Physical address |
0x2010 C2E0 |
Instance |
CAN_A_LO |
0x2010 D2E0 |
CAN_B_LO |
||
0x2810 C2E0 |
CAN_A_HI |
||
0x2810 D2E0 |
CAN_B_HI |
||
Description |
Receive Message6 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x2E4 |
||
Physical address |
0x2010 C2E4 |
Instance |
CAN_A_LO |
0x2010 D2E4 |
CAN_B_LO |
||
0x2810 C2E4 |
CAN_A_HI |
||
0x2810 D2E4 |
CAN_B_HI |
||
Description |
Receive Message6 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x2E8 |
||
Physical address |
0x2010 C2E8 |
Instance |
CAN_A_LO |
0x2010 D2E8 |
CAN_B_LO |
||
0x2810 C2E8 |
CAN_A_HI |
||
0x2810 D2E8 |
CAN_B_HI |
||
Description |
Receive Message6 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG6_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x2EC |
||
Physical address |
0x2010 C2EC |
Instance |
CAN_A_LO |
0x2010 D2EC |
CAN_B_LO |
||
0x2810 C2EC |
CAN_A_HI |
||
0x2810 D2EC |
CAN_B_HI |
||
Description |
Receive Message6 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG6_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x2F0 |
||
Physical address |
0x2010 C2F0 |
Instance |
CAN_A_LO |
0x2010 D2F0 |
CAN_B_LO |
||
0x2810 C2F0 |
CAN_A_HI |
||
0x2810 D2F0 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG6_AMR |
Receive Message6 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x2F4 |
||
Physical address |
0x2010 C2F4 |
Instance |
CAN_A_LO |
0x2010 D2F4 |
CAN_B_LO |
||
0x2810 C2F4 |
CAN_A_HI |
||
0x2810 D2F4 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG6_ACR |
Receive Message6 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x2F8 |
||
Physical address |
0x2010 C2F8 |
Instance |
CAN_A_LO |
0x2010 D2F8 |
CAN_B_LO |
||
0x2810 C2F8 |
CAN_A_HI |
||
0x2810 D2F8 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG6_AMR_DATA |
Receive Message6 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x2FC |
||
Physical address |
0x2010 C2FC |
Instance |
CAN_A_LO |
0x2010 D2FC |
CAN_B_LO |
||
0x2810 C2FC |
CAN_A_HI |
||
0x2810 D2FC |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG6_ACR_DATA |
Receive Message6 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x300 |
||
Physical address |
0x2010 C300 |
Instance |
CAN_A_LO |
0x2010 D300 |
CAN_B_LO |
||
0x2810 C300 |
CAN_A_HI |
||
0x2810 D300 |
CAN_B_HI |
||
Description |
Receive Message7 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x304 |
||
Physical address |
0x2010 C304 |
Instance |
CAN_A_LO |
0x2010 D304 |
CAN_B_LO |
||
0x2810 C304 |
CAN_A_HI |
||
0x2810 D304 |
CAN_B_HI |
||
Description |
Receive Message7 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x308 |
||
Physical address |
0x2010 C308 |
Instance |
CAN_A_LO |
0x2010 D308 |
CAN_B_LO |
||
0x2810 C308 |
CAN_A_HI |
||
0x2810 D308 |
CAN_B_HI |
||
Description |
Receive Message7 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG7_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x30C |
||
Physical address |
0x2010 C30C |
Instance |
CAN_A_LO |
0x2010 D30C |
CAN_B_LO |
||
0x2810 C30C |
CAN_A_HI |
||
0x2810 D30C |
CAN_B_HI |
||
Description |
Receive Message7 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG7_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x310 |
||
Physical address |
0x2010 C310 |
Instance |
CAN_A_LO |
0x2010 D310 |
CAN_B_LO |
||
0x2810 C310 |
CAN_A_HI |
||
0x2810 D310 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG7_AMR |
Receive Message7 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x314 |
||
Physical address |
0x2010 C314 |
Instance |
CAN_A_LO |
0x2010 D314 |
CAN_B_LO |
||
0x2810 C314 |
CAN_A_HI |
||
0x2810 D314 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG7_ACR |
Receive Message7 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x318 |
||
Physical address |
0x2010 C318 |
Instance |
CAN_A_LO |
0x2010 D318 |
CAN_B_LO |
||
0x2810 C318 |
CAN_A_HI |
||
0x2810 D318 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG7_AMR_DATA |
Receive Message7 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x31C |
||
Physical address |
0x2010 C31C |
Instance |
CAN_A_LO |
0x2010 D31C |
CAN_B_LO |
||
0x2810 C31C |
CAN_A_HI |
||
0x2810 D31C |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG7_ACR_DATA |
Receive Message7 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x320 |
||
Physical address |
0x2010 C320 |
Instance |
CAN_A_LO |
0x2010 D320 |
CAN_B_LO |
||
0x2810 C320 |
CAN_A_HI |
||
0x2810 D320 |
CAN_B_HI |
||
Description |
Receive Message8 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x324 |
||
Physical address |
0x2010 C324 |
Instance |
CAN_A_LO |
0x2010 D324 |
CAN_B_LO |
||
0x2810 C324 |
CAN_A_HI |
||
0x2810 D324 |
CAN_B_HI |
||
Description |
Receive Message8 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x328 |
||
Physical address |
0x2010 C328 |
Instance |
CAN_A_LO |
0x2010 D328 |
CAN_B_LO |
||
0x2810 C328 |
CAN_A_HI |
||
0x2810 D328 |
CAN_B_HI |
||
Description |
Receive Message8 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG8_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x32C |
||
Physical address |
0x2010 C32C |
Instance |
CAN_A_LO |
0x2010 D32C |
CAN_B_LO |
||
0x2810 C32C |
CAN_A_HI |
||
0x2810 D32C |
CAN_B_HI |
||
Description |
Receive Message8 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG8_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x330 |
||
Physical address |
0x2010 C330 |
Instance |
CAN_A_LO |
0x2010 D330 |
CAN_B_LO |
||
0x2810 C330 |
CAN_A_HI |
||
0x2810 D330 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG8_AMR |
Receive Message8 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x334 |
||
Physical address |
0x2010 C334 |
Instance |
CAN_A_LO |
0x2010 D334 |
CAN_B_LO |
||
0x2810 C334 |
CAN_A_HI |
||
0x2810 D334 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG8_ACR |
Receive Message8 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x338 |
||
Physical address |
0x2010 C338 |
Instance |
CAN_A_LO |
0x2010 D338 |
CAN_B_LO |
||
0x2810 C338 |
CAN_A_HI |
||
0x2810 D338 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG8_AMR_DATA |
Receive Message8 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x33C |
||
Physical address |
0x2010 C33C |
Instance |
CAN_A_LO |
0x2010 D33C |
CAN_B_LO |
||
0x2810 C33C |
CAN_A_HI |
||
0x2810 D33C |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG8_ACR_DATA |
Receive Message8 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x340 |
||
Physical address |
0x2010 C340 |
Instance |
CAN_A_LO |
0x2010 D340 |
CAN_B_LO |
||
0x2810 C340 |
CAN_A_HI |
||
0x2810 D340 |
CAN_B_HI |
||
Description |
Receive Message9 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x344 |
||
Physical address |
0x2010 C344 |
Instance |
CAN_A_LO |
0x2010 D344 |
CAN_B_LO |
||
0x2810 C344 |
CAN_A_HI |
||
0x2810 D344 |
CAN_B_HI |
||
Description |
Receive Message9 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x348 |
||
Physical address |
0x2010 C348 |
Instance |
CAN_A_LO |
0x2010 D348 |
CAN_B_LO |
||
0x2810 C348 |
CAN_A_HI |
||
0x2810 D348 |
CAN_B_HI |
||
Description |
Receive Message9 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG9_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x34C |
||
Physical address |
0x2010 C34C |
Instance |
CAN_A_LO |
0x2010 D34C |
CAN_B_LO |
||
0x2810 C34C |
CAN_A_HI |
||
0x2810 D34C |
CAN_B_HI |
||
Description |
Receive Message9 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG9_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x350 |
||
Physical address |
0x2010 C350 |
Instance |
CAN_A_LO |
0x2010 D350 |
CAN_B_LO |
||
0x2810 C350 |
CAN_A_HI |
||
0x2810 D350 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG9_AMR |
Receive Message9 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x354 |
||
Physical address |
0x2010 C354 |
Instance |
CAN_A_LO |
0x2010 D354 |
CAN_B_LO |
||
0x2810 C354 |
CAN_A_HI |
||
0x2810 D354 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG9_ACR |
Receive Message9 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x358 |
||
Physical address |
0x2010 C358 |
Instance |
CAN_A_LO |
0x2010 D358 |
CAN_B_LO |
||
0x2810 C358 |
CAN_A_HI |
||
0x2810 D358 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG9_AMR_DATA |
Receive Message9 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x35C |
||
Physical address |
0x2010 C35C |
Instance |
CAN_A_LO |
0x2010 D35C |
CAN_B_LO |
||
0x2810 C35C |
CAN_A_HI |
||
0x2810 D35C |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG9_ACR_DATA |
Receive Message9 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x360 |
||
Physical address |
0x2010 C360 |
Instance |
CAN_A_LO |
0x2010 D360 |
CAN_B_LO |
||
0x2810 C360 |
CAN_A_HI |
||
0x2810 D360 |
CAN_B_HI |
||
Description |
Receive Message10 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x364 |
||
Physical address |
0x2010 C364 |
Instance |
CAN_A_LO |
0x2010 D364 |
CAN_B_LO |
||
0x2810 C364 |
CAN_A_HI |
||
0x2810 D364 |
CAN_B_HI |
||
Description |
Receive Message10 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x368 |
||
Physical address |
0x2010 C368 |
Instance |
CAN_A_LO |
0x2010 D368 |
CAN_B_LO |
||
0x2810 C368 |
CAN_A_HI |
||
0x2810 D368 |
CAN_B_HI |
||
Description |
Receive Message10 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG10_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x36C |
||
Physical address |
0x2010 C36C |
Instance |
CAN_A_LO |
0x2010 D36C |
CAN_B_LO |
||
0x2810 C36C |
CAN_A_HI |
||
0x2810 D36C |
CAN_B_HI |
||
Description |
Receive Message10 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG10_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x370 |
||
Physical address |
0x2010 C370 |
Instance |
CAN_A_LO |
0x2010 D370 |
CAN_B_LO |
||
0x2810 C370 |
CAN_A_HI |
||
0x2810 D370 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG10_AMR |
Receive Message10 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x374 |
||
Physical address |
0x2010 C374 |
Instance |
CAN_A_LO |
0x2010 D374 |
CAN_B_LO |
||
0x2810 C374 |
CAN_A_HI |
||
0x2810 D374 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG10_ACR |
Receive Message10 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x378 |
||
Physical address |
0x2010 C378 |
Instance |
CAN_A_LO |
0x2010 D378 |
CAN_B_LO |
||
0x2810 C378 |
CAN_A_HI |
||
0x2810 D378 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG10_AMR_DATA |
Receive Message10 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x37C |
||
Physical address |
0x2010 C37C |
Instance |
CAN_A_LO |
0x2010 D37C |
CAN_B_LO |
||
0x2810 C37C |
CAN_A_HI |
||
0x2810 D37C |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG10_ACR_DATA |
Receive Message10 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x380 |
||
Physical address |
0x2010 C380 |
Instance |
CAN_A_LO |
0x2010 D380 |
CAN_B_LO |
||
0x2810 C380 |
CAN_A_HI |
||
0x2810 D380 |
CAN_B_HI |
||
Description |
Receive Message11 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x384 |
||
Physical address |
0x2010 C384 |
Instance |
CAN_A_LO |
0x2010 D384 |
CAN_B_LO |
||
0x2810 C384 |
CAN_A_HI |
||
0x2810 D384 |
CAN_B_HI |
||
Description |
Receive Message11 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x388 |
||
Physical address |
0x2010 C388 |
Instance |
CAN_A_LO |
0x2010 D388 |
CAN_B_LO |
||
0x2810 C388 |
CAN_A_HI |
||
0x2810 D388 |
CAN_B_HI |
||
Description |
Receive Message11 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG11_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x38C |
||
Physical address |
0x2010 C38C |
Instance |
CAN_A_LO |
0x2010 D38C |
CAN_B_LO |
||
0x2810 C38C |
CAN_A_HI |
||
0x2810 D38C |
CAN_B_HI |
||
Description |
Receive Message11 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG11_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x390 |
||
Physical address |
0x2010 C390 |
Instance |
CAN_A_LO |
0x2010 D390 |
CAN_B_LO |
||
0x2810 C390 |
CAN_A_HI |
||
0x2810 D390 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG11_AMR |
Receive Message11 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x394 |
||
Physical address |
0x2010 C394 |
Instance |
CAN_A_LO |
0x2010 D394 |
CAN_B_LO |
||
0x2810 C394 |
CAN_A_HI |
||
0x2810 D394 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG11_ACR |
Receive Message11 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x398 |
||
Physical address |
0x2010 C398 |
Instance |
CAN_A_LO |
0x2010 D398 |
CAN_B_LO |
||
0x2810 C398 |
CAN_A_HI |
||
0x2810 D398 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG11_AMR_DATA |
Receive Message11 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x39C |
||
Physical address |
0x2010 C39C |
Instance |
CAN_A_LO |
0x2010 D39C |
CAN_B_LO |
||
0x2810 C39C |
CAN_A_HI |
||
0x2810 D39C |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG11_ACR_DATA |
Receive Message11 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x3A0 |
||
Physical address |
0x2010 C3A0 |
Instance |
CAN_A_LO |
0x2010 D3A0 |
CAN_B_LO |
||
0x2810 C3A0 |
CAN_A_HI |
||
0x2810 D3A0 |
CAN_B_HI |
||
Description |
Receive Message12 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x3A4 |
||
Physical address |
0x2010 C3A4 |
Instance |
CAN_A_LO |
0x2010 D3A4 |
CAN_B_LO |
||
0x2810 C3A4 |
CAN_A_HI |
||
0x2810 D3A4 |
CAN_B_HI |
||
Description |
Receive Message12 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x3A8 |
||
Physical address |
0x2010 C3A8 |
Instance |
CAN_A_LO |
0x2010 D3A8 |
CAN_B_LO |
||
0x2810 C3A8 |
CAN_A_HI |
||
0x2810 D3A8 |
CAN_B_HI |
||
Description |
Receive Message12 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG12_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x3AC |
||
Physical address |
0x2010 C3AC |
Instance |
CAN_A_LO |
0x2010 D3AC |
CAN_B_LO |
||
0x2810 C3AC |
CAN_A_HI |
||
0x2810 D3AC |
CAN_B_HI |
||
Description |
Receive Message12 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG12_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x3B0 |
||
Physical address |
0x2010 C3B0 |
Instance |
CAN_A_LO |
0x2010 D3B0 |
CAN_B_LO |
||
0x2810 C3B0 |
CAN_A_HI |
||
0x2810 D3B0 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG12_AMR |
Receive Message12 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x3B4 |
||
Physical address |
0x2010 C3B4 |
Instance |
CAN_A_LO |
0x2010 D3B4 |
CAN_B_LO |
||
0x2810 C3B4 |
CAN_A_HI |
||
0x2810 D3B4 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG12_ACR |
Receive Message12 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x3B8 |
||
Physical address |
0x2010 C3B8 |
Instance |
CAN_A_LO |
0x2010 D3B8 |
CAN_B_LO |
||
0x2810 C3B8 |
CAN_A_HI |
||
0x2810 D3B8 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG12_AMR_DATA |
Receive Message12 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x3BC |
||
Physical address |
0x2010 C3BC |
Instance |
CAN_A_LO |
0x2010 D3BC |
CAN_B_LO |
||
0x2810 C3BC |
CAN_A_HI |
||
0x2810 D3BC |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG12_ACR_DATA |
Receive Message12 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x3C0 |
||
Physical address |
0x2010 C3C0 |
Instance |
CAN_A_LO |
0x2010 D3C0 |
CAN_B_LO |
||
0x2810 C3C0 |
CAN_A_HI |
||
0x2810 D3C0 |
CAN_B_HI |
||
Description |
Receive Message13 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x3C4 |
||
Physical address |
0x2010 C3C4 |
Instance |
CAN_A_LO |
0x2010 D3C4 |
CAN_B_LO |
||
0x2810 C3C4 |
CAN_A_HI |
||
0x2810 D3C4 |
CAN_B_HI |
||
Description |
Receive Message13 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x3C8 |
||
Physical address |
0x2010 C3C8 |
Instance |
CAN_A_LO |
0x2010 D3C8 |
CAN_B_LO |
||
0x2810 C3C8 |
CAN_A_HI |
||
0x2810 D3C8 |
CAN_B_HI |
||
Description |
Receive Message13 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG13_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x3CC |
||
Physical address |
0x2010 C3CC |
Instance |
CAN_A_LO |
0x2010 D3CC |
CAN_B_LO |
||
0x2810 C3CC |
CAN_A_HI |
||
0x2810 D3CC |
CAN_B_HI |
||
Description |
Receive Message13 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG13_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x3D0 |
||
Physical address |
0x2010 C3D0 |
Instance |
CAN_A_LO |
0x2010 D3D0 |
CAN_B_LO |
||
0x2810 C3D0 |
CAN_A_HI |
||
0x2810 D3D0 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG13_AMR |
Receive Message13 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x3D4 |
||
Physical address |
0x2010 C3D4 |
Instance |
CAN_A_LO |
0x2010 D3D4 |
CAN_B_LO |
||
0x2810 C3D4 |
CAN_A_HI |
||
0x2810 D3D4 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG13_ACR |
Receive Message13 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x3D8 |
||
Physical address |
0x2010 C3D8 |
Instance |
CAN_A_LO |
0x2010 D3D8 |
CAN_B_LO |
||
0x2810 C3D8 |
CAN_A_HI |
||
0x2810 D3D8 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG13_AMR_DATA |
Receive Message13 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x3DC |
||
Physical address |
0x2010 C3DC |
Instance |
CAN_A_LO |
0x2010 D3DC |
CAN_B_LO |
||
0x2810 C3DC |
CAN_A_HI |
||
0x2810 D3DC |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG13_ACR_DATA |
Receive Message13 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x3E0 |
||
Physical address |
0x2010 C3E0 |
Instance |
CAN_A_LO |
0x2010 D3E0 |
CAN_B_LO |
||
0x2810 C3E0 |
CAN_A_HI |
||
0x2810 D3E0 |
CAN_B_HI |
||
Description |
Receive Message14 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x3E4 |
||
Physical address |
0x2010 C3E4 |
Instance |
CAN_A_LO |
0x2010 D3E4 |
CAN_B_LO |
||
0x2810 C3E4 |
CAN_A_HI |
||
0x2810 D3E4 |
CAN_B_HI |
||
Description |
Receive Message14 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x3E8 |
||
Physical address |
0x2010 C3E8 |
Instance |
CAN_A_LO |
0x2010 D3E8 |
CAN_B_LO |
||
0x2810 C3E8 |
CAN_A_HI |
||
0x2810 D3E8 |
CAN_B_HI |
||
Description |
Receive Message14 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG14_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x3EC |
||
Physical address |
0x2010 C3EC |
Instance |
CAN_A_LO |
0x2010 D3EC |
CAN_B_LO |
||
0x2810 C3EC |
CAN_A_HI |
||
0x2810 D3EC |
CAN_B_HI |
||
Description |
Receive Message14 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG14_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x3F0 |
||
Physical address |
0x2010 C3F0 |
Instance |
CAN_A_LO |
0x2010 D3F0 |
CAN_B_LO |
||
0x2810 C3F0 |
CAN_A_HI |
||
0x2810 D3F0 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG14_AMR |
Receive Message14 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x3F4 |
||
Physical address |
0x2010 C3F4 |
Instance |
CAN_A_LO |
0x2010 D3F4 |
CAN_B_LO |
||
0x2810 C3F4 |
CAN_A_HI |
||
0x2810 D3F4 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG14_ACR |
Receive Message14 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x3F8 |
||
Physical address |
0x2010 C3F8 |
Instance |
CAN_A_LO |
0x2010 D3F8 |
CAN_B_LO |
||
0x2810 C3F8 |
CAN_A_HI |
||
0x2810 D3F8 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG14_AMR_DATA |
Receive Message14 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x3FC |
||
Physical address |
0x2010 C3FC |
Instance |
CAN_A_LO |
0x2010 D3FC |
CAN_B_LO |
||
0x2810 C3FC |
CAN_A_HI |
||
0x2810 D3FC |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG14_ACR_DATA |
Receive Message14 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x400 |
||
Physical address |
0x2010 C400 |
Instance |
CAN_A_LO |
0x2010 D400 |
CAN_B_LO |
||
0x2810 C400 |
CAN_A_HI |
||
0x2810 D400 |
CAN_B_HI |
||
Description |
Receive Message15 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x404 |
||
Physical address |
0x2010 C404 |
Instance |
CAN_A_LO |
0x2010 D404 |
CAN_B_LO |
||
0x2810 C404 |
CAN_A_HI |
||
0x2810 D404 |
CAN_B_HI |
||
Description |
Receive Message15 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x408 |
||
Physical address |
0x2010 C408 |
Instance |
CAN_A_LO |
0x2010 D408 |
CAN_B_LO |
||
0x2810 C408 |
CAN_A_HI |
||
0x2810 D408 |
CAN_B_HI |
||
Description |
Receive Message15 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG15_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x40C |
||
Physical address |
0x2010 C40C |
Instance |
CAN_A_LO |
0x2010 D40C |
CAN_B_LO |
||
0x2810 C40C |
CAN_A_HI |
||
0x2810 D40C |
CAN_B_HI |
||
Description |
Receive Message15 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG15_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x410 |
||
Physical address |
0x2010 C410 |
Instance |
CAN_A_LO |
0x2010 D410 |
CAN_B_LO |
||
0x2810 C410 |
CAN_A_HI |
||
0x2810 D410 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG15_AMR |
Receive Message15 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x414 |
||
Physical address |
0x2010 C414 |
Instance |
CAN_A_LO |
0x2010 D414 |
CAN_B_LO |
||
0x2810 C414 |
CAN_A_HI |
||
0x2810 D414 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG15_ACR |
Receive Message15 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x418 |
||
Physical address |
0x2010 C418 |
Instance |
CAN_A_LO |
0x2010 D418 |
CAN_B_LO |
||
0x2810 C418 |
CAN_A_HI |
||
0x2810 D418 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG15_AMR_DATA |
Receive Message15 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x41C |
||
Physical address |
0x2010 C41C |
Instance |
CAN_A_LO |
0x2010 D41C |
CAN_B_LO |
||
0x2810 C41C |
CAN_A_HI |
||
0x2810 D41C |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG15_ACR_DATA |
Receive Message15 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x420 |
||
Physical address |
0x2010 C420 |
Instance |
CAN_A_LO |
0x2010 D420 |
CAN_B_LO |
||
0x2810 C420 |
CAN_A_HI |
||
0x2810 D420 |
CAN_B_HI |
||
Description |
Receive Message16 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x424 |
||
Physical address |
0x2010 C424 |
Instance |
CAN_A_LO |
0x2010 D424 |
CAN_B_LO |
||
0x2810 C424 |
CAN_A_HI |
||
0x2810 D424 |
CAN_B_HI |
||
Description |
Receive Message16 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x428 |
||
Physical address |
0x2010 C428 |
Instance |
CAN_A_LO |
0x2010 D428 |
CAN_B_LO |
||
0x2810 C428 |
CAN_A_HI |
||
0x2810 D428 |
CAN_B_HI |
||
Description |
Receive Message16 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG16_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x42C |
||
Physical address |
0x2010 C42C |
Instance |
CAN_A_LO |
0x2010 D42C |
CAN_B_LO |
||
0x2810 C42C |
CAN_A_HI |
||
0x2810 D42C |
CAN_B_HI |
||
Description |
Receive Message16 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG16_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x430 |
||
Physical address |
0x2010 C430 |
Instance |
CAN_A_LO |
0x2010 D430 |
CAN_B_LO |
||
0x2810 C430 |
CAN_A_HI |
||
0x2810 D430 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG16_AMR |
Receive Message16 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x434 |
||
Physical address |
0x2010 C434 |
Instance |
CAN_A_LO |
0x2010 D434 |
CAN_B_LO |
||
0x2810 C434 |
CAN_A_HI |
||
0x2810 D434 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG16_ACR |
Receive Message16 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x438 |
||
Physical address |
0x2010 C438 |
Instance |
CAN_A_LO |
0x2010 D438 |
CAN_B_LO |
||
0x2810 C438 |
CAN_A_HI |
||
0x2810 D438 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG16_AMR_DATA |
Receive Message16 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x43C |
||
Physical address |
0x2010 C43C |
Instance |
CAN_A_LO |
0x2010 D43C |
CAN_B_LO |
||
0x2810 C43C |
CAN_A_HI |
||
0x2810 D43C |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG16_ACR_DATA |
Receive Message16 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x440 |
||
Physical address |
0x2010 C440 |
Instance |
CAN_A_LO |
0x2010 D440 |
CAN_B_LO |
||
0x2810 C440 |
CAN_A_HI |
||
0x2810 D440 |
CAN_B_HI |
||
Description |
Receive Message17 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x444 |
||
Physical address |
0x2010 C444 |
Instance |
CAN_A_LO |
0x2010 D444 |
CAN_B_LO |
||
0x2810 C444 |
CAN_A_HI |
||
0x2810 D444 |
CAN_B_HI |
||
Description |
Receive Message17 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x448 |
||
Physical address |
0x2010 C448 |
Instance |
CAN_A_LO |
0x2010 D448 |
CAN_B_LO |
||
0x2810 C448 |
CAN_A_HI |
||
0x2810 D448 |
CAN_B_HI |
||
Description |
Receive Message17 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG17_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x44C |
||
Physical address |
0x2010 C44C |
Instance |
CAN_A_LO |
0x2010 D44C |
CAN_B_LO |
||
0x2810 C44C |
CAN_A_HI |
||
0x2810 D44C |
CAN_B_HI |
||
Description |
Receive Message17 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG17_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x450 |
||
Physical address |
0x2010 C450 |
Instance |
CAN_A_LO |
0x2010 D450 |
CAN_B_LO |
||
0x2810 C450 |
CAN_A_HI |
||
0x2810 D450 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG17_AMR |
Receive Message17 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x454 |
||
Physical address |
0x2010 C454 |
Instance |
CAN_A_LO |
0x2010 D454 |
CAN_B_LO |
||
0x2810 C454 |
CAN_A_HI |
||
0x2810 D454 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG17_ACR |
Receive Message17 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x458 |
||
Physical address |
0x2010 C458 |
Instance |
CAN_A_LO |
0x2010 D458 |
CAN_B_LO |
||
0x2810 C458 |
CAN_A_HI |
||
0x2810 D458 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG17_AMR_DATA |
Receive Message17 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x45C |
||
Physical address |
0x2010 C45C |
Instance |
CAN_A_LO |
0x2010 D45C |
CAN_B_LO |
||
0x2810 C45C |
CAN_A_HI |
||
0x2810 D45C |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG17_ACR_DATA |
Receive Message17 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x460 |
||
Physical address |
0x2010 C460 |
Instance |
CAN_A_LO |
0x2010 D460 |
CAN_B_LO |
||
0x2810 C460 |
CAN_A_HI |
||
0x2810 D460 |
CAN_B_HI |
||
Description |
Receive Message18 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x464 |
||
Physical address |
0x2010 C464 |
Instance |
CAN_A_LO |
0x2010 D464 |
CAN_B_LO |
||
0x2810 C464 |
CAN_A_HI |
||
0x2810 D464 |
CAN_B_HI |
||
Description |
Receive Message18 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x468 |
||
Physical address |
0x2010 C468 |
Instance |
CAN_A_LO |
0x2010 D468 |
CAN_B_LO |
||
0x2810 C468 |
CAN_A_HI |
||
0x2810 D468 |
CAN_B_HI |
||
Description |
Receive Message18 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG18_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x46C |
||
Physical address |
0x2010 C46C |
Instance |
CAN_A_LO |
0x2010 D46C |
CAN_B_LO |
||
0x2810 C46C |
CAN_A_HI |
||
0x2810 D46C |
CAN_B_HI |
||
Description |
Receive Message18 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG18_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x470 |
||
Physical address |
0x2010 C470 |
Instance |
CAN_A_LO |
0x2010 D470 |
CAN_B_LO |
||
0x2810 C470 |
CAN_A_HI |
||
0x2810 D470 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG18_AMR |
Receive Message18 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x474 |
||
Physical address |
0x2010 C474 |
Instance |
CAN_A_LO |
0x2010 D474 |
CAN_B_LO |
||
0x2810 C474 |
CAN_A_HI |
||
0x2810 D474 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG18_ACR |
Receive Message18 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x478 |
||
Physical address |
0x2010 C478 |
Instance |
CAN_A_LO |
0x2010 D478 |
CAN_B_LO |
||
0x2810 C478 |
CAN_A_HI |
||
0x2810 D478 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG18_AMR_DATA |
Receive Message18 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x47C |
||
Physical address |
0x2010 C47C |
Instance |
CAN_A_LO |
0x2010 D47C |
CAN_B_LO |
||
0x2810 C47C |
CAN_A_HI |
||
0x2810 D47C |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG18_ACR_DATA |
Receive Message18 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x480 |
||
Physical address |
0x2010 C480 |
Instance |
CAN_A_LO |
0x2010 D480 |
CAN_B_LO |
||
0x2810 C480 |
CAN_A_HI |
||
0x2810 D480 |
CAN_B_HI |
||
Description |
Receive Message19 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x484 |
||
Physical address |
0x2010 C484 |
Instance |
CAN_A_LO |
0x2010 D484 |
CAN_B_LO |
||
0x2810 C484 |
CAN_A_HI |
||
0x2810 D484 |
CAN_B_HI |
||
Description |
Receive Message19 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x488 |
||
Physical address |
0x2010 C488 |
Instance |
CAN_A_LO |
0x2010 D488 |
CAN_B_LO |
||
0x2810 C488 |
CAN_A_HI |
||
0x2810 D488 |
CAN_B_HI |
||
Description |
Receive Message19 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG19_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x48C |
||
Physical address |
0x2010 C48C |
Instance |
CAN_A_LO |
0x2010 D48C |
CAN_B_LO |
||
0x2810 C48C |
CAN_A_HI |
||
0x2810 D48C |
CAN_B_HI |
||
Description |
Receive Message19 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG19_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x490 |
||
Physical address |
0x2010 C490 |
Instance |
CAN_A_LO |
0x2010 D490 |
CAN_B_LO |
||
0x2810 C490 |
CAN_A_HI |
||
0x2810 D490 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG19_AMR |
Receive Message19 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x494 |
||
Physical address |
0x2010 C494 |
Instance |
CAN_A_LO |
0x2010 D494 |
CAN_B_LO |
||
0x2810 C494 |
CAN_A_HI |
||
0x2810 D494 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG19_ACR |
Receive Message19 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x498 |
||
Physical address |
0x2010 C498 |
Instance |
CAN_A_LO |
0x2010 D498 |
CAN_B_LO |
||
0x2810 C498 |
CAN_A_HI |
||
0x2810 D498 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG19_AMR_DATA |
Receive Message19 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x49C |
||
Physical address |
0x2010 C49C |
Instance |
CAN_A_LO |
0x2010 D49C |
CAN_B_LO |
||
0x2810 C49C |
CAN_A_HI |
||
0x2810 D49C |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG19_ACR_DATA |
Receive Message19 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x4A0 |
||
Physical address |
0x2010 C4A0 |
Instance |
CAN_A_LO |
0x2010 D4A0 |
CAN_B_LO |
||
0x2810 C4A0 |
CAN_A_HI |
||
0x2810 D4A0 |
CAN_B_HI |
||
Description |
Receive Message20 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x4A4 |
||
Physical address |
0x2010 C4A4 |
Instance |
CAN_A_LO |
0x2010 D4A4 |
CAN_B_LO |
||
0x2810 C4A4 |
CAN_A_HI |
||
0x2810 D4A4 |
CAN_B_HI |
||
Description |
Receive Message20 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x4A8 |
||
Physical address |
0x2010 C4A8 |
Instance |
CAN_A_LO |
0x2010 D4A8 |
CAN_B_LO |
||
0x2810 C4A8 |
CAN_A_HI |
||
0x2810 D4A8 |
CAN_B_HI |
||
Description |
Receive Message20 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG20_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x4AC |
||
Physical address |
0x2010 C4AC |
Instance |
CAN_A_LO |
0x2010 D4AC |
CAN_B_LO |
||
0x2810 C4AC |
CAN_A_HI |
||
0x2810 D4AC |
CAN_B_HI |
||
Description |
Receive Message20 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG20_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x4B0 |
||
Physical address |
0x2010 C4B0 |
Instance |
CAN_A_LO |
0x2010 D4B0 |
CAN_B_LO |
||
0x2810 C4B0 |
CAN_A_HI |
||
0x2810 D4B0 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG20_AMR |
Receive Message20 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x4B4 |
||
Physical address |
0x2010 C4B4 |
Instance |
CAN_A_LO |
0x2010 D4B4 |
CAN_B_LO |
||
0x2810 C4B4 |
CAN_A_HI |
||
0x2810 D4B4 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG20_ACR |
Receive Message20 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x4B8 |
||
Physical address |
0x2010 C4B8 |
Instance |
CAN_A_LO |
0x2010 D4B8 |
CAN_B_LO |
||
0x2810 C4B8 |
CAN_A_HI |
||
0x2810 D4B8 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG20_AMR_DATA |
Receive Message20 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x4BC |
||
Physical address |
0x2010 C4BC |
Instance |
CAN_A_LO |
0x2010 D4BC |
CAN_B_LO |
||
0x2810 C4BC |
CAN_A_HI |
||
0x2810 D4BC |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG20_ACR_DATA |
Receive Message20 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x4C0 |
||
Physical address |
0x2010 C4C0 |
Instance |
CAN_A_LO |
0x2010 D4C0 |
CAN_B_LO |
||
0x2810 C4C0 |
CAN_A_HI |
||
0x2810 D4C0 |
CAN_B_HI |
||
Description |
Receive Message21 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x4C4 |
||
Physical address |
0x2010 C4C4 |
Instance |
CAN_A_LO |
0x2010 D4C4 |
CAN_B_LO |
||
0x2810 C4C4 |
CAN_A_HI |
||
0x2810 D4C4 |
CAN_B_HI |
||
Description |
Receive Message21 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x4C8 |
||
Physical address |
0x2010 C4C8 |
Instance |
CAN_A_LO |
0x2010 D4C8 |
CAN_B_LO |
||
0x2810 C4C8 |
CAN_A_HI |
||
0x2810 D4C8 |
CAN_B_HI |
||
Description |
Receive Message21 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG21_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x4CC |
||
Physical address |
0x2010 C4CC |
Instance |
CAN_A_LO |
0x2010 D4CC |
CAN_B_LO |
||
0x2810 C4CC |
CAN_A_HI |
||
0x2810 D4CC |
CAN_B_HI |
||
Description |
Receive Message21 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG21_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x4D0 |
||
Physical address |
0x2010 C4D0 |
Instance |
CAN_A_LO |
0x2010 D4D0 |
CAN_B_LO |
||
0x2810 C4D0 |
CAN_A_HI |
||
0x2810 D4D0 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG21_AMR |
Receive Message21 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x4D4 |
||
Physical address |
0x2010 C4D4 |
Instance |
CAN_A_LO |
0x2010 D4D4 |
CAN_B_LO |
||
0x2810 C4D4 |
CAN_A_HI |
||
0x2810 D4D4 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG21_ACR |
Receive Message21 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x4D8 |
||
Physical address |
0x2010 C4D8 |
Instance |
CAN_A_LO |
0x2010 D4D8 |
CAN_B_LO |
||
0x2810 C4D8 |
CAN_A_HI |
||
0x2810 D4D8 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG21_AMR_DATA |
Receive Message21 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x4DC |
||
Physical address |
0x2010 C4DC |
Instance |
CAN_A_LO |
0x2010 D4DC |
CAN_B_LO |
||
0x2810 C4DC |
CAN_A_HI |
||
0x2810 D4DC |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG21_ACR_DATA |
Receive Message21 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x4E0 |
||
Physical address |
0x2010 C4E0 |
Instance |
CAN_A_LO |
0x2010 D4E0 |
CAN_B_LO |
||
0x2810 C4E0 |
CAN_A_HI |
||
0x2810 D4E0 |
CAN_B_HI |
||
Description |
Receive Message22 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x4E4 |
||
Physical address |
0x2010 C4E4 |
Instance |
CAN_A_LO |
0x2010 D4E4 |
CAN_B_LO |
||
0x2810 C4E4 |
CAN_A_HI |
||
0x2810 D4E4 |
CAN_B_HI |
||
Description |
Receive Message22 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x4E8 |
||
Physical address |
0x2010 C4E8 |
Instance |
CAN_A_LO |
0x2010 D4E8 |
CAN_B_LO |
||
0x2810 C4E8 |
CAN_A_HI |
||
0x2810 D4E8 |
CAN_B_HI |
||
Description |
Receive Message22 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG22_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x4EC |
||
Physical address |
0x2010 C4EC |
Instance |
CAN_A_LO |
0x2010 D4EC |
CAN_B_LO |
||
0x2810 C4EC |
CAN_A_HI |
||
0x2810 D4EC |
CAN_B_HI |
||
Description |
Receive Message22 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG22_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x4F0 |
||
Physical address |
0x2010 C4F0 |
Instance |
CAN_A_LO |
0x2010 D4F0 |
CAN_B_LO |
||
0x2810 C4F0 |
CAN_A_HI |
||
0x2810 D4F0 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG22_AMR |
Receive Message22 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x4F4 |
||
Physical address |
0x2010 C4F4 |
Instance |
CAN_A_LO |
0x2010 D4F4 |
CAN_B_LO |
||
0x2810 C4F4 |
CAN_A_HI |
||
0x2810 D4F4 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG22_ACR |
Receive Message22 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x4F8 |
||
Physical address |
0x2010 C4F8 |
Instance |
CAN_A_LO |
0x2010 D4F8 |
CAN_B_LO |
||
0x2810 C4F8 |
CAN_A_HI |
||
0x2810 D4F8 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG22_AMR_DATA |
Receive Message22 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x4FC |
||
Physical address |
0x2010 C4FC |
Instance |
CAN_A_LO |
0x2010 D4FC |
CAN_B_LO |
||
0x2810 C4FC |
CAN_A_HI |
||
0x2810 D4FC |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG22_ACR_DATA |
Receive Message22 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x500 |
||
Physical address |
0x2010 C500 |
Instance |
CAN_A_LO |
0x2010 D500 |
CAN_B_LO |
||
0x2810 C500 |
CAN_A_HI |
||
0x2810 D500 |
CAN_B_HI |
||
Description |
Receive Message23 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x504 |
||
Physical address |
0x2010 C504 |
Instance |
CAN_A_LO |
0x2010 D504 |
CAN_B_LO |
||
0x2810 C504 |
CAN_A_HI |
||
0x2810 D504 |
CAN_B_HI |
||
Description |
Receive Message23 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x508 |
||
Physical address |
0x2010 C508 |
Instance |
CAN_A_LO |
0x2010 D508 |
CAN_B_LO |
||
0x2810 C508 |
CAN_A_HI |
||
0x2810 D508 |
CAN_B_HI |
||
Description |
Receive Message23 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG23_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x50C |
||
Physical address |
0x2010 C50C |
Instance |
CAN_A_LO |
0x2010 D50C |
CAN_B_LO |
||
0x2810 C50C |
CAN_A_HI |
||
0x2810 D50C |
CAN_B_HI |
||
Description |
Receive Message23 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG23_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x510 |
||
Physical address |
0x2010 C510 |
Instance |
CAN_A_LO |
0x2010 D510 |
CAN_B_LO |
||
0x2810 C510 |
CAN_A_HI |
||
0x2810 D510 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG23_AMR |
Receive Message23 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x514 |
||
Physical address |
0x2010 C514 |
Instance |
CAN_A_LO |
0x2010 D514 |
CAN_B_LO |
||
0x2810 C514 |
CAN_A_HI |
||
0x2810 D514 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG23_ACR |
Receive Message23 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x518 |
||
Physical address |
0x2010 C518 |
Instance |
CAN_A_LO |
0x2010 D518 |
CAN_B_LO |
||
0x2810 C518 |
CAN_A_HI |
||
0x2810 D518 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG23_AMR_DATA |
Receive Message23 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x51C |
||
Physical address |
0x2010 C51C |
Instance |
CAN_A_LO |
0x2010 D51C |
CAN_B_LO |
||
0x2810 C51C |
CAN_A_HI |
||
0x2810 D51C |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG23_ACR_DATA |
Receive Message23 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x520 |
||
Physical address |
0x2010 C520 |
Instance |
CAN_A_LO |
0x2010 D520 |
CAN_B_LO |
||
0x2810 C520 |
CAN_A_HI |
||
0x2810 D520 |
CAN_B_HI |
||
Description |
Receive Message24 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x524 |
||
Physical address |
0x2010 C524 |
Instance |
CAN_A_LO |
0x2010 D524 |
CAN_B_LO |
||
0x2810 C524 |
CAN_A_HI |
||
0x2810 D524 |
CAN_B_HI |
||
Description |
Receive Message24 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x528 |
||
Physical address |
0x2010 C528 |
Instance |
CAN_A_LO |
0x2010 D528 |
CAN_B_LO |
||
0x2810 C528 |
CAN_A_HI |
||
0x2810 D528 |
CAN_B_HI |
||
Description |
Receive Message24 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG24_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x52C |
||
Physical address |
0x2010 C52C |
Instance |
CAN_A_LO |
0x2010 D52C |
CAN_B_LO |
||
0x2810 C52C |
CAN_A_HI |
||
0x2810 D52C |
CAN_B_HI |
||
Description |
Receive Message24 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG24_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x530 |
||
Physical address |
0x2010 C530 |
Instance |
CAN_A_LO |
0x2010 D530 |
CAN_B_LO |
||
0x2810 C530 |
CAN_A_HI |
||
0x2810 D530 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG24_AMR |
Receive Message24 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x534 |
||
Physical address |
0x2010 C534 |
Instance |
CAN_A_LO |
0x2010 D534 |
CAN_B_LO |
||
0x2810 C534 |
CAN_A_HI |
||
0x2810 D534 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG24_ACR |
Receive Message24 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x538 |
||
Physical address |
0x2010 C538 |
Instance |
CAN_A_LO |
0x2010 D538 |
CAN_B_LO |
||
0x2810 C538 |
CAN_A_HI |
||
0x2810 D538 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG24_AMR_DATA |
Receive Message24 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x53C |
||
Physical address |
0x2010 C53C |
Instance |
CAN_A_LO |
0x2010 D53C |
CAN_B_LO |
||
0x2810 C53C |
CAN_A_HI |
||
0x2810 D53C |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG24_ACR_DATA |
Receive Message24 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x540 |
||
Physical address |
0x2010 C540 |
Instance |
CAN_A_LO |
0x2010 D540 |
CAN_B_LO |
||
0x2810 C540 |
CAN_A_HI |
||
0x2810 D540 |
CAN_B_HI |
||
Description |
Receive Message25 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x544 |
||
Physical address |
0x2010 C544 |
Instance |
CAN_A_LO |
0x2010 D544 |
CAN_B_LO |
||
0x2810 C544 |
CAN_A_HI |
||
0x2810 D544 |
CAN_B_HI |
||
Description |
Receive Message25 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x548 |
||
Physical address |
0x2010 C548 |
Instance |
CAN_A_LO |
0x2010 D548 |
CAN_B_LO |
||
0x2810 C548 |
CAN_A_HI |
||
0x2810 D548 |
CAN_B_HI |
||
Description |
Receive Message25 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG25_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x54C |
||
Physical address |
0x2010 C54C |
Instance |
CAN_A_LO |
0x2010 D54C |
CAN_B_LO |
||
0x2810 C54C |
CAN_A_HI |
||
0x2810 D54C |
CAN_B_HI |
||
Description |
Receive Message25 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG25_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x550 |
||
Physical address |
0x2010 C550 |
Instance |
CAN_A_LO |
0x2010 D550 |
CAN_B_LO |
||
0x2810 C550 |
CAN_A_HI |
||
0x2810 D550 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG25_AMR |
Receive Message25 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x554 |
||
Physical address |
0x2010 C554 |
Instance |
CAN_A_LO |
0x2010 D554 |
CAN_B_LO |
||
0x2810 C554 |
CAN_A_HI |
||
0x2810 D554 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG25_ACR |
Receive Message25 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x558 |
||
Physical address |
0x2010 C558 |
Instance |
CAN_A_LO |
0x2010 D558 |
CAN_B_LO |
||
0x2810 C558 |
CAN_A_HI |
||
0x2810 D558 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG25_AMR_DATA |
Receive Message25 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x55C |
||
Physical address |
0x2010 C55C |
Instance |
CAN_A_LO |
0x2010 D55C |
CAN_B_LO |
||
0x2810 C55C |
CAN_A_HI |
||
0x2810 D55C |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG25_ACR_DATA |
Receive Message25 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x560 |
||
Physical address |
0x2010 C560 |
Instance |
CAN_A_LO |
0x2010 D560 |
CAN_B_LO |
||
0x2810 C560 |
CAN_A_HI |
||
0x2810 D560 |
CAN_B_HI |
||
Description |
Receive Message26 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x564 |
||
Physical address |
0x2010 C564 |
Instance |
CAN_A_LO |
0x2010 D564 |
CAN_B_LO |
||
0x2810 C564 |
CAN_A_HI |
||
0x2810 D564 |
CAN_B_HI |
||
Description |
Receive Message26 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x568 |
||
Physical address |
0x2010 C568 |
Instance |
CAN_A_LO |
0x2010 D568 |
CAN_B_LO |
||
0x2810 C568 |
CAN_A_HI |
||
0x2810 D568 |
CAN_B_HI |
||
Description |
Receive Message26 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG26_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x56C |
||
Physical address |
0x2010 C56C |
Instance |
CAN_A_LO |
0x2010 D56C |
CAN_B_LO |
||
0x2810 C56C |
CAN_A_HI |
||
0x2810 D56C |
CAN_B_HI |
||
Description |
Receive Message26 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG26_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x570 |
||
Physical address |
0x2010 C570 |
Instance |
CAN_A_LO |
0x2010 D570 |
CAN_B_LO |
||
0x2810 C570 |
CAN_A_HI |
||
0x2810 D570 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG26_AMR |
Receive Message26 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x574 |
||
Physical address |
0x2010 C574 |
Instance |
CAN_A_LO |
0x2010 D574 |
CAN_B_LO |
||
0x2810 C574 |
CAN_A_HI |
||
0x2810 D574 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG26_ACR |
Receive Message26 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x578 |
||
Physical address |
0x2010 C578 |
Instance |
CAN_A_LO |
0x2010 D578 |
CAN_B_LO |
||
0x2810 C578 |
CAN_A_HI |
||
0x2810 D578 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG26_AMR_DATA |
Receive Message26 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x57C |
||
Physical address |
0x2010 C57C |
Instance |
CAN_A_LO |
0x2010 D57C |
CAN_B_LO |
||
0x2810 C57C |
CAN_A_HI |
||
0x2810 D57C |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG26_ACR_DATA |
Receive Message26 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x580 |
||
Physical address |
0x2010 C580 |
Instance |
CAN_A_LO |
0x2010 D580 |
CAN_B_LO |
||
0x2810 C580 |
CAN_A_HI |
||
0x2810 D580 |
CAN_B_HI |
||
Description |
Receive Message27 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x584 |
||
Physical address |
0x2010 C584 |
Instance |
CAN_A_LO |
0x2010 D584 |
CAN_B_LO |
||
0x2810 C584 |
CAN_A_HI |
||
0x2810 D584 |
CAN_B_HI |
||
Description |
Receive Message27 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x588 |
||
Physical address |
0x2010 C588 |
Instance |
CAN_A_LO |
0x2010 D588 |
CAN_B_LO |
||
0x2810 C588 |
CAN_A_HI |
||
0x2810 D588 |
CAN_B_HI |
||
Description |
Receive Message27 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG27_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x58C |
||
Physical address |
0x2010 C58C |
Instance |
CAN_A_LO |
0x2010 D58C |
CAN_B_LO |
||
0x2810 C58C |
CAN_A_HI |
||
0x2810 D58C |
CAN_B_HI |
||
Description |
Receive Message27 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG27_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x590 |
||
Physical address |
0x2010 C590 |
Instance |
CAN_A_LO |
0x2010 D590 |
CAN_B_LO |
||
0x2810 C590 |
CAN_A_HI |
||
0x2810 D590 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG27_AMR |
Receive Message27 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x594 |
||
Physical address |
0x2010 C594 |
Instance |
CAN_A_LO |
0x2010 D594 |
CAN_B_LO |
||
0x2810 C594 |
CAN_A_HI |
||
0x2810 D594 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG27_ACR |
Receive Message27 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x598 |
||
Physical address |
0x2010 C598 |
Instance |
CAN_A_LO |
0x2010 D598 |
CAN_B_LO |
||
0x2810 C598 |
CAN_A_HI |
||
0x2810 D598 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG27_AMR_DATA |
Receive Message27 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x59C |
||
Physical address |
0x2010 C59C |
Instance |
CAN_A_LO |
0x2010 D59C |
CAN_B_LO |
||
0x2810 C59C |
CAN_A_HI |
||
0x2810 D59C |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG27_ACR_DATA |
Receive Message27 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x5A0 |
||
Physical address |
0x2010 C5A0 |
Instance |
CAN_A_LO |
0x2010 D5A0 |
CAN_B_LO |
||
0x2810 C5A0 |
CAN_A_HI |
||
0x2810 D5A0 |
CAN_B_HI |
||
Description |
Receive Message28 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x5A4 |
||
Physical address |
0x2010 C5A4 |
Instance |
CAN_A_LO |
0x2010 D5A4 |
CAN_B_LO |
||
0x2810 C5A4 |
CAN_A_HI |
||
0x2810 D5A4 |
CAN_B_HI |
||
Description |
Receive Message28 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x5A8 |
||
Physical address |
0x2010 C5A8 |
Instance |
CAN_A_LO |
0x2010 D5A8 |
CAN_B_LO |
||
0x2810 C5A8 |
CAN_A_HI |
||
0x2810 D5A8 |
CAN_B_HI |
||
Description |
Receive Message28 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG28_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x5AC |
||
Physical address |
0x2010 C5AC |
Instance |
CAN_A_LO |
0x2010 D5AC |
CAN_B_LO |
||
0x2810 C5AC |
CAN_A_HI |
||
0x2810 D5AC |
CAN_B_HI |
||
Description |
Receive Message28 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG28_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x5B0 |
||
Physical address |
0x2010 C5B0 |
Instance |
CAN_A_LO |
0x2010 D5B0 |
CAN_B_LO |
||
0x2810 C5B0 |
CAN_A_HI |
||
0x2810 D5B0 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG28_AMR |
Receive Message28 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x5B4 |
||
Physical address |
0x2010 C5B4 |
Instance |
CAN_A_LO |
0x2010 D5B4 |
CAN_B_LO |
||
0x2810 C5B4 |
CAN_A_HI |
||
0x2810 D5B4 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG28_ACR |
Receive Message28 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x5B8 |
||
Physical address |
0x2010 C5B8 |
Instance |
CAN_A_LO |
0x2010 D5B8 |
CAN_B_LO |
||
0x2810 C5B8 |
CAN_A_HI |
||
0x2810 D5B8 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG28_AMR_DATA |
Receive Message28 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x5BC |
||
Physical address |
0x2010 C5BC |
Instance |
CAN_A_LO |
0x2010 D5BC |
CAN_B_LO |
||
0x2810 C5BC |
CAN_A_HI |
||
0x2810 D5BC |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG28_ACR_DATA |
Receive Message28 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x5C0 |
||
Physical address |
0x2010 C5C0 |
Instance |
CAN_A_LO |
0x2010 D5C0 |
CAN_B_LO |
||
0x2810 C5C0 |
CAN_A_HI |
||
0x2810 D5C0 |
CAN_B_HI |
||
Description |
Receive Message29 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x5C4 |
||
Physical address |
0x2010 C5C4 |
Instance |
CAN_A_LO |
0x2010 D5C4 |
CAN_B_LO |
||
0x2810 C5C4 |
CAN_A_HI |
||
0x2810 D5C4 |
CAN_B_HI |
||
Description |
Receive Message29 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x5C8 |
||
Physical address |
0x2010 C5C8 |
Instance |
CAN_A_LO |
0x2010 D5C8 |
CAN_B_LO |
||
0x2810 C5C8 |
CAN_A_HI |
||
0x2810 D5C8 |
CAN_B_HI |
||
Description |
Receive Message29 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG29_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x5CC |
||
Physical address |
0x2010 C5CC |
Instance |
CAN_A_LO |
0x2010 D5CC |
CAN_B_LO |
||
0x2810 C5CC |
CAN_A_HI |
||
0x2810 D5CC |
CAN_B_HI |
||
Description |
Receive Message29 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG29_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x5D0 |
||
Physical address |
0x2010 C5D0 |
Instance |
CAN_A_LO |
0x2010 D5D0 |
CAN_B_LO |
||
0x2810 C5D0 |
CAN_A_HI |
||
0x2810 D5D0 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG29_AMR |
Receive Message29 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x5D4 |
||
Physical address |
0x2010 C5D4 |
Instance |
CAN_A_LO |
0x2010 D5D4 |
CAN_B_LO |
||
0x2810 C5D4 |
CAN_A_HI |
||
0x2810 D5D4 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG29_ACR |
Receive Message29 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x5D8 |
||
Physical address |
0x2010 C5D8 |
Instance |
CAN_A_LO |
0x2010 D5D8 |
CAN_B_LO |
||
0x2810 C5D8 |
CAN_A_HI |
||
0x2810 D5D8 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG29_AMR_DATA |
Receive Message29 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x5DC |
||
Physical address |
0x2010 C5DC |
Instance |
CAN_A_LO |
0x2010 D5DC |
CAN_B_LO |
||
0x2810 C5DC |
CAN_A_HI |
||
0x2810 D5DC |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG29_ACR_DATA |
Receive Message29 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x5E0 |
||
Physical address |
0x2010 C5E0 |
Instance |
CAN_A_LO |
0x2010 D5E0 |
CAN_B_LO |
||
0x2810 C5E0 |
CAN_A_HI |
||
0x2810 D5E0 |
CAN_B_HI |
||
Description |
Receive Message30 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x5E4 |
||
Physical address |
0x2010 C5E4 |
Instance |
CAN_A_LO |
0x2010 D5E4 |
CAN_B_LO |
||
0x2810 C5E4 |
CAN_A_HI |
||
0x2810 D5E4 |
CAN_B_HI |
||
Description |
Receive Message30 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x5E8 |
||
Physical address |
0x2010 C5E8 |
Instance |
CAN_A_LO |
0x2010 D5E8 |
CAN_B_LO |
||
0x2810 C5E8 |
CAN_A_HI |
||
0x2810 D5E8 |
CAN_B_HI |
||
Description |
Receive Message30 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG30_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x5EC |
||
Physical address |
0x2010 C5EC |
Instance |
CAN_A_LO |
0x2010 D5EC |
CAN_B_LO |
||
0x2810 C5EC |
CAN_A_HI |
||
0x2810 D5EC |
CAN_B_HI |
||
Description |
Receive Message30 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG30_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x5F0 |
||
Physical address |
0x2010 C5F0 |
Instance |
CAN_A_LO |
0x2010 D5F0 |
CAN_B_LO |
||
0x2810 C5F0 |
CAN_A_HI |
||
0x2810 D5F0 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG30_AMR |
Receive Message30 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x5F4 |
||
Physical address |
0x2010 C5F4 |
Instance |
CAN_A_LO |
0x2010 D5F4 |
CAN_B_LO |
||
0x2810 C5F4 |
CAN_A_HI |
||
0x2810 D5F4 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG30_ACR |
Receive Message30 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x5F8 |
||
Physical address |
0x2010 C5F8 |
Instance |
CAN_A_LO |
0x2010 D5F8 |
CAN_B_LO |
||
0x2810 C5F8 |
CAN_A_HI |
||
0x2810 D5F8 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG30_AMR_DATA |
Receive Message30 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x5FC |
||
Physical address |
0x2010 C5FC |
Instance |
CAN_A_LO |
0x2010 D5FC |
CAN_B_LO |
||
0x2810 C5FC |
CAN_A_HI |
||
0x2810 D5FC |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG30_ACR_DATA |
Receive Message30 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x600 |
||
Physical address |
0x2010 C600 |
Instance |
CAN_A_LO |
0x2010 D600 |
CAN_B_LO |
||
0x2810 C600 |
CAN_A_HI |
||
0x2810 D600 |
CAN_B_HI |
||
Description |
Receive Message31 buffer command and control register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
Reserved |
|
RO |
0x00 |
23 |
WPNH |
Write protect not high 0: Bit[21:16] remain unchanged 1:
The write protect is not set and bit[21:16] are modified.. default The read
back value of this bit is undefined |
RW |
1 |
22 |
Reserved |
|
RO |
0 |
21 |
RTR |
RTR bit; Control bit 0: This is a regular message 1: This
is an RTR message. |
RW |
0 |
20 |
IDE |
Extended identifier bit; Control bit 0: This is a standard
format message. 1: This is an extended format message. |
RW |
0 |
19:16 |
DLC |
Data length code; Control bits 0: Message has 0 data byte.
1: Message has 1 data byte. ... 8: Message has 8 data bytes. 9:15: Message
has 8 data bytes. |
RW |
0x0 |
15:8 |
Reserved |
|
RO |
0x00 |
7 |
WPNL |
Write protect not low 0: Bits[6:3] remain unchanged 1:
This write protect is not set and bits[6:3] are modified.. default. This bit
is always zero for read back |
RW |
0 |
6 |
LF |
Link flag; Control bit 0: This buffer is not linked to the
next buffer 1: This buffer is linked with the next buffer |
RW |
0 |
5 |
RX_INT_ENABLE |
Receive interrupt enable; Control bit 0: Interrupt
generation is disabled 1: Interrupt generation is enabled |
RW |
0 |
4 |
RTR_REPLY |
Automatic message reply upon receipt of an RTR message;
Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR
message handling enabled |
RW |
0 |
3 |
TxBufferEbl |
Transaction buffer enable; Control bit 0: Buffer is
disabled 1: Buffer is enabled |
RW |
0 |
2 |
RTRabort |
RTR abort request; Command bit 0: Idle 1: Requests removal
of a pending RTR message reply. The flag is cleared when the message was
removed or when the message won arbitration. The TxReq flag is cleared at the
same time |
RW |
0 |
1 |
RTRP |
RTReply pending; Command bit 0: No RTR reply request
pending 1: RTR reply request pending |
RW |
0 |
0 |
MsgAv_RTRS |
Message available/RTR sent; Command bit If RTRreply flag is
set.. this bit shows if an RTR auto-reply message has been sent.. otherwise
it indicates if the buffer contains a valid message. Read 0: Idle 1: New
message available (RTRreply = 0).. RTR auto-reply message sent (RTRreply = 1)
Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR
auto-reply message. Note: Before acknowledging receipt of a new message.. the
message content must be copied into system memory. Acknowledging a message
clears the MsgAv flag. |
RW |
0 |
Address offset |
0x604 |
||
Physical address |
0x2010 C604 |
Instance |
CAN_A_LO |
0x2010 D604 |
CAN_B_LO |
||
0x2810 C604 |
CAN_A_HI |
||
0x2810 D604 |
CAN_B_HI |
||
Description |
Receive Message31 buffer Identifier register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
ID |
RxMessage0 buffer identifier (29-bit wide) |
RW |
0x0000 0000 |
2:0 |
Reserved |
|
RO |
0x0 |
Address offset |
0x608 |
||
Physical address |
0x2010 C608 |
Instance |
CAN_A_LO |
0x2010 D608 |
CAN_B_LO |
||
0x2810 C608 |
CAN_A_HI |
||
0x2810 D608 |
CAN_B_HI |
||
Description |
Receive Message31 buffer data high register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG31_DATA_HIGH |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 1 [23:16]: CAN data
byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1
[31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2
[7:0]: CAN data byte 1 |
RW |
0x0000 0000 |
Address offset |
0x60C |
||
Physical address |
0x2010 C60C |
Instance |
CAN_A_LO |
0x2010 D60C |
CAN_B_LO |
||
0x2810 C60C |
CAN_A_HI |
||
0x2810 D60C |
CAN_B_HI |
||
Description |
Receive Message31 buffer data low register |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG31_DATA_LOW |
The byte mapping can be set using the CAN swap_endian configuration
bit. swap_endian = 0.. default: [31:24]: CAN data byte 5 [23:16]: CAN data
byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1
[31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6
[7:0]: CAN data byte 5 |
RW |
0x0000 0000 |
Address offset |
0x610 |
||
Physical address |
0x2010 C610 |
Instance |
CAN_A_LO |
0x2010 D610 |
CAN_B_LO |
||
0x2810 C610 |
CAN_A_HI |
||
0x2810 D610 |
CAN_B_HI |
||
Description |
Acceptance mask register (AMR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG31_AMR |
Receive Message31 buffer AMR bits [31:3]: Identifier [2]: IDE
[1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the
respective ACR. The message is not accepted when the incoming bit does not
match with the respective ACR flag. 1: The incoming bit is a "don't
care" |
RW |
0x0000 0000 |
Address offset |
0x614 |
||
Physical address |
0x2010 C614 |
Instance |
CAN_A_LO |
0x2010 D614 |
CAN_B_LO |
||
0x2810 C614 |
CAN_A_HI |
||
0x2810 D614 |
CAN_B_HI |
||
Description |
Acceptance code register (ACR) |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG31_ACR |
Receive Message31 buffer ACR bits [31:3]: Identifier [2]:
IDE [1]: RTR [0]: N/A |
RW |
0x0000 0000 |
Address offset |
0x618 |
||
Physical address |
0x2010 C618 |
Instance |
CAN_A_LO |
0x2010 D618 |
CAN_B_LO |
||
0x2810 C618 |
CAN_A_HI |
||
0x2810 D618 |
CAN_B_HI |
||
Description |
AMR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG31_AMR_DATA |
Receive Message31 buffer AMR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
Address offset |
0x61C |
||
Physical address |
0x2010 C61C |
Instance |
CAN_A_LO |
0x2010 D61C |
CAN_B_LO |
||
0x2810 C61C |
CAN_A_HI |
||
0x2810 D61C |
CAN_B_HI |
||
Description |
ACR- Data |
||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
RX_MSG31_ACR_DATA |
Receive Message31 buffer ACR Data bits [15:8]: CAN data
byte 1 [7:0]: CAN data byte 2 |
RW |
0x0000 0000 |
CAN has no common
memories.