CFG_DDR_SGMII_PHY

This section provides information on the CFG_DDR_SGMII_PHY Module Instance. Each of the module registers is described below.

No lock registers supported.

 

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CFG_DDR_SGMII_PHY Register Mapping Summary

CFG_DDR_SGMII_PHY Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

SOFT_RESET_DDR_PHY

RW

32

0x0000 0000

0x000

0x2000 7000

DDRPHY_MODE

RW

32

0x0000 0002

0x004

0x2000 7004

DDRPHY_STARTUP

RW

32

0x0020 0000

0x008

0x2000 7008

SPARE_0

RW

32

0x0000 0000

0x00C

0x2000 700C

SOFT_RESET_MAIN_PLL

RW

32

0x0000 0000

0x080

0x2000 7080

PLL_CTRL_MAIN

RW

32

0x0000 10BE

0x084

0x2000 7084

PLL_REF_FB_MAIN

RW

32

0x0000 0100

0x088

0x2000 7088

PLL_FRACN_MAIN

RO

32

0x0000 0000

0x08C

0x2000 708C

PLL_DIV_0_1_MAIN

RW

32

0x0800 0200

0x090

0x2000 7090

PLL_DIV_2_3_MAIN

RW

32

0x1400 0800

0x094

0x2000 7094

PLL_CTRL2_MAIN

RW

32

0x0000 1018

0x098

0x2000 7098

PLL_CAL_MAIN

RO

32

0x0000 0008

0x09C

0x2000 709C

PLL_PHADJ_MAIN

RW

32

0x0000 0001

0x0A0

0x2000 70A0

SSCG_REG_0_MAIN

RO

32

0x0000 0000

0x0A4

0x2000 70A4

SSCG_REG_1_MAIN

RO

32

0x0000 000A

0x0A8

0x2000 70A8

SSCG_REG_2_MAIN

RW

32

0x0000 0030

0x0AC

0x2000 70AC

SSCG_REG_3_MAIN

RO

32

0x0000 0001

0x0B0

0x2000 70B0

RPC_RESET_MAIN_PLL

RW

32

0x0000 0000

0x0B4

0x2000 70B4

SOFT_RESET_IOSCB_PLL

RW

32

0x0000 0000

0x100

0x2000 7100

PLL_CTRL_IOSCB

RW

32

0x0000 10BE

0x104

0x2000 7104

PLL_REF_FB_IOSCB

RW

32

0x0000 0100

0x108

0x2000 7108

PLL_FRACN_IOSCB

RO

32

0x0000 0000

0x10C

0x2000 710C

PLL_DIV_0_1_IOSCB

RW

32

0x0200 0100

0x110

0x2000 7110

PLL_DIV_2_3_IOSCB

RW

32

0x0100 0100

0x114

0x2000 7114

PLL_CTRL2_IOSCB

RW

32

0x0000 1018

0x118

0x2000 7118

PLL_CAL_IOSCB

RO

32

0x0000 0008

0x11C

0x2000 711C

PLL_PHADJ_IOSCB

RW

32

0x0000 4001

0x120

0x2000 7120

SSCG_REG_0_IOSCB

RO

32

0x0000 0000

0x124

0x2000 7124

SSCG_REG_1_IOSCB

RO

32

0x0000 000A

0x128

0x2000 7128

SSCG_REG_2_IOSCB

RW

32

0x0000 0020

0x12C

0x2000 712C

SSCG_REG_3_IOSCB

RO

32

0x0000 0001

0x130

0x2000 7130

RPC_RESET_IOSCB

RW

32

0x0000 0000

0x134

0x2000 7134

SOFT_RESET_BANK_CTRL

RW

32

0x0000 0000

0x180

0x2000 7180

DPC_BITS

RW

32

0x0005 C5C3

0x184

0x2000 7184

BANK_STATUS

RO

32

0x0000 0000

0x188

0x2000 7188

RPC_RESET_BANK_CTRL

RW

32

0x0000 0000

0x18C

0x2000 718C

SOFT_RESET_IOCALIB

RW

32

0x0000 0000

0x200

0x2000 7200

IOC_REG0

RW

32

0x0000 8000

0x204

0x2000 7204

IOC_REG1

RO

32

0x0000 0000

0x208

0x2000 7208

IOC_REG2

RO

32

0x0000 0000

0x20C

0x2000 720C

IOC_REG3

RO

32

0x0000 0000

0x210

0x2000 7210

IOC_REG4

RO

32

0x0000 0000

0x214

0x2000 7214

IOC_REG5

RO

32

0x0000 0000

0x218

0x2000 7218

IOC_REG6

RW

32

0x0000 0005

0x21C

0x2000 721C

RPC_RESET_IOCALIB

RW

32

0x0000 0000

0x220

0x2000 7220

RPC_calib

RW

32

0x0000 0000

0x224

0x2000 7224

SOFT_RESET_CFM

RW

32

0x0000 0000

0x280

0x2000 7280

BCLKMUX

RW

32

0x0000 0208

0x284

0x2000 7284

PLL_CKMUX

RW

32

0x0000 0005

0x288

0x2000 7288

MSSCLKMUX

RW

32

0x0000 0000

0x28C

0x2000 728C

SPARE0

RW

32

0x0000 0000

0x290

0x2000 7290

FMETER_ADDR

RO

32

0x0000 0000

0x294

0x2000 7294

FMETER_DATAW

RO

32

0x0000 0000

0x298

0x2000 7298

FMETER_DATAR

RO

32

0x0000 0000

0x29C

0x2000 729C

TEST_CTRL

RO

32

0x0000 0000

0x2A0

0x2000 72A0

RPC_RESET_CFM

RW

32

0x0000 0000

0x2A4

0x2000 72A4

SOFT_RESET_DECODER_DRIVER

RW

32

0x0000 0000

0x300

0x2000 7300

RPC1_DRV

RW

32

0x0000 0000

0x304

0x2000 7304

RPC2_DRV

RW

32

0x0000 0000

0x308

0x2000 7308

RPC3_DRV

RW

32

0x0000 0000

0x30C

0x2000 730C

RPC4_DRV

RW

32

0x0000 0000

0x310

0x2000 7310

SOFT_RESET_DECODER_ODT

RW

32

0x0000 0000

0x380

0x2000 7380

RPC1_ODT

RW

32

0x0000 0000

0x384

0x2000 7384

RPC2_ODT

RW

32

0x0000 0000

0x388

0x2000 7388

RPC3_ODT

RW

32

0x0000 0000

0x38C

0x2000 738C

RPC4_ODT

RW

32

0x0000 0000

0x390

0x2000 7390

RPC5_ODT

RW

32

0x0000 0000

0x394

0x2000 7394

RPC6_ODT

RW

32

0x0000 0000

0x398

0x2000 7398

RPC7_ODT

RW

32

0x0000 0000

0x39C

0x2000 739C

RPC8_ODT

RW

32

0x0000 0000

0x3A0

0x2000 73A0

RPC9_ODT

RW

32

0x0000 0000

0x3A4

0x2000 73A4

RPC10_ODT

RW

32

0x0000 0000

0x3A8

0x2000 73A8

RPC11_ODT

RW

32

0x0000 0000

0x3AC

0x2000 73AC

SOFT_RESET_DECODER_IO

RW

32

0x0000 0000

0x400

0x2000 7400

OVRT1

RW

32

0x0000 0000

0x404

0x2000 7404

OVRT2

RW

32

0x0000 0000

0x408

0x2000 7408

OVRT3

RW

32

0x0000 0000

0x40C

0x2000 740C

OVRT4

RW

32

0x0000 0000

0x410

0x2000 7410

OVRT5

RW

32

0x0000 0000

0x414

0x2000 7414

OVRT6

RW

32

0x0000 0000

0x418

0x2000 7418

OVRT7

RW

32

0x0000 0000

0x41C

0x2000 741C

OVRT8

RW

32

0x0000 0000

0x420

0x2000 7420

OVRT9

RW

32

0x0000 0000

0x424

0x2000 7424

OVRT10

RW

32

0x0000 0000

0x428

0x2000 7428

OVRT11

RW

32

0x0000 0000

0x42C

0x2000 742C

OVRT12

RW

32

0x0000 0000

0x430

0x2000 7430

OVRT13

RW

32

0x0000 0000

0x434

0x2000 7434

OVRT14

RW

32

0x0000 0000

0x438

0x2000 7438

OVRT15

RW

32

0x0000 0000

0x43C

0x2000 743C

OVRT16

RW

32

0x0000 0000

0x440

0x2000 7440

RPC17

RW

32

0x0000 0000

0x444

0x2000 7444

RPC18

RW

32

0x0000 0000

0x448

0x2000 7448

RPC19

RW

32

0x0000 0000

0x44C

0x2000 744C

RPC20

RW

32

0x0000 0000

0x450

0x2000 7450

RPC21

RW

32

0x0000 0000

0x454

0x2000 7454

RPC22

RW

32

0x0000 0000

0x458

0x2000 7458

RPC23

RW

32

0x0000 0000

0x45C

0x2000 745C

RPC24

RW

32

0x0000 0000

0x460

0x2000 7460

RPC25

RW

32

0x0000 0000

0x464

0x2000 7464

RPC26

RW

32

0x0000 0000

0x468

0x2000 7468

RPC27

RW

32

0x0000 0000

0x46C

0x2000 746C

RPC28

RW

32

0x0000 0000

0x470

0x2000 7470

RPC29

RW

32

0x0000 0000

0x474

0x2000 7474

RPC30

RW

32

0x0000 0000

0x478

0x2000 7478

RPC31

RW

32

0x0000 0000

0x47C

0x2000 747C

RPC32

RW

32

0x0000 0000

0x480

0x2000 7480

RPC33

RW

32

0x0000 0000

0x484

0x2000 7484

RPC34

RW

32

0x0000 0000

0x488

0x2000 7488

RPC35

RW

32

0x0000 0000

0x48C

0x2000 748C

RPC36

RW

32

0x0000 0000

0x490

0x2000 7490

RPC37

RW

32

0x0000 0000

0x494

0x2000 7494

RPC38

RW

32

0x0000 0000

0x498

0x2000 7498

RPC39

RW

32

0x0000 0000

0x49C

0x2000 749C

RPC40

RW

32

0x0000 0000

0x4A0

0x2000 74A0

RPC41

RW

32

0x0000 0000

0x4A4

0x2000 74A4

RPC42

RW

32

0x0000 0000

0x4A8

0x2000 74A8

RPC43

RW

32

0x0000 0000

0x4AC

0x2000 74AC

RPC44

RW

32

0x0000 0000

0x4B0

0x2000 74B0

RPC45

RW

32

0x0000 0000

0x4B4

0x2000 74B4

RPC46

RW

32

0x0000 0000

0x4B8

0x2000 74B8

RPC47

RW

32

0x0000 0000

0x4BC

0x2000 74BC

RPC48

RW

32

0x0000 0000

0x4C0

0x2000 74C0

RPC49

RW

32

0x0000 0000

0x4C4

0x2000 74C4

RPC50

RW

32

0x0000 0000

0x4C8

0x2000 74C8

RPC51

RW

32

0x0000 0000

0x4CC

0x2000 74CC

RPC52

RW

32

0x0000 0000

0x4D0

0x2000 74D0

RPC53

RW

32

0x0000 0000

0x4D4

0x2000 74D4

RPC54

RW

32

0x0000 0000

0x4D8

0x2000 74D8

RPC55

RW

32

0x0000 0000

0x4DC

0x2000 74DC

RPC56

RW

32

0x0000 0000

0x4E0

0x2000 74E0

RPC57

RW

32

0x0000 0000

0x4E4

0x2000 74E4

RPC58

RW

32

0x0000 0000

0x4E8

0x2000 74E8

RPC59

RW

32

0x0000 0000

0x4EC

0x2000 74EC

RPC60

RW

32

0x0000 0000

0x4F0

0x2000 74F0

RPC61

RW

32

0x0000 0000

0x4F4

0x2000 74F4

RPC62

RW

32

0x0000 0000

0x4F8

0x2000 74F8

RPC63

RW

32

0x0000 0000

0x4FC

0x2000 74FC

RPC64

RW

32

0x0000 0000

0x500

0x2000 7500

RPC65

RW

32

0x0000 0000

0x504

0x2000 7504

RPC66

RW

32

0x0000 0000

0x508

0x2000 7508

RPC67

RW

32

0x0000 0000

0x50C

0x2000 750C

RPC68

RW

32

0x0000 0000

0x510

0x2000 7510

RPC69

RW

32

0x0000 0000

0x514

0x2000 7514

RPC70

RW

32

0x0000 0000

0x518

0x2000 7518

RPC71

RW

32

0x0000 0000

0x51C

0x2000 751C

RPC72

RW

32

0x0000 0000

0x520

0x2000 7520

RPC73

RW

32

0x0000 0000

0x524

0x2000 7524

RPC74

RW

32

0x0000 0000

0x528

0x2000 7528

RPC75

RW

32

0x0000 0000

0x52C

0x2000 752C

RPC76

RW

32

0x0000 0000

0x530

0x2000 7530

RPC77

RW

32

0x0000 0000

0x534

0x2000 7534

RPC78

RW

32

0x0000 0000

0x538

0x2000 7538

RPC79

RW

32

0x0000 0000

0x53C

0x2000 753C

RPC80

RW

32

0x0000 0000

0x540

0x2000 7540

RPC81

RW

32

0x0000 0000

0x544

0x2000 7544

RPC82

RW

32

0x0000 0000

0x548

0x2000 7548

RPC83

RW

32

0x0000 0000

0x54C

0x2000 754C

RPC84

RW

32

0x0000 0000

0x550

0x2000 7550

RPC85

RW

32

0x0000 0000

0x554

0x2000 7554

RPC86

RW

32

0x0000 0000

0x558

0x2000 7558

RPC87

RW

32

0x0000 0000

0x55C

0x2000 755C

RPC88

RW

32

0x0000 0000

0x560

0x2000 7560

RPC89

RW

32

0x0000 0000

0x564

0x2000 7564

RPC90

RW

32

0x0000 0000

0x568

0x2000 7568

RPC91

RW

32

0x0000 0000

0x56C

0x2000 756C

RPC92

RW

32

0x0000 0000

0x570

0x2000 7570

RPC93

RW

32

0x0000 0000

0x574

0x2000 7574

RPC94

RW

32

0x0000 0000

0x578

0x2000 7578

RPC95

RW

32

0x0000 0000

0x57C

0x2000 757C

RPC96

RW

32

0x0000 0000

0x580

0x2000 7580

RPC97

RW

32

0x0000 0000

0x584

0x2000 7584

RPC98

RW

32

0x0000 0000

0x588

0x2000 7588

RPC99

RW

32

0x0000 0000

0x58C

0x2000 758C

RPC100

RW

32

0x0000 0000

0x590

0x2000 7590

RPC101

RW

32

0x0000 0000

0x594

0x2000 7594

RPC102

RW

32

0x0000 0000

0x598

0x2000 7598

RPC103

RW

32

0x0000 0000

0x59C

0x2000 759C

RPC104

RW

32

0x0000 0000

0x5A0

0x2000 75A0

RPC105

RW

32

0x0000 0000

0x5A4

0x2000 75A4

RPC106

RW

32

0x0000 0000

0x5A8

0x2000 75A8

RPC107

RW

32

0x0000 0000

0x5AC

0x2000 75AC

RPC108

RW

32

0x0000 0000

0x5B0

0x2000 75B0

RPC109

RW

32

0x0000 0000

0x5B4

0x2000 75B4

RPC110

RW

32

0x0000 0000

0x5B8

0x2000 75B8

RPC111

RW

32

0x0000 0000

0x5BC

0x2000 75BC

RPC112

RW

32

0x0000 0000

0x5C0

0x2000 75C0

RPC113

RW

32

0x0000 0000

0x5C4

0x2000 75C4

RPC114

RW

32

0x0000 0000

0x5C8

0x2000 75C8

RPC115

RW

32

0x0000 0000

0x5CC

0x2000 75CC

RPC116

RW

32

0x0000 0000

0x5D0

0x2000 75D0

RPC117

RW

32

0x0000 0000

0x5D4

0x2000 75D4

RPC118

RW

32

0x0000 0000

0x5D8

0x2000 75D8

RPC119

RW

32

0x0000 0000

0x5DC

0x2000 75DC

RPC120

RW

32

0x0000 0000

0x5E0

0x2000 75E0

RPC121

RW

32

0x0000 0000

0x5E4

0x2000 75E4

RPC122

RW

32

0x0000 0000

0x5E8

0x2000 75E8

RPC123

RW

32

0x0000 0000

0x5EC

0x2000 75EC

RPC124

RW

32

0x0000 0000

0x5F0

0x2000 75F0

RPC125

RW

32

0x0000 0000

0x5F4

0x2000 75F4

RPC126

RW

32

0x0000 0000

0x5F8

0x2000 75F8

RPC127

RW

32

0x0000 0000

0x5FC

0x2000 75FC

RPC128

RW

32

0x0000 0000

0x600

0x2000 7600

RPC129

RW

32

0x0000 0000

0x604

0x2000 7604

RPC130

RW

32

0x0000 0000

0x608

0x2000 7608

RPC131

RW

32

0x0000 0000

0x60C

0x2000 760C

RPC132

RW

32

0x0000 0000

0x610

0x2000 7610

RPC133

RW

32

0x0000 0000

0x614

0x2000 7614

RPC134

RW

32

0x0000 0000

0x618

0x2000 7618

RPC135

RW

32

0x0000 0000

0x61C

0x2000 761C

RPC136

RW

32

0x0000 0000

0x620

0x2000 7620

RPC137

RW

32

0x0000 0000

0x624

0x2000 7624

RPC138

RW

32

0x0000 0000

0x628

0x2000 7628

RPC139

RW

32

0x0000 0000

0x62C

0x2000 762C

RPC140

RW

32

0x0000 0000

0x630

0x2000 7630

RPC141

RW

32

0x0000 0000

0x634

0x2000 7634

RPC142

RW

32

0x0000 0000

0x638

0x2000 7638

RPC143

RW

32

0x0000 0000

0x63C

0x2000 763C

RPC144

RW

32

0x0000 0000

0x640

0x2000 7640

RPC145

RW

32

0x0000 0000

0x644

0x2000 7644

RPC146

RW

32

0x0000 0000

0x648

0x2000 7648

RPC147

RW

32

0x0000 0000

0x64C

0x2000 764C

RPC148

RW

32

0x0000 0000

0x650

0x2000 7650

RPC149

RW

32

0x0000 0000

0x654

0x2000 7654

RPC150

RW

32

0x0000 0000

0x658

0x2000 7658

RPC151

RW

32

0x0000 0000

0x65C

0x2000 765C

RPC152

RW

32

0x0000 0000

0x660

0x2000 7660

RPC153

RW

32

0x0000 0000

0x664

0x2000 7664

RPC154

RW

32

0x0000 0000

0x668

0x2000 7668

RPC155

RW

32

0x0000 0000

0x66C

0x2000 766C

RPC156

RW

32

0x0000 0000

0x670

0x2000 7670

RPC157

RW

32

0x0000 0000

0x674

0x2000 7674

RPC158

RW

32

0x0000 0000

0x678

0x2000 7678

RPC159

RW

32

0x0000 0000

0x67C

0x2000 767C

RPC160

RW

32

0x0000 0000

0x680

0x2000 7680

RPC161

RW

32

0x0000 0000

0x684

0x2000 7684

RPC162

RW

32

0x0000 0000

0x688

0x2000 7688

RPC163

RW

32

0x0000 0000

0x68C

0x2000 768C

RPC164

RW

32

0x0000 0000

0x690

0x2000 7690

RPC165

RW

32

0x0000 0000

0x694

0x2000 7694

RPC166

RW

32

0x0000 0000

0x698

0x2000 7698

RPC167

RW

32

0x0000 0000

0x69C

0x2000 769C

RPC168

RW

32

0x0000 0000

0x6A0

0x2000 76A0

RPC169

RW

32

0x0000 0000

0x6A4

0x2000 76A4

RPC170

RW

32

0x0000 0000

0x6A8

0x2000 76A8

RPC171

RW

32

0x0000 0000

0x6AC

0x2000 76AC

RPC172

RW

32

0x0000 0000

0x6B0

0x2000 76B0

RPC173

RW

32

0x0000 0000

0x6B4

0x2000 76B4

RPC174

RW

32

0x0000 0000

0x6B8

0x2000 76B8

RPC175

RW

32

0x0000 0000

0x6BC

0x2000 76BC

RPC176

RW

32

0x0000 0000

0x6C0

0x2000 76C0

RPC177

RW

32

0x0000 0000

0x6C4

0x2000 76C4

RPC178

RW

32

0x0000 0000

0x6C8

0x2000 76C8

RPC179

RW

32

0x0000 0000

0x6CC

0x2000 76CC

RPC180

RW

32

0x0000 0000

0x6D0

0x2000 76D0

RPC181

RW

32

0x0000 0000

0x6D4

0x2000 76D4

RPC182

RW

32

0x0000 0000

0x6D8

0x2000 76D8

RPC183

RW

32

0x0000 0000

0x6DC

0x2000 76DC

RPC184

RW

32

0x0000 0000

0x6E0

0x2000 76E0

RPC185

RW

32

0x0000 0000

0x6E4

0x2000 76E4

RPC186

RW

32

0x0000 0000

0x6E8

0x2000 76E8

RPC187

RW

32

0x0000 0000

0x6EC

0x2000 76EC

RPC188

RW

32

0x0000 0000

0x6F0

0x2000 76F0

RPC189

RW

32

0x0000 0000

0x6F4

0x2000 76F4

RPC190

RW

32

0x0000 0000

0x6F8

0x2000 76F8

RPC191

RW

32

0x0000 0000

0x6FC

0x2000 76FC

RPC192

RW

32

0x0000 0000

0x700

0x2000 7700

RPC193

RW

32

0x0000 0000

0x704

0x2000 7704

RPC194

RW

32

0x0000 0000

0x708

0x2000 7708

RPC195

RW

32

0x0000 0000

0x70C

0x2000 770C

RPC196

RW

32

0x0000 0000

0x710

0x2000 7710

RPC197

RW

32

0x0000 0000

0x714

0x2000 7714

RPC198

RW

32

0x0000 0000

0x718

0x2000 7718

RPC199

RW

32

0x0000 0000

0x71C

0x2000 771C

RPC200

RW

32

0x0000 0000

0x720

0x2000 7720

RPC201

RW

32

0x0000 0000

0x724

0x2000 7724

RPC202

RW

32

0x0000 0000

0x728

0x2000 7728

RPC203

RW

32

0x0000 0000

0x72C

0x2000 772C

RPC204

RW

32

0x0000 0000

0x730

0x2000 7730

RPC205

RW

32

0x0000 0000

0x734

0x2000 7734

RPC206

RW

32

0x0000 0000

0x738

0x2000 7738

RPC207

RW

32

0x0000 0000

0x73C

0x2000 773C

RPC208

RW

32

0x0000 0000

0x740

0x2000 7740

RPC209

RW

32

0x0000 0000

0x744

0x2000 7744

RPC210

RW

32

0x0000 0000

0x748

0x2000 7748

RPC211

RW

32

0x0000 0000

0x74C

0x2000 774C

RPC212

RW

32

0x0000 0000

0x750

0x2000 7750

RPC213

RW

32

0x0000 0000

0x754

0x2000 7754

RPC214

RW

32

0x0000 0000

0x758

0x2000 7758

RPC215

RW

32

0x0000 0000

0x75C

0x2000 775C

RPC216

RW

32

0x0000 0000

0x760

0x2000 7760

RPC217

RW

32

0x0000 0000

0x764

0x2000 7764

RPC218

RW

32

0x0000 0000

0x768

0x2000 7768

RPC219

RW

32

0x0000 0000

0x76C

0x2000 776C

RPC220

RW

32

0x0000 0000

0x770

0x2000 7770

RPC221

RW

32

0x0000 0000

0x774

0x2000 7774

RPC222

RW

32

0x0000 0000

0x778

0x2000 7778

RPC223

RW

32

0x0000 0000

0x77C

0x2000 777C

RPC224

RW

32

0x0000 0000

0x780

0x2000 7780

RPC225

RW

32

0x0000 0000

0x784

0x2000 7784

RPC226

RW

32

0x0000 0000

0x788

0x2000 7788

RPC227

RW

32

0x0000 0000

0x78C

0x2000 778C

RPC228

RW

32

0x0000 0000

0x790

0x2000 7790

RPC229

RW

32

0x0000 0000

0x794

0x2000 7794

RPC230

RW

32

0x0000 0000

0x798

0x2000 7798

RPC231

RW

32

0x0000 0000

0x79C

0x2000 779C

RPC232

RW

32

0x0000 0000

0x7A0

0x2000 77A0

RPC233

RW

32

0x0000 0000

0x7A4

0x2000 77A4

RPC234

RW

32

0x0000 0000

0x7A8

0x2000 77A8

RPC235

RW

32

0x0000 0000

0x7AC

0x2000 77AC

RPC236

RW

32

0x0000 0000

0x7B0

0x2000 77B0

RPC237

RW

32

0x0000 0000

0x7B4

0x2000 77B4

RPC238

RW

32

0x0000 0000

0x7B8

0x2000 77B8

RPC239

RW

32

0x0000 0000

0x7BC

0x2000 77BC

RPC240

RW

32

0x0000 0000

0x7C0

0x2000 77C0

RPC241

RW

32

0x0000 0000

0x7C4

0x2000 77C4

RPC242

RW

32

0x0000 0000

0x7C8

0x2000 77C8

RPC243

RW

32

0x0000 0000

0x7CC

0x2000 77CC

RPC244

RW

32

0x0000 0000

0x7D0

0x2000 77D0

RPC245

RW

32

0x0000 0000

0x7D4

0x2000 77D4

RPC246

RW

32

0x0000 0000

0x7D8

0x2000 77D8

RPC247

RW

32

0x0000 0000

0x7DC

0x2000 77DC

RPC248

RW

32

0x0000 0000

0x7E0

0x2000 77E0

RPC249

RW

32

0x0000 0000

0x7E4

0x2000 77E4

RPC250

RW

32

0x0000 0000

0x7E8

0x2000 77E8

SPIO251

RW

32

0x0000 0000

0x7EC

0x2000 77EC

SPIO252

RW

32

0x0000 0000

0x7F0

0x2000 77F0

SPIO253

RW

32

0x0000 0000

0x7F4

0x2000 77F4

SOFT_RESET_TIP

RW

32

0x0000 0000

0x800

0x2000 7800

RANK_SELECT

RW

32

0x0000 0000

0x804

0x2000 7804

LANE_SELECT

RW

32

0x0000 0000

0x808

0x2000 7808

TRAINING_SKIP

RW

32

0x0000 0000

0x80C

0x2000 780C

TRAINING_START

RW

32

0x0000 0000

0x810

0x2000 7810

TRAINING_STATUS

RO

32

0x0000 0000

0x814

0x2000 7814

TRAINING_RESET

RW

32

0x0000 0000

0x818

0x2000 7818

GT_ERR_COMB

RO

32

0x0000 0000

0x81C

0x2000 781C

GT_CLK_SEL

RO

32

0x0000 0000

0x820

0x2000 7820

GT_TXDLY

RO

32

0x0000 0000

0x824

0x2000 7824

GT_STEPS_180

RO

32

0x0000 0000

0x828

0x2000 7828

GT_STATE

RO

32

0x0000 0000

0x82C

0x2000 782C

WL_DELAY_0

RO

32

0x0000 0000

0x830

0x2000 7830

DQ_DQS_ERR_DONE

RO

32

0x0000 0000

0x834

0x2000 7834

DQDQS_WINDOW

RO

32

0x0000 0000

0x838

0x2000 7838

DQDQS_STATE

RO

32

0x0000 0000

0x83C

0x2000 783C

DELTA0

RO

32

0x0000 0000

0x840

0x2000 7840

DELTA1

RO

32

0x0000 0000

0x844

0x2000 7844

DQDQS_STATUS0

RO

32

0x0000 0000

0x848

0x2000 7848

DQDQS_STATUS1

RO

32

0x0000 0000

0x84C

0x2000 784C

DQDQS_STATUS2

RO

32

0x0000 0000

0x850

0x2000 7850

DQDQS_STATUS3

RO

32

0x0000 0000

0x854

0x2000 7854

DQDQS_STATUS4

RO

32

0x0000 0000

0x858

0x2000 7858

DQDQS_STATUS5

RO

32

0x0000 0000

0x85C

0x2000 785C

DQDQS_STATUS6

RO

32

0x0000 0000

0x860

0x2000 7860

ADDCMD_STATUS0

RO

32

0x0000 0000

0x864

0x2000 7864

ADDCMD_STATUS1

RO

32

0x0000 0000

0x868

0x2000 7868

ADDCMD_ANSWER

RO

32

0x0000 0000

0x86C

0x2000 786C

BCLKSCLK_ANSWER

RO

32

0x0000 0000

0x870

0x2000 7870

DQDQS_WRCALIB_OFFSET

RO

32

0x0000 0000

0x874

0x2000 7874

EXPERT_MODE_EN

RW

32

0x0000 0000

0x878

0x2000 7878

EXPERT_DLYCNT_MOVE_REG0

RW

32

0x0000 0000

0x87C

0x2000 787C

EXPERT_DLYCNT_MOVE_REG1

RW

32

0x0000 0000

0x880

0x2000 7880

EXPERT_DLYCNT_DIRECTION_REG0

RW

32

0x0000 0000

0x884

0x2000 7884

EXPERT_DLYCNT_DIRECTION_REG1

RW

32

0x0000 0000

0x888

0x2000 7888

EXPERT_DLYCNT_LOAD_REG0

RW

32

0x0000 0000

0x88C

0x2000 788C

EXPERT_DLYCNT_LOAD_REG1

RW

32

0x0000 0000

0x890

0x2000 7890

EXPERT_DLYCNT_OOR_REG0

RO

32

0x0000 0000

0x894

0x2000 7894

EXPERT_DLYCNT_OOR_REG1

RO

32

0x0000 0000

0x898

0x2000 7898

EXPERT_DLYCNT_MV_RD_DLY_REG

RW

32

0x0000 0000

0x89C

0x2000 789C

EXPERT_DLYCNT_PAUSE

RW

32

0x0000 0000

0x8A0

0x2000 78A0

EXPERT_PLLCNT

RW

32

0x0000 0004

0x8A4

0x2000 78A4

EXPERT_DQLANE_READBACK

RO

32

0x0000 0000

0x8A8

0x2000 78A8

EXPERT_ADDCMD_LN_READBACK

RO

32

0x0000 0000

0x8AC

0x2000 78AC

EXPERT_READ_GATE_CONTROLS

RW

32

0x0000 0000

0x8B0

0x2000 78B0

EXPERT_DQ_DQS_OPTIMIZATION0

RO

32

0x0000 0000

0x8B4

0x2000 78B4

EXPERT_DQ_DQS_OPTIMIZATION1

RO

32

0x0000 0000

0x8B8

0x2000 78B8

EXPERT_WRCALIB

RW

32

0x0000 0000

0x8BC

0x2000 78BC

EXPERT_CALIF

RW

32

0x0000 0000

0x8C0

0x2000 78C0

EXPERT_CALIF_READBACK

RO

32

0x0000 0000

0x8C4

0x2000 78C4

EXPERT_CALIF_READBACK1

RO

32

0x0000 0000

0x8C8

0x2000 78C8

EXPERT_DFI_STATUS_OVERRIDE_TO_SHIM

RW

32

0x0000 0000

0x8CC

0x2000 78CC

TIP_CFG_PARAMS

RW

32

0x0000 0000

0x8D0

0x2000 78D0

TIP_VREF_PARAM

RW

32

0x0000 0000

0x8D4

0x2000 78D4

LANE_ALIGNMENT_FIFO_CONTROL

RW

32

0x0000 0002

0x8D8

0x2000 78D8

SOFT_RESET_SGMII

RW

32

0x0000 0000

0xC00

0x2000 7C00

SGMII_MODE

RW

32

0x0040 E60C

0xC04

0x2000 7C04

PLL_CNTL

RW

32

0x8014 0101

0xC08

0x2000 7C08

CH0_CNTL

RW

32

0x009C 0000

0xC0C

0x2000 7C0C

CH1_CNTL

RW

32

0x009C 0000

0xC10

0x2000 7C10

RECAL_CNTL

RW

32

0x0000 0008

0xC14

0x2000 7C14

CLK_CNTL

RW

32

0xF000 0000

0xC18

0x2000 7C18

DYN_CNTL

RW

32

0x0000 0400

0xC1C

0x2000 7C1C

PVT_STAT

RW

32

0x8000 0000

0xC20

0x2000 7C20

SPARE_CNTL

RW

32

0xFF00 0000

0xC24

0x2000 7C24

SPARE_STAT

RO

32

0x0000 0000

0xC28

0x2000 7C28

 

CFG_DDR_SGMII_PHY Register Descriptions

CFG_DDR_SGMII_PHY : SOFT_RESET_DDR_PHY

Address offset

0x000

Physical address

0x2000 7000

Instance

CFG_DDR_SGMII_PHY

Description

Compulsory register for all SCB slaves, facilitating global soft reset.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

BLOCKID_DDR_PHY

This returns the block type and chip location. The form of BLOCKID = {4'h0, SLVTYPE, CHIPID, SUBID}. SLVTYPE=4'h2 for PCIESS MAIN. CHIPID=4'h0 for PCIESS. SUBID=4'h4 for the MAIN page.

RO

0x0000

15:9

Reserved

 

RO
Rreturns0s

0x00

8

PERIPH_DDR_PHY

This asserts functional reset of the peripheral block. It is asserted and left asserted at power-up.

WO

0

 

 

Write 0

[scb_periph_not_in_soft_reset_ddr_phy] Reset not asserted.

 

 

 

Write 1

[scb_periph_reset_ddr_phy] SCB registers reset pulsed.

 

7:2

Reserved

 

RO
Rreturns0s

0x00

1

V_MAP_DDR_PHY

Resets all the volatile register bits.

WO

0

 

 

Write 0

[scb_v_regs_not_in_soft_reset_ddr_phy] Reset not asserted.

 

 

 

Write 1

[scb_v_regs_reset_ddr_phy] SCB Volatile reset (i.e. RW-X registers are reset)

 

0

NV_MAP_DDR_PHY

Resets all the non-volatile register bits (e.g. RW-P bits).

WO

0

 

 

Write 0

[scb_nv_regs_not_in_soft_reset_ddr_phy] Reset not asserted.

 

 

 

Write 1

[scb_nv_regs_reset_ddr_phy] SCB Non-Volatile reset (i.e. RW-P registers are reset.

 

 

CFG_DDR_SGMII_PHY : DDRPHY_MODE

Address offset

0x004

Physical address

0x2000 7004

Instance

CFG_DDR_SGMII_PHY

Description

DDRPHY MODE Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:29

Reserved

 

RO
Rreturns0s

0x0

28:27

Command_Address_Pipe

Added Command/Address pipelining

RW

0x0

26

rank

select rank

RW

0

25

Power_down

Power down DDR PHY

RW

0

24:23

preset_odt_clk

Default, +1,+2, -1 increment settings

RW

0x0

22:21

ADD_CMD_input_pin_termination

Default, +1,+2, -1 increment settings

RW

0x0

20:19

DQS_termination

Default, +1,+2, -1 increment settings

RW

0x0

18:17

DQ_termination

Default, +1,+2, -1 increment settings

RW

0x0

16:15

Clock_out_drive

Default, +1,+2, -1 increment settings

RW

0x0

14:13

ADD_CMD_drive

Default, +1,+2, -1 increment settings

RW

0x0

12:11

DQS_drive

Default, +1,+2, -1 increment settings

RW

0x0

10:9

DQ_drive

Default, +1,+2, -1 increment settings

RW

0x0

8

DMI_DBI

Data mask or Data bus inversion on/off

RW

0

7:5

Bus_width

DDR bus width (16 or 32)

RW

0x0

4

CRC

CRC on/off

RW

0

3

ECC

ECC on/off

RW

0

2:0

DDRMODE

DDR3, DDR3L, DDR4, LPDDR3, LPDDR4 decode. "000 ddr3
001 ddr33L
010 ddr4
011 LPDDR3
100 LPDDR4"

RW

0x2

 

CFG_DDR_SGMII_PHY : DDRPHY_STARTUP

Address offset

0x008

Physical address

0x2000 7008

Instance

CFG_DDR_SGMII_PHY

Description

DDRPHY STARTUP register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:22

reserved3

Reserved

RW

0x000

21

DYNEN_APB_DECODER_PRESETS

Enable APB DECODER PRESET bit over rides

RW

1

20

DYNEN_APB_BANKCNTL

Enable APB BANKCNTL bit over rides

RW

0

19

DYNEN_APB_IO_CALIB

Enable APB IO CALIB bit over rides

RW

0

18

DYNEN_APB_CFM

Enable APB CFM bit over rides

RW

0

17

DYNEN_APB_PLL1

Enable APB PLL1 bit over rides

RW

0

16

DYNEN_APB_PLL0

Enable APB PLL0 bit over rides

RW

0

15:13

Reserved

Reserved

RO

0x0

12

DYNEN_SCB_BANKCNTL

Enable SCB BANKCNTL bit over rides

RW

0

11

DYNEN_SCB_IO_CALIB

Enable SCB IO CALIB bit over rides

RW

0

10

DYNEN_SCB_CFM

Enable SCB CFM bit over rides

RW

0

9

DYNEN_SCB_PLL1

Enable SCB PLL1 bit over rides

RW

0

8

DYNEN_SCB_PLL0

Enable SCB PLL0 bit over rides

RW

0

7:5

Reserved

Reserved

RO

0x0

4

Persist_DATA

Persist all DATA Dqa dn DQS bits. When 1:
write RPC_lp_persist_dqs to 1
write RPC_lp_persist_dqsp to 1
write RPC_lp_persist_dqsn to 1
else 0

RW

0

3

Persist_CLKOUT

Persist all clkout bits. When 1:
write RPC_lp_persist_clkp to 1
write RPC_lp_persist_clkn to 1
else 0

RW

0

2

PERSIST_ADD_CMD

Persit all Addcmd bits . When 1:
write RPC_lp_persist_addcmd to 1
else 0

RW

0

1

DATA_Lockdn

Data bits honor Lockdn clobal signal

RW

0

0

ADD_CMD_Lockdn

Addcmd bits honor Lockdn global signal

RW

0

 

CFG_DDR_SGMII_PHY : SPARE_0

Address offset

0x00C

Physical address

0x2000 700C

Instance

CFG_DDR_SGMII_PHY

Description

spare logic

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

Reserved

 

RO
Rreturns0s

0x0000

15:0

spare_0

Spare register bits

RW

0x0000

 

CFG_DDR_SGMII_PHY : SOFT_RESET_MAIN_PLL

Address offset

0x080

Physical address

0x2000 7080

Instance

CFG_DDR_SGMII_PHY

Description

This is a compulsory register for all SCB slaves and must be at the same offset in all slaves to facilitate global soft reset of all SCB registers with a single broadcast write from the SCB master.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

BLOCKID_MAIN_PLL

This returns the block type and chip location. (IO SCB bus only)

RO

0x0000

 

 

Read 0x0000

[block_address_main_pll]

 

15:9

Reserved

 

RO
Rreturns0s

0x00

8

PERIPH_MAIN_PLL

This asserts the functional reset of the block. It is asserted at power up. When written is stays asserted until written to 0.

WO

0

 

 

Write 0

[scb_periph_not_in_soft_reset_main_pll]

 

 

 

Write 1

[scb_periph_reset_main_pll]

 

7:2

Reserved

 

RO
Rreturns0s

0x00

1

V_MAP_MAIN_PLL

This when asserted resets all the register bits apart from the non-volatile registers@ the bit self clears. i.e. is similar to a W1P bit

WO

0

 

 

Write 0

[scb_v_regs_not_in_soft_reset_main_pll]

 

 

 

Write 1

[scb_v_regs_reset_main_pll]

 

0

NV_MAP_MAIN_PLL

This when asserted resets all the non-volatile register bits e.g. RW-P bits@ the bit self clears i.e. is similar to a W1P bit

WO

0

 

 

Write 0

[scb_nv_regs_not_in_soft_reset_main_pll]

 

 

 

Write 1

[scb_nv_regs_reset_main_pll]

 

 

CFG_DDR_SGMII_PHY : PLL_CTRL_MAIN

Address offset

0x084

Physical address

0x2000 7084

Instance

CFG_DDR_SGMII_PHY

Description

PLL control register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

Reserved

Status of PLL lock_b

RO

0

30

Reserved

 

RO

0

29

Reserved

pll unlock interrupt signal

RO

0

28

Reserved

pll lock interrupt signal

RO

0

27

Reserved

Enable pll unlock interrupt

RO

0

26

Reserved

Enable pll lock interrupt

RO

0

25

LOCK

Status of PLL lock

RO

0

24

LP_REQUIRES_LOCK

 

RW

0

23:20

Reserved

 

RO

0x0

19:16

Reserved

 

RO

0x0

15:13

Reserved

 

RO

0x0

12

Reserved

 

RO

1

11:8

Reserved

 

RO

0x0

7

Reserved

 

RO

1

6

REG_RFCLK_SEL

 

RW

0

5

REG_DIVQ3_EN

 

RW

1

4

REG_DIVQ2_EN

 

RW

1

3

REG_DIVQ1_EN

 

RW

1

2

REG_DIVQ0_EN

 

RW

1

1

REG_RFDIV_EN

 

RW

1

0

REG_POWERDOWN_B

 

RW

0

 

CFG_DDR_SGMII_PHY : PLL_REF_FB_MAIN

Address offset

0x088

Physical address

0x2000 7088

Instance

CFG_DDR_SGMII_PHY

Description

PLL reference and feedback registers

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:28

Reserved

 

RO

0x0

27:16

Reserved

 

RO

0x000

15:14

Reserved

 

RO

0x0

13:8

RFDIV

 

RW

0x01

7:4

Reserved

 

RO

0x0

3

Reserved

 

RO

0

2:1

Reserved

 

RO

0x0

0

Reserved

 

RO

0

 

CFG_DDR_SGMII_PHY : PLL_FRACN_MAIN

Address offset

0x08C

Physical address

0x2000 708C

Instance

CFG_DDR_SGMII_PHY

Description

PLL fractional register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:8

Reserved

 

RO

0x00 0000

7:2

Reserved

 

RO

0x00

1

Reserved

 

RO

0

0

Reserved

 

RO

0

 

CFG_DDR_SGMII_PHY : PLL_DIV_0_1_MAIN

Address offset

0x090

Physical address

0x2000 7090

Instance

CFG_DDR_SGMII_PHY

Description

PLL 0/1 division registers

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

Reserved

 

RO

0

30:24

POST1DIV

 

RW

0x08

23:22

Reserved

 

RO

0x0

21:19

Reserved

 

RO

0x0

18:16

VCO1PH_SEL

 

RO

0x0

15

Reserved

 

RO

0

14:8

POST0DIV

 

RW

0x02

7:6

Reserved

 

RO

0x0

5:3

Reserved

 

RO

0x0

2:0

VCO0PH_SEL

 

RO

0x0

 

CFG_DDR_SGMII_PHY : PLL_DIV_2_3_MAIN

Address offset

0x094

Physical address

0x2000 7094

Instance

CFG_DDR_SGMII_PHY

Description

PLL 2/3 division registers

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

Reserved

 

RO

0

30:24

POST3DIV

 

RW

0x14

23:22

Reserved

 

RO

0x0

21:19

Reserved

 

RO

0x0

18:16

VCO3PH_SEL

 

RO

0x0

15

Reserved

 

RO

0

14:8

POST2DIV

 

RW

0x08

7:6

Reserved

 

RO

0x0

5:3

Reserved

 

RO

0x0

2:0

VCO2PH_SEL

 

RO

0x0

 

CFG_DDR_SGMII_PHY : PLL_CTRL2_MAIN

Address offset

0x098

Physical address

0x2000 7098

Instance

CFG_DDR_SGMII_PHY

Description

PLL control register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:21

Reserved

 

RO

0x000

20:18

Reserved

 

RO

0x0

17

Reserved

 

RO

0

16:13

Reserved

 

RO

0x0

12:9

Reserved

 

RO

0x8

8:6

Reserved

 

RO

0x0

5

Reserved

 

RO

0

4

Reserved

 

RO

1

3:2

BWP

 

RW

0x2

1:0

BWI

 

RW

0x0

 

CFG_DDR_SGMII_PHY : PLL_CAL_MAIN

Address offset

0x09C

Physical address

0x2000 709C

Instance

CFG_DDR_SGMII_PHY

Description

PLL calibration register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:23

Reserved

 

RO

0x000

22:16

Reserved

 

RO

0x00

15

Reserved

 

RO

0

14:8

Reserved

 

RO

0x00

7:5

Reserved

 

RO

0x0

4

Reserved

 

RO

0

3

Reserved

 

RO

1

2:0

Reserved

 

RO

0x0

 

CFG_DDR_SGMII_PHY : PLL_PHADJ_MAIN

Address offset

0x0A0

Physical address

0x2000 70A0

Instance

CFG_DDR_SGMII_PHY

Description

PLL phase registers

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:15

Reserved

 

RO

0x0 0000

14

REG_LOADPHS_B

 

RW

0

13:11

REG_OUT3_PHSINIT

 

RW

0x0

10:8

REG_OUT2_PHSINIT

 

RW

0x0

7:5

REG_OUT1_PHSINIT

 

RW

0x0

4:2

REG_OUT0_PHSINIT

 

RW

0x0

1

Reserved

 

RO

0

0

Reserved

 

RO

1

 

CFG_DDR_SGMII_PHY : SSCG_REG_0_MAIN

Address offset

0x0A4

Physical address

0x2000 70A4

Instance

CFG_DDR_SGMII_PHY

Description

SSCG registers 0

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:30

Reserved

 

RO

0x0

29:6

Reserved

 

RO

0x00 0000

5:0

Reserved

 

RO

0x00

 

CFG_DDR_SGMII_PHY : SSCG_REG_1_MAIN

Address offset

0x0A8

Physical address

0x2000 70A8

Instance

CFG_DDR_SGMII_PHY

Description

SSCG registers 1

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:30

Reserved

 

RO

0x0

29:6

Reserved

 

RO

0x00 0000

5:1

Reserved

 

RO

0x05

0

Reserved

 

RO

0

 

CFG_DDR_SGMII_PHY : SSCG_REG_2_MAIN

Address offset

0x0AC

Physical address

0x2000 70AC

Instance

CFG_DDR_SGMII_PHY

Description

SSCG registers 2

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:24

Reserved

 

RO

0x00

23:12

Reserved

 

RO

0x000

11:0

INTIN

 

RW

0x030

 

CFG_DDR_SGMII_PHY : SSCG_REG_3_MAIN

Address offset

0x0B0

Physical address

0x2000 70B0

Instance

CFG_DDR_SGMII_PHY

Description

SSCG registers 3

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:23

Reserved

 

RO

0x000

22

Reserved

 

RO

0

21:20

Reserved

 

RO

0x0

19

Reserved

 

RO

0

18:11

Reserved

 

RO

0x00

10:3

Reserved

 

RO

0x00

2:1

Reserved

 

RO

0x0

0

Reserved

 

RO

1

 

CFG_DDR_SGMII_PHY : RPC_RESET_MAIN_PLL

Address offset

0x0B4

Physical address

0x2000 70B4

Instance

CFG_DDR_SGMII_PHY

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

soft_reset_periph_MAIN_PLL

RPC reset register

RW

0

 

CFG_DDR_SGMII_PHY : SOFT_RESET_IOSCB_PLL

Address offset

0x100

Physical address

0x2000 7100

Instance

CFG_DDR_SGMII_PHY

Description

This is a compulsory register for all SCB slaves and must be at the same offset in all slaves to facilitate global soft reset of all SCB registers with a single broadcast write from the SCB master.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

BLOCKID_IOSCB_PLL

This returns the block type and chip location. (IO SCB bus only)

RO

0x0000

 

 

Read 0x0000

[block_address_ioscb_pll]

 

15:9

Reserved

 

RO
Rreturns0s

0x00

8

PERIPH_IOSCB_PLL

This asserts the functional reset of the block. It is asserted at power up. When written is stays asserted until written to 0.

WO

0

 

 

Write 0

[scb_periph_not_in_soft_reset_ioscb_pll]

 

 

 

Write 1

[scb_periph_reset_ioscb_pll]

 

7:2

Reserved

 

RO
Rreturns0s

0x00

1

V_MAP_IOSCB_PLL

This when asserted resets all the register bits apart from the non-volatile registers@ the bit self clears. i.e. is similar to a W1P bit

WO

0

 

 

Write 0

[scb_v_regs_not_in_soft_reset_ioscb_pll]

 

 

 

Write 1

[scb_v_regs_reset_ioscb_pll]

 

0

NV_MAP_IOSCB_PLL

This when asserted resets all the non-volatile register bits e.g. RW-P bits@ the bit self clears i.e. is similar to a W1P bit

WO

0

 

 

Write 0

[scb_nv_regs_not_in_soft_reset_ioscb_pll]

 

 

 

Write 1

[scb_nv_regs_reset_ioscb_pll]

 

 

CFG_DDR_SGMII_PHY : PLL_CTRL_IOSCB

Address offset

0x104

Physical address

0x2000 7104

Instance

CFG_DDR_SGMII_PHY

Description

PLL control register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

Reserved

Status of PLL lock_b

RO

0

30

Reserved

 

RO

0

29

Reserved

pll unlock interrupt signal

RO

0

28

Reserved

pll lock interrupt signal

RO

0

27

Reserved

Enable pll unlock interrupt

RO

0

26

Reserved

Enable pll lock interrupt

RO

0

25

LOCK

Status of PLL lock

RO

0

24

LP_REQUIRES_LOCK

 

RW

0

23:20

Reserved

 

RO

0x0

19:16

Reserved

 

RO

0x0

15:13

Reserved

 

RO

0x0

12

Reserved

 

RO

1

11:8

Reserved

 

RO

0x0

7

Reserved

 

RO

1

6

REG_RFCLK_SEL

 

RW

0

5

REG_DIVQ3_EN

 

RW

1

4

REG_DIVQ2_EN

 

RW

1

3

REG_DIVQ1_EN

 

RW

1

2

REG_DIVQ0_EN

 

RW

1

1

REG_RFDIV_EN

 

RW

1

0

REG_POWERDOWN_B

 

RW

0

 

CFG_DDR_SGMII_PHY : PLL_REF_FB_IOSCB

Address offset

0x108

Physical address

0x2000 7108

Instance

CFG_DDR_SGMII_PHY

Description

PLL reference and feedback registers

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:28

Reserved

 

RO

0x0

27:16

Reserved

 

RO

0x000

15:14

Reserved

 

RO

0x0

13:8

RFDIV

 

RW

0x01

7:4

Reserved

 

RO

0x0

3

Reserved

 

RO

0

2:1

Reserved

 

RO

0x0

0

Reserved

 

RO

0

 

CFG_DDR_SGMII_PHY : PLL_FRACN_IOSCB

Address offset

0x10C

Physical address

0x2000 710C

Instance

CFG_DDR_SGMII_PHY

Description

PLL fractional register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:8

Reserved

 

RO

0x00 0000

7:2

Reserved

 

RO

0x00

1

Reserved

 

RO

0

0

Reserved

 

RO

0

 

CFG_DDR_SGMII_PHY : PLL_DIV_0_1_IOSCB

Address offset

0x110

Physical address

0x2000 7110

Instance

CFG_DDR_SGMII_PHY

Description

PLL 0/1 division registers

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

Reserved

 

RO

0

30:24

POST1DIV

 

RW

0x02

23:22

Reserved

 

RO

0x0

21:19

Reserved

 

RO

0x0

18:16

VCO1PH_SEL

 

RO

0x0

15

Reserved

 

RO

0

14:8

POST0DIV

 

RW

0x01

7:6

Reserved

 

RO

0x0

5:3

Reserved

 

RO

0x0

2:0

VCO0PH_SEL

 

RO

0x0

 

CFG_DDR_SGMII_PHY : PLL_DIV_2_3_IOSCB

Address offset

0x114

Physical address

0x2000 7114

Instance

CFG_DDR_SGMII_PHY

Description

PLL 2/3 division registers

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

Reserved

 

RO

0

30:24

POST3DIV

 

RW

0x01

23:22

Reserved

 

RO

0x0

21:19

Reserved

 

RO

0x0

18:16

VCO3PH_SEL

 

RO

0x0

15

Reserved

 

RO

0

14:8

POST2DIV

 

RW

0x01

7:6

Reserved

 

RO

0x0

5:3

Reserved

 

RO

0x0

2:0

VCO2PH_SEL

 

RO

0x0

 

CFG_DDR_SGMII_PHY : PLL_CTRL2_IOSCB

Address offset

0x118

Physical address

0x2000 7118

Instance

CFG_DDR_SGMII_PHY

Description

PLL control register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:21

Reserved

 

RO

0x000

20:18

Reserved

 

RO

0x0

17

Reserved

 

RO

0

16:13

Reserved

 

RO

0x0

12:9

Reserved

 

RO

0x8

8:6

Reserved

 

RO

0x0

5

Reserved

 

RO

0

4

Reserved

 

RO

1

3:2

BWP

 

RW

0x2

1:0

BWI

 

RW

0x0

 

CFG_DDR_SGMII_PHY : PLL_CAL_IOSCB

Address offset

0x11C

Physical address

0x2000 711C

Instance

CFG_DDR_SGMII_PHY

Description

PLL calibration register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:23

Reserved

 

RO

0x000

22:16

Reserved

 

RO

0x00

15

Reserved

 

RO

0

14:8

Reserved

 

RO

0x00

7:5

Reserved

 

RO

0x0

4

Reserved

 

RO

0

3

Reserved

 

RO

1

2:0

Reserved

 

RO

0x0

 

CFG_DDR_SGMII_PHY : PLL_PHADJ_IOSCB

Address offset

0x120

Physical address

0x2000 7120

Instance

CFG_DDR_SGMII_PHY

Description

PLL phase registers

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:15

Reserved

 

RO

0x0 0000

14

REG_LOADPHS_B

 

RW

1

13:11

REG_OUT3_PHSINIT

 

RW

0x0

10:8

REG_OUT2_PHSINIT

 

RW

0x0

7:5

REG_OUT1_PHSINIT

 

RW

0x0

4:2

REG_OUT0_PHSINIT

 

RW

0x0

1

Reserved

 

RO

0

0

Reserved

 

RO

1

 

CFG_DDR_SGMII_PHY : SSCG_REG_0_IOSCB

Address offset

0x124

Physical address

0x2000 7124

Instance

CFG_DDR_SGMII_PHY

Description

SSCG registers 0

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:30

Reserved

 

RO

0x0

29:6

Reserved

 

RO

0x00 0000

5:0

Reserved

 

RO

0x00

 

CFG_DDR_SGMII_PHY : SSCG_REG_1_IOSCB

Address offset

0x128

Physical address

0x2000 7128

Instance

CFG_DDR_SGMII_PHY

Description

SSCG registers 1

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:30

Reserved

 

RO

0x0

29:6

Reserved

 

RO

0x00 0000

5:1

Reserved

 

RO

0x05

0

Reserved

 

RO

0

 

CFG_DDR_SGMII_PHY : SSCG_REG_2_IOSCB

Address offset

0x12C

Physical address

0x2000 712C

Instance

CFG_DDR_SGMII_PHY

Description

SSCG registers 2

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:24

Reserved

 

RO

0x00

23:12

Reserved

 

RO

0x000

11:0

INTIN

 

RW

0x020

 

CFG_DDR_SGMII_PHY : SSCG_REG_3_IOSCB

Address offset

0x130

Physical address

0x2000 7130

Instance

CFG_DDR_SGMII_PHY

Description

SSCG registers 3

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:23

Reserved

 

RO

0x000

22

Reserved

 

RO

0

21:20

Reserved

 

RO

0x0

19

Reserved

 

RO

0

18:11

Reserved

 

RO

0x00

10:3

Reserved

 

RO

0x00

2:1

Reserved

 

RO

0x0

0

Reserved

 

RO

1

 

CFG_DDR_SGMII_PHY : RPC_RESET_IOSCB

Address offset

0x134

Physical address

0x2000 7134

Instance

CFG_DDR_SGMII_PHY

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

soft_reset_periph_IOSCB

RPC reset register

RW

0

 

CFG_DDR_SGMII_PHY : SOFT_RESET_BANK_CTRL

Address offset

0x180

Physical address

0x2000 7180

Instance

CFG_DDR_SGMII_PHY

Description

This is a compulsory register for all SCB slaves and must be at the same offset in all slaves to facilitate global soft reset of all SCB registers with a single broadcast write from the SCB master.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

BLOCKID_BANK_CTRL

This returns the block type and chip location. (IO SCB bus only)

RO

0x0000

 

 

Read 0x0000

[block_address_bank_ctrl]

 

15:9

Reserved

 

RO
Rreturns0s

0x00

8

PERIPH_BANK_CTRL

This asserts the functional reset of the block. It is asserted at power up. When written is stays asserted until written to 0.

WO

0

 

 

Write 0

[scb_periph_not_in_soft_reset_bank_ctrl]

 

 

 

Write 1

[scb_periph_reset_bank_ctrl]

 

7:2

Reserved

 

RO
Rreturns0s

0x00

1

V_MAP_BANK_CTRL

This when asserted resets all the register bits apart from the non-volatile registers@ the bit self clears. i.e. is similar to a W1P bit

WO

0

 

 

Write 0

[scb_v_regs_not_in_soft_reset_bank_ctrl]

 

 

 

Write 1

[scb_v_regs_reset_bank_ctrl]

 

0

NV_MAP_BANK_CTRL

This when asserted resets all the non-volatile register bits e.g. RW-P bits@ the bit self clears i.e. is similar to a W1P bit

WO

0

 

 

Write 0

[scb_nv_regs_not_in_soft_reset_bank_ctrl]

 

 

 

Write 1

[scb_nv_regs_reset_bank_ctrl]

 

 

CFG_DDR_SGMII_PHY : DPC_BITS

Address offset

0x184

Physical address

0x2000 7184

Instance

CFG_DDR_SGMII_PHY

Description

DPC Bits Register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:20

Reserved

 

RO

0x000

19

dpc_move_en_v

enable dynamic control of vrgen circuit for ADDCMD pins

RW

0

18

dpc_vrgen_en_v

enable vref generator for ADDCMD pins

RW

1

17:12

dpc_vrgen_v

reference voltage ratio setting for ADDCMD pins

RW

0x1C

11

dpc_move_en_h

enable dynamic control of vrgen circuit for DQ/DQS pins

RW

0

10

dpc_vrgen_en_h

enable vref generator for DQ/DQS pins

RW

1

9:4

dpc_vrgen_h

reference voltage ratio setting for DQ/DQS pins

RW

0x1C

3:0

dpc_vs

bank voltage select for pvt calibration

RW

0x3

 

CFG_DDR_SGMII_PHY : BANK_STATUS

Address offset

0x188

Physical address

0x2000 7188

Instance

CFG_DDR_SGMII_PHY

Description

Bank Complete Registers

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1

sro_ioen_bnk_b

Bank power on complete (active low for polling)

RO

0

0

sro_calib_status_b

Bank calibration complete (active low for polling)

RO

0

 

CFG_DDR_SGMII_PHY : RPC_RESET_BANK_CTRL

Address offset

0x18C

Physical address

0x2000 718C

Instance

CFG_DDR_SGMII_PHY

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

soft_reset_periph_BANK_CTRL

RPC reset register

RW

0

 

CFG_DDR_SGMII_PHY : SOFT_RESET_IOCALIB

Address offset

0x200

Physical address

0x2000 7200

Instance

CFG_DDR_SGMII_PHY

Description

This is a compulsory register for all SCB slaves and must be at the same offset in all slaves to facilitate global soft reset of all SCB registers with a single broadcast write from the SCB master.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

BLOCKID_IOCALIB

This returns the block type and chip location. (IO SCB bus only)

RO

0x0000

 

 

Read 0x0000

[block_address_iocalib]

 

15:9

Reserved

 

RO
Rreturns0s

0x00

8

PERIPH_IOCALIB

This asserts the functional reset of the block. It is asserted at power up. When written is stays asserted until written to 0.

WO

0

 

 

Write 0

[scb_periph_not_in_soft_reset_iocalib]

 

 

 

Write 1

[scb_periph_reset_iocalib]

 

7:2

Reserved

 

RO
Rreturns0s

0x00

1

V_MAP_IOCALIB

This when asserted resets all the register bits apart from the non-volatile registers@ the bit self clears. i.e. is similar to a W1P bit

WO

0

 

 

Write 0

[scb_v_regs_not_in_soft_reset_iocalib]

 

 

 

Write 1

[scb_v_regs_reset_iocalib]

 

0

NV_MAP_IOCALIB

This when asserted resets all the non-volatile register bits e.g. RW-P bits@ the bit self clears i.e. is similar to a W1P bit

WO

0

 

 

Write 0

[scb_nv_regs_not_in_soft_reset_iocalib]

 

 

 

Write 1

[scb_nv_regs_reset_iocalib]

 

 

CFG_DDR_SGMII_PHY : IOC_REG0

Address offset

0x204

Physical address

0x2000 7204

Instance

CFG_DDR_SGMII_PHY

Description

IO calib control register0

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:19

Reserved

 

RO

0x0000

18

Reserved

 

RO

0

17

Reserved

 

RO

0

16

Reserved

 

RO

0

15

Reserved

 

RO

1

14

reg_calib_lock

 

RW

0

13

reg_calib_start

 

RW

0

12

Reserved

 

RO

0

11:6

Reserved

 

RO

0x00

5:0

Reserved

 

RO

0x00

 

CFG_DDR_SGMII_PHY : IOC_REG1

Address offset

0x208

Physical address

0x2000 7208

Instance

CFG_DDR_SGMII_PHY

Description

IO calib control register1

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:8

Reserved

 

RO

0x00 0000

7

Reserved

 

RO

0

6

Reserved

 

RO

0

5

Reserved

 

RO

0

4

sro_ioen_out

 

RO

0

3

sro_calib_intrpt

 

RO

0

2

sro_calib_status

 

RO

0

1

Reserved

 

RO

0

0

Reserved

 

RO

0

 

CFG_DDR_SGMII_PHY : IOC_REG2

Address offset

0x20C

Physical address

0x2000 720C

Instance

CFG_DDR_SGMII_PHY

Description

IO calib control register2

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:29

Reserved

 

RO

0x0

28

Reserved

 

RO

0

27:21

sro_ref_ncode

 

RO

0x00

20:14

sro_ref_pcode

 

RO

0x00

13:7

sro_ncode

 

RO

0x00

6:0

sro_pcode

 

RO

0x00

 

CFG_DDR_SGMII_PHY : IOC_REG3

Address offset

0x210

Physical address

0x2000 7210

Instance

CFG_DDR_SGMII_PHY

Description

IO calib control register3

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:23

Reserved

 

RO

0x000

22

Reserved

 

RO

0

21

Reserved

 

RO

0

20

Reserved

 

RO

0

19

Reserved

 

RO

0

18

Reserved

 

RO

0

17:12

Reserved

 

RO

0x00

11

Reserved

 

RO

0

10:5

Reserved

 

RO

0x00

4:0

Reserved

 

RO

0x00

 

CFG_DDR_SGMII_PHY : IOC_REG4

Address offset

0x214

Physical address

0x2000 7214

Instance

CFG_DDR_SGMII_PHY

Description

IO calib control register4

Type

RO

 

Bits

Field Name

Description

Type

Reset

31

Reserved

 

RO

0

30

Reserved

 

RO

0

29

Reserved

 

RO

0

28

Reserved

 

RO

0

27

Reserved

 

RO

0

26

Reserved

 

RO

0

25

Reserved

 

RO

0

24

Reserved

 

RO

0

23:18

Reserved

 

RO

0x00

17:12

Reserved

 

RO

0x00

11:6

Reserved

 

RO

0x00

5:0

Reserved

 

RO

0x00

 

CFG_DDR_SGMII_PHY : IOC_REG5

Address offset

0x218

Physical address

0x2000 7218

Instance

CFG_DDR_SGMII_PHY

Description

IO calib control register5

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:30

Reserved

 

RO

0x0

29:24

sro_slewf

 

RO

0x00

23:18

sro_slewr

 

RO

0x00

17:6

sro_ref_slewf

 

RO

0x000

5:0

sro_ref_slewr

 

RO

0x00

 

CFG_DDR_SGMII_PHY : IOC_REG6

Address offset

0x21C

Physical address

0x2000 721C

Instance

CFG_DDR_SGMII_PHY

Description

IO calibr control resgister6

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO

0x0000 0000

2:1

reg_calib_clkdiv

 

RW

0x2

0

reg_calib_reset

 

RW

1

 

CFG_DDR_SGMII_PHY : RPC_RESET_IOCALIB

Address offset

0x220

Physical address

0x2000 7220

Instance

CFG_DDR_SGMII_PHY

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

soft_reset_periph_IOCALIB

RPC reset register

RW

0

 

CFG_DDR_SGMII_PHY : RPC_calib

Address offset

0x224

Physical address

0x2000 7224

Instance

CFG_DDR_SGMII_PHY

Description

RPC calib register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1

lock_pvt

 

RW

0

0

start_pvt

 

RW

0

 

CFG_DDR_SGMII_PHY : SOFT_RESET_CFM

Address offset

0x280

Physical address

0x2000 7280

Instance

CFG_DDR_SGMII_PHY

Description

This is a compulsory register for all SCB slaves and must be at the same offset in all slaves to facilitate global soft reset of all SCB registers with a single broadcast write from the SCB master.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

BLOCKID_CFM

This returns the block type and chip location. (IO SCB bus only)

RO

0x0000

 

 

Read 0x0000

[block_address_cfm]

 

15:9

Reserved

 

RO
Rreturns0s

0x00

8

PERIPH_CFM

This asserts the functional reset of the block. It is asserted at power up. When written is stays asserted until written to 0.

WO

0

 

 

Write 0

[scb_periph_not_in_soft_reset_cfm]

 

 

 

Write 1

[scb_periph_reset_cfm]

 

7:2

Reserved

 

RO
Rreturns0s

0x00

1

V_MAP_CFM

This when asserted resets all the register bits apart from the non-volatile registers@ the bit self clears. i.e. is similar to a W1P bit

WO

0

 

 

Write 0

[scb_v_regs_not_in_soft_reset_cfm]

 

 

 

Write 1

[scb_v_regs_reset_cfm]

 

0

NV_MAP_CFM

This when asserted resets all the non-volatile register bits e.g. RW-P bits@ the bit self clears i.e. is similar to a W1P bit

WO

0

 

 

Write 0

[scb_nv_regs_not_in_soft_reset_cfm]

 

 

 

Write 1

[scb_nv_regs_reset_cfm]

 

 

CFG_DDR_SGMII_PHY : BCLKMUX

Address offset

0x284

Physical address

0x2000 7284

Instance

CFG_DDR_SGMII_PHY

Description

BCLK mux selections

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:30

Reserved

 

RO

0x0

29:25

bclk5_sel

 

RW

0x00

24:20

bclk4_sel

 

RW

0x00

19:15

bclk3_sel

 

RW

0x00

14:10

bclk2_sel

 

RW

0x00

9:5

bclk1_sel

 

RW

0x10

4:0

bclk0_sel

 

RW

0x08

 

CFG_DDR_SGMII_PHY : PLL_CKMUX

Address offset

0x288

Physical address

0x2000 7288

Instance

CFG_DDR_SGMII_PHY

Description

PLL RF clk mux selections

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:15

Reserved

 

RO

0x0 0000

14:10

pll1_fdr_sel

 

RW

0x00

9:8

pll1_rfclk1_sel

 

RW

0x0

7:6

pll1_rfclk0_sel

 

RW

0x0

5:4

pll0_rfclk1_sel

 

RW

0x0

3:2

pll0_rfclk0_sel

 

RW

0x1

1:0

clk_in_mac_tsu

 

RW

0x1

 

CFG_DDR_SGMII_PHY : MSSCLKMUX

Address offset

0x28C

Physical address

0x2000 728C

Instance

CFG_DDR_SGMII_PHY

Description

MSS Clock mux selections

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:5

Reserved

 

RO

0x000 0000

4

clk_standby_sel

 

RW

0

3:2

mssclk_mux_md

 

RW

0x0

1:0

mssclk_mux_sel

 

RW

0x0

 

CFG_DDR_SGMII_PHY : SPARE0

Address offset

0x290

Physical address

0x2000 7290

Instance

CFG_DDR_SGMII_PHY

Description

spare logic

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

spare0

 

RW

0x0000 0000

 

CFG_DDR_SGMII_PHY : FMETER_ADDR

Address offset

0x294

Physical address

0x2000 7294

Instance

CFG_DDR_SGMII_PHY

Description

Frequency_meter_address_selections

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:6

Reserved

 

RO

0x000 0000

5:2

Reserved

 

RO

0x0

1:0

Reserved

 

RO

0x0

 

CFG_DDR_SGMII_PHY : FMETER_DATAW

Address offset

0x298

Physical address

0x2000 7298

Instance

CFG_DDR_SGMII_PHY

Description

Frequency_meter_data_write

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:25

Reserved

 

RO

0x00

24

Reserved

 

RO

0

23:0

Reserved

 

RO

0x00 0000

 

CFG_DDR_SGMII_PHY : FMETER_DATAR

Address offset

0x29C

Physical address

0x2000 729C

Instance

CFG_DDR_SGMII_PHY

Description

Frequency_meter_data_read

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:24

Reserved

 

RO

0x00

23:0

Reserved

 

RO

0x00 0000

 

CFG_DDR_SGMII_PHY : TEST_CTRL

Address offset

0x2A0

Physical address

0x2000 72A0

Instance

CFG_DDR_SGMII_PHY

Description

Test MUX Controls

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO

0x0 0000

11:7

Reserved

 

RO

0x00

6

Reserved

 

RO

0

5:1

Reserved

 

RO

0x00

0

Reserved

 

RO

0

 

CFG_DDR_SGMII_PHY : RPC_RESET_CFM

Address offset

0x2A4

Physical address

0x2000 72A4

Instance

CFG_DDR_SGMII_PHY

Description

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

soft_reset_periph_CFM

RPC reset register

RW

0

 

CFG_DDR_SGMII_PHY : SOFT_RESET_DECODER_DRIVER

Address offset

0x300

Physical address

0x2000 7300

Instance

CFG_DDR_SGMII_PHY

Description

This is a compulsory register for all SCB slaves and must be at the same offset in all slaves to facilitate global soft reset of all SCB registers with a single broadcast write from the SCB master.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

BLOCKID_DECODER_DRIVER

This returns the block type and chip location. (IO SCB bus only)

RO

0x0000

 

 

Read 0x0000

[block_address_decoder_driver]

 

15:9

Reserved

 

RO
Rreturns0s

0x00

8

PERIPH_DECODER_DRIVER

This asserts the functional reset of the block. It is asserted at power up. When written is stays asserted until written to 0.

WO

0

 

 

Write 0

[scb_periph_not_in_soft_reset_decoder_driver]

 

 

 

Write 1

[scb_periph_reset_decoder_driver]

 

7:2

Reserved

 

RO
Rreturns0s

0x00

1

V_MAP_DECODER_DRIVER

This when asserted resets all the register bits apart from the non-volatile registers, the bit self clears. i.e. is similar to a W1P bit

WO

0

 

 

Write 0

[scb_v_regs_not_in_soft_reset_decoder_driver]

 

 

 

Write 1

[scb_v_regs_reset_decoder_driver]

 

0

NV_MAP_DECODER_DRIVER

This when asserted resets all the non-volatile register bits e.g. RW-P bits, the bit self clears i.e. is similar to a W1P bit

WO

0

 

 

Write 0

[scb_nv_regs_not_in_soft_reset_decoder_driver]

 

 

 

Write 1

[scb_nv_regs_reset_decoder_driver]

 

 

CFG_DDR_SGMII_PHY : RPC1_DRV

Address offset

0x304

Physical address

0x2000 7304

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3:0

drv_addcmd

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC2_DRV

Address offset

0x308

Physical address

0x2000 7308

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3:0

drv_clk

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC3_DRV

Address offset

0x30C

Physical address

0x2000 730C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3:0

drv_dq

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC4_DRV

Address offset

0x310

Physical address

0x2000 7310

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3:0

drv_dqs

 

RW

0x0

 

CFG_DDR_SGMII_PHY : SOFT_RESET_DECODER_ODT

Address offset

0x380

Physical address

0x2000 7380

Instance

CFG_DDR_SGMII_PHY

Description

This is a compulsory register for all SCB slaves and must be at the same offset in all slaves to facilitate global soft reset of all SCB registers with a single broadcast write from the SCB master.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

BLOCKID_DECODER_ODT

This returns the block type and chip location. (IO SCB bus only)

RO

0x0000

 

 

Read 0x0000

[block_address_decoder_odt]

 

15:9

Reserved

 

RO
Rreturns0s

0x00

8

PERIPH_DECODER_ODT

This asserts the functional reset of the block. It is asserted at power up. When written is stays asserted until written to 0.

WO

0

 

 

Write 0

[scb_periph_not_in_soft_reset_decoder_odt]

 

 

 

Write 1

[scb_periph_reset_decoder_odt]

 

7:2

Reserved

 

RO
Rreturns0s

0x00

1

V_MAP_DECODER_ODT

This when asserted resets all the register bits apart from the non-volatile registers, the bit self clears. i.e. is similar to a W1P bit

WO

0

 

 

Write 0

[scb_v_regs_not_in_soft_reset_decoder_odt]

 

 

 

Write 1

[scb_v_regs_reset_decoder_odt]

 

0

NV_MAP_DECODER_ODT

This when asserted resets all the non-volatile register bits e.g. RW-P bits, the bit self clears i.e. is similar to a W1P bit

WO

0

 

 

Write 0

[scb_nv_regs_not_in_soft_reset_decoder_odt]

 

 

 

Write 1

[scb_nv_regs_reset_decoder_odt]

 

 

CFG_DDR_SGMII_PHY : RPC1_ODT

Address offset

0x384

Physical address

0x2000 7384

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3:0

odt_addcmd

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC2_ODT

Address offset

0x388

Physical address

0x2000 7388

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3:0

odt_clk

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC3_ODT

Address offset

0x38C

Physical address

0x2000 738C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3:0

odt_dq

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC4_ODT

Address offset

0x390

Physical address

0x2000 7390

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3:0

odt_dqs

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC5_ODT

Address offset

0x394

Physical address

0x2000 7394

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

odt_dyn_sel_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC6_ODT

Address offset

0x398

Physical address

0x2000 7398

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

odt_dyn_sel_data

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC7_ODT

Address offset

0x39C

Physical address

0x2000 739C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

odt_static_addcmd

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC8_ODT

Address offset

0x3A0

Physical address

0x2000 73A0

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

odt_static_clkn

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC9_ODT

Address offset

0x3A4

Physical address

0x2000 73A4

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

odt_static_clkp

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC10_ODT

Address offset

0x3A8

Physical address

0x2000 73A8

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

odt_static_dq

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC11_ODT

Address offset

0x3AC

Physical address

0x2000 73AC

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

odt_static_dqs

 

RW

0x0

 

CFG_DDR_SGMII_PHY : SOFT_RESET_DECODER_IO

Address offset

0x400

Physical address

0x2000 7400

Instance

CFG_DDR_SGMII_PHY

Description

This is a compulsory register for all SCB slaves and must be at the same offset in all slaves to facilitate global soft reset of all SCB registers with a single broadcast write from the SCB master.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

BLOCKID_DECODER_IO

This returns the block type and chip location. (IO SCB bus only)

RO

0x0000

 

 

Read 0x0000

[block_address_decoder_io]

 

15:9

Reserved

 

RO
Rreturns0s

0x00

8

PERIPH_DECODER_IO

This asserts the functional reset of the block. It is asserted at power up. When written is stays asserted until written to 0.

WO

0

 

 

Write 0

[scb_periph_not_in_soft_reset_decoder_io]

 

 

 

Write 1

[scb_periph_reset_decoder_io]

 

7:2

Reserved

 

RO
Rreturns0s

0x00

1

V_MAP_DECODER_IO

This when asserted resets all the register bits apart from the non-volatile registers, the bit self clears. i.e. is similar to a W1P bit

WO

0

 

 

Write 0

[scb_v_regs_not_in_soft_reset_decoder_io]

 

 

 

Write 1

[scb_v_regs_reset_decoder_io]

 

0

NV_MAP_DECODER_IO

This when asserted resets all the non-volatile register bits e.g. RW-P bits, the bit self clears i.e. is similar to a W1P bit

WO

0

 

 

Write 0

[scb_nv_regs_not_in_soft_reset_decoder_io]

 

 

 

Write 1

[scb_nv_regs_reset_decoder_io]

 

 

CFG_DDR_SGMII_PHY : OVRT1

Address offset

0x404

Physical address

0x2000 7404

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

drv_addcmd0

 

RW

0x000

 

CFG_DDR_SGMII_PHY : OVRT2

Address offset

0x408

Physical address

0x2000 7408

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

drv_addcmd1

 

RW

0x000

 

CFG_DDR_SGMII_PHY : OVRT3

Address offset

0x40C

Physical address

0x2000 740C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

drv_addcmd2

 

RW

0x000

 

CFG_DDR_SGMII_PHY : OVRT4

Address offset

0x410

Physical address

0x2000 7410

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

drv_data0

 

RW

0x000

 

CFG_DDR_SGMII_PHY : OVRT5

Address offset

0x414

Physical address

0x2000 7414

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

drv_data1

 

RW

0x000

 

CFG_DDR_SGMII_PHY : OVRT6

Address offset

0x418

Physical address

0x2000 7418

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

drv_data2

 

RW

0x000

 

CFG_DDR_SGMII_PHY : OVRT7

Address offset

0x41C

Physical address

0x2000 741C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

drv_data3

 

RW

0x000

 

CFG_DDR_SGMII_PHY : OVRT8

Address offset

0x420

Physical address

0x2000 7420

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

drv_ecc

 

RW

0x000

 

CFG_DDR_SGMII_PHY : OVRT9

Address offset

0x424

Physical address

0x2000 7424

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

en_addcmd0

 

RW

0x000

 

CFG_DDR_SGMII_PHY : OVRT10

Address offset

0x428

Physical address

0x2000 7428

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

en_addcmd1

 

RW

0x000

 

CFG_DDR_SGMII_PHY : OVRT11

Address offset

0x42C

Physical address

0x2000 742C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

en_addcmd2

 

RW

0x000

 

CFG_DDR_SGMII_PHY : OVRT12

Address offset

0x430

Physical address

0x2000 7430

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

en_data0

 

RW

0x000

 

CFG_DDR_SGMII_PHY : OVRT13

Address offset

0x434

Physical address

0x2000 7434

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

en_data1

 

RW

0x000

 

CFG_DDR_SGMII_PHY : OVRT14

Address offset

0x438

Physical address

0x2000 7438

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

en_data2

 

RW

0x000

 

CFG_DDR_SGMII_PHY : OVRT15

Address offset

0x43C

Physical address

0x2000 743C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

en_data3

 

RW

0x000

 

CFG_DDR_SGMII_PHY : OVRT16

Address offset

0x440

Physical address

0x2000 7440

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

en_ecc

 

RW

0x000

 

CFG_DDR_SGMII_PHY : RPC17

Address offset

0x444

Physical address

0x2000 7444

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

bclk_sel_ac

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC18

Address offset

0x448

Physical address

0x2000 7448

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:9

Reserved

 

RO
Rreturns0s

0x00 0000

8:0

bclk_sel_addcmd

 

RW

0x000

 

CFG_DDR_SGMII_PHY : RPC19

Address offset

0x44C

Physical address

0x2000 744C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

bclk_sel_clkn

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC20

Address offset

0x450

Physical address

0x2000 7450

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

bclk_sel_clkp

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC21

Address offset

0x454

Physical address

0x2000 7454

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:9

Reserved

 

RO
Rreturns0s

0x00 0000

8:0

bclk_sel_data

 

RW

0x000

 

CFG_DDR_SGMII_PHY : RPC22

Address offset

0x458

Physical address

0x2000 7458

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

bclk_sel_dq

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC23

Address offset

0x45C

Physical address

0x2000 745C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

bclk_sel_dqsn

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC24

Address offset

0x460

Physical address

0x2000 7460

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

bclk_sel_dqsp

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC25

Address offset

0x464

Physical address

0x2000 7464

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

cdr_md_addcmd

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC26

Address offset

0x468

Physical address

0x2000 7468

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

cdr_md_data

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC27

Address offset

0x46C

Physical address

0x2000 746C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

clk_md_addcmd

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC28

Address offset

0x470

Physical address

0x2000 7470

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

clk_sel_addcmd

 

RW

0x000

 

CFG_DDR_SGMII_PHY : RPC29

Address offset

0x474

Physical address

0x2000 7474

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

clk_sel_data

 

RW

0x000

 

CFG_DDR_SGMII_PHY : RPC30

Address offset

0x478

Physical address

0x2000 7478

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

code_sel_addcmd

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC31

Address offset

0x47C

Physical address

0x2000 747C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

code_sel_data

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC32

Address offset

0x480

Physical address

0x2000 7480

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

comp_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC33

Address offset

0x484

Physical address

0x2000 7484

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

comp_clkn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC34

Address offset

0x488

Physical address

0x2000 7488

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

comp_clkp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC35

Address offset

0x48C

Physical address

0x2000 748C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

comp_dq

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC36

Address offset

0x490

Physical address

0x2000 7490

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

comp_dqsn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC37

Address offset

0x494

Physical address

0x2000 7494

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

comp_dqsp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC38

Address offset

0x498

Physical address

0x2000 7498

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

divclk_sel_addcmd

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC39

Address offset

0x49C

Physical address

0x2000 749C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

divclk_sel_data

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC40

Address offset

0x4A0

Physical address

0x2000 74A0

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

div_addcmd

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC41

Address offset

0x4A4

Physical address

0x2000 74A4

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

div_data

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC42

Address offset

0x4A8

Physical address

0x2000 74A8

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

dly_md_addcmd

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC43

Address offset

0x4AC

Physical address

0x2000 74AC

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

dly_md_clkn

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC44

Address offset

0x4B0

Physical address

0x2000 74B0

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

dly_md_clkp

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC45

Address offset

0x4B4

Physical address

0x2000 74B4

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

dly_md_dq

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC46

Address offset

0x4B8

Physical address

0x2000 74B8

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

dly_md_dqsn

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC47

Address offset

0x4BC

Physical address

0x2000 74BC

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

dly_md_dqsp

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC48

Address offset

0x4C0

Physical address

0x2000 74C0

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

dqs_md_data

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC49

Address offset

0x4C4

Physical address

0x2000 74C4

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

dynen_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC50

Address offset

0x4C8

Physical address

0x2000 74C8

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

dynen_data

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC51

Address offset

0x4CC

Physical address

0x2000 74CC

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

dynen_soft_reset_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC52

Address offset

0x4D0

Physical address

0x2000 74D0

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

dynen_soft_reset_data

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC53

Address offset

0x4D4

Physical address

0x2000 74D4

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

edgedet_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC54

Address offset

0x4D8

Physical address

0x2000 74D8

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

edgedet_clkn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC55

Address offset

0x4DC

Physical address

0x2000 74DC

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

edgedet_clkp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC56

Address offset

0x4E0

Physical address

0x2000 74E0

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

edgedet_dq

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC57

Address offset

0x4E4

Physical address

0x2000 74E4

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

edgedet_dqsn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC58

Address offset

0x4E8

Physical address

0x2000 74E8

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

edgedet_dqsp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC59

Address offset

0x4EC

Physical address

0x2000 74EC

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

eyewidth_addcmd

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC60

Address offset

0x4F0

Physical address

0x2000 74F0

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

eyewidth_clkn

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC61

Address offset

0x4F4

Physical address

0x2000 74F4

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

eyewidth_clkp

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC62

Address offset

0x4F8

Physical address

0x2000 74F8

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

eyewidth_dq

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC63

Address offset

0x4FC

Physical address

0x2000 74FC

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

eyewidth_dqsn

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC64

Address offset

0x500

Physical address

0x2000 7500

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

eyewidth_dqsp

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC65

Address offset

0x504

Physical address

0x2000 7504

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

eyewidth_sel_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC66

Address offset

0x508

Physical address

0x2000 7508

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

eyewidth_sel_clkn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC67

Address offset

0x50C

Physical address

0x2000 750C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

eyewidth_sel_clkp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC68

Address offset

0x510

Physical address

0x2000 7510

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

eyewidth_sel_dq

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC69

Address offset

0x514

Physical address

0x2000 7514

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

eyewidth_sel_dqsn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC70

Address offset

0x518

Physical address

0x2000 7518

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

eyewidth_sel_dqsp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC71

Address offset

0x51C

Physical address

0x2000 751C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

eye_en_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC72

Address offset

0x520

Physical address

0x2000 7520

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

eye_en_clkn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC73

Address offset

0x524

Physical address

0x2000 7524

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

eye_en_clkp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC74

Address offset

0x528

Physical address

0x2000 7528

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

eye_en_dq

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC75

Address offset

0x52C

Physical address

0x2000 752C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

eye_en_dqsn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC76

Address offset

0x530

Physical address

0x2000 7530

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

eye_en_dqsp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC77

Address offset

0x534

Physical address

0x2000 7534

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

eye_sdr_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC78

Address offset

0x538

Physical address

0x2000 7538

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

eye_sdr_clkn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC79

Address offset

0x53C

Physical address

0x2000 753C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

eye_sdr_clkp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC80

Address offset

0x540

Physical address

0x2000 7540

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

eye_sdr_dq

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC81

Address offset

0x544

Physical address

0x2000 7544

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

eye_sdr_dqsn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC82

Address offset

0x548

Physical address

0x2000 7548

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

eye_sdr_dqsp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC83

Address offset

0x54C

Physical address

0x2000 754C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

fifowe_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC84

Address offset

0x550

Physical address

0x2000 7550

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

fifowe_clkn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC85

Address offset

0x554

Physical address

0x2000 7554

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

fifowe_clkp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC86

Address offset

0x558

Physical address

0x2000 7558

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

fifowe_dq

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC87

Address offset

0x55C

Physical address

0x2000 755C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

fifowe_dqsn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC88

Address offset

0x560

Physical address

0x2000 7560

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

fifowe_dqsp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC89

Address offset

0x564

Physical address

0x2000 7564

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

fifo_en_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC90

Address offset

0x568

Physical address

0x2000 7568

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

fifo_en_data

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC91

Address offset

0x56C

Physical address

0x2000 756C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

fifo_run_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC92

Address offset

0x570

Physical address

0x2000 7570

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

fifo_run_data

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC93

Address offset

0x574

Physical address

0x2000 7574

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

gsr_disable_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC94

Address offset

0x578

Physical address

0x2000 7578

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

gsr_disable_data

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC95

Address offset

0x57C

Physical address

0x2000 757C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

ibufmd_addcmd

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC96

Address offset

0x580

Physical address

0x2000 7580

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

ibufmd_clk

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC97

Address offset

0x584

Physical address

0x2000 7584

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

ibufmd_dq

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC98

Address offset

0x588

Physical address

0x2000 7588

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

ibufmd_dqs

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC99

Address offset

0x58C

Physical address

0x2000 758C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

indly_sel_addcmd

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC100

Address offset

0x590

Physical address

0x2000 7590

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

indly_sel_clkn

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC101

Address offset

0x594

Physical address

0x2000 7594

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

indly_sel_clkp

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC102

Address offset

0x598

Physical address

0x2000 7598

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

indly_sel_dq

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC103

Address offset

0x59C

Physical address

0x2000 759C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

indly_sel_dqsn

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC104

Address offset

0x5A0

Physical address

0x2000 75A0

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

indly_sel_dqsp

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC105

Address offset

0x5A4

Physical address

0x2000 75A4

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

lane_pvt_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC106

Address offset

0x5A8

Physical address

0x2000 75A8

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

lane_pvt_data

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC107

Address offset

0x5AC

Physical address

0x2000 75AC

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

lsr_disable_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC108

Address offset

0x5B0

Physical address

0x2000 75B0

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

lsr_disable_clkn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC109

Address offset

0x5B4

Physical address

0x2000 75B4

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

lsr_disable_clkp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC110

Address offset

0x5B8

Physical address

0x2000 75B8

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

lsr_disable_dq

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC111

Address offset

0x5BC

Physical address

0x2000 75BC

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

lsr_disable_dqsn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC112

Address offset

0x5C0

Physical address

0x2000 75C0

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

lsr_disable_dqsp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC113

Address offset

0x5C4

Physical address

0x2000 75C4

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

mvdly_en_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC114

Address offset

0x5C8

Physical address

0x2000 75C8

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

mvdly_en_clkn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC115

Address offset

0x5CC

Physical address

0x2000 75CC

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

mvdly_en_clkp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC116

Address offset

0x5D0

Physical address

0x2000 75D0

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

mvdly_en_dq

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC117

Address offset

0x5D4

Physical address

0x2000 75D4

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

mvdly_en_dqsn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC118

Address offset

0x5D8

Physical address

0x2000 75D8

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

mvdly_en_dqsp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC119

Address offset

0x5DC

Physical address

0x2000 75DC

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

oeclk_inv_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC120

Address offset

0x5E0

Physical address

0x2000 75E0

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

oeclk_inv_clkn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC121

Address offset

0x5E4

Physical address

0x2000 75E4

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

oeclk_inv_clkp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC122

Address offset

0x5E8

Physical address

0x2000 75E8

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

oeclk_inv_dq

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC123

Address offset

0x5EC

Physical address

0x2000 75EC

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

oeclk_inv_dqsn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC124

Address offset

0x5F0

Physical address

0x2000 75F0

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

oeclk_inv_dqsp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC125

Address offset

0x5F4

Physical address

0x2000 75F4

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

oe_md_addcmd

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC126

Address offset

0x5F8

Physical address

0x2000 75F8

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

oe_md_clkn

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC127

Address offset

0x5FC

Physical address

0x2000 75FC

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

oe_md_clkp

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC128

Address offset

0x600

Physical address

0x2000 7600

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

oe_md_dq

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC129

Address offset

0x604

Physical address

0x2000 7604

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

oe_md_dqsn

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC130

Address offset

0x608

Physical address

0x2000 7608

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

oe_md_dqsp

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC131

Address offset

0x60C

Physical address

0x2000 760C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

pause_en_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC132

Address offset

0x610

Physical address

0x2000 7610

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

pause_en_data

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC133

Address offset

0x614

Physical address

0x2000 7614

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

qdr_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC134

Address offset

0x618

Physical address

0x2000 7618

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

qdr_data

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC135

Address offset

0x61C

Physical address

0x2000 761C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

qdr_md_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC136

Address offset

0x620

Physical address

0x2000 7620

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

qdr_md_clkn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC137

Address offset

0x624

Physical address

0x2000 7624

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

qdr_md_clkp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC138

Address offset

0x628

Physical address

0x2000 7628

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

qdr_md_dq

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC139

Address offset

0x62C

Physical address

0x2000 762C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

qdr_md_dqsn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC140

Address offset

0x630

Physical address

0x2000 7630

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

qdr_md_dqsp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC141

Address offset

0x634

Physical address

0x2000 7634

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

rank2_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC142

Address offset

0x638

Physical address

0x2000 7638

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

rank2_data

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC143

Address offset

0x63C

Physical address

0x2000 763C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

rst_inv_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC144

Address offset

0x640

Physical address

0x2000 7640

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

rst_inv_data

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC145

Address offset

0x644

Physical address

0x2000 7644

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

Reserved

 

RO
Rreturns0s

0x000 0000

6:0

rxdly_addcmd

 

RW

0x00

 

CFG_DDR_SGMII_PHY : RPC146

Address offset

0x648

Physical address

0x2000 7648

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

Reserved

 

RO
Rreturns0s

0x000 0000

6:0

rxdly_clkn

 

RW

0x00

 

CFG_DDR_SGMII_PHY : RPC147

Address offset

0x64C

Physical address

0x2000 764C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

Reserved

 

RO
Rreturns0s

0x000 0000

6:0

rxdly_clkp

 

RW

0x00

 

CFG_DDR_SGMII_PHY : RPC148

Address offset

0x650

Physical address

0x2000 7650

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

rxdly_dir_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC149

Address offset

0x654

Physical address

0x2000 7654

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

rxdly_dir_data

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC150

Address offset

0x658

Physical address

0x2000 7658

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

Reserved

 

RO
Rreturns0s

0x000 0000

6:0

rxdly_dq

 

RW

0x00

 

CFG_DDR_SGMII_PHY : RPC151

Address offset

0x65C

Physical address

0x2000 765C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

Reserved

 

RO
Rreturns0s

0x000 0000

6:0

rxdly_dqsn

 

RW

0x00

 

CFG_DDR_SGMII_PHY : RPC152

Address offset

0x660

Physical address

0x2000 7660

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

Reserved

 

RO
Rreturns0s

0x000 0000

6:0

rxdly_dqsp

 

RW

0x00

 

CFG_DDR_SGMII_PHY : RPC153

Address offset

0x664

Physical address

0x2000 7664

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

rxdly_en_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC154

Address offset

0x668

Physical address

0x2000 7668

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

rxdly_en_data

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC155

Address offset

0x66C

Physical address

0x2000 766C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:8

Reserved

 

RO
Rreturns0s

0x00 0000

7:0

rxdly_offset_addcmd

 

RW

0x00

 

CFG_DDR_SGMII_PHY : RPC156

Address offset

0x670

Physical address

0x2000 7670

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:8

Reserved

 

RO
Rreturns0s

0x00 0000

7:0

rxdly_offset_data

 

RW

0x00

 

CFG_DDR_SGMII_PHY : RPC157

Address offset

0x674

Physical address

0x2000 7674

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

rxdly_wide_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC158

Address offset

0x678

Physical address

0x2000 7678

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

rxdly_wide_clkn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC159

Address offset

0x67C

Physical address

0x2000 767C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

rxdly_wide_clkp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC160

Address offset

0x680

Physical address

0x2000 7680

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

rxdly_wide_dq

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC161

Address offset

0x684

Physical address

0x2000 7684

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

rxdly_wide_dqsn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC162

Address offset

0x688

Physical address

0x2000 7688

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

rxdly_wide_dqsp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC163

Address offset

0x68C

Physical address

0x2000 768C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

rxmvdly_en_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC164

Address offset

0x690

Physical address

0x2000 7690

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

rxmvdly_en_data

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC165

Address offset

0x694

Physical address

0x2000 7694

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

rxptr_addcmd

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC166

Address offset

0x698

Physical address

0x2000 7698

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

rxptr_data

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC167

Address offset

0x69C

Physical address

0x2000 769C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3:0

rx_md_addcmd

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC168

Address offset

0x6A0

Physical address

0x2000 76A0

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3:0

rx_md_clkn

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC169

Address offset

0x6A4

Physical address

0x2000 76A4

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3:0

rx_md_clkp

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC170

Address offset

0x6A8

Physical address

0x2000 76A8

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3:0

rx_md_dq

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC171

Address offset

0x6AC

Physical address

0x2000 76AC

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3:0

rx_md_dqsn

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC172

Address offset

0x6B0

Physical address

0x2000 76B0

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3:0

rx_md_dqsp

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC173

Address offset

0x6B4

Physical address

0x2000 76B4

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sclk0_en_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC174

Address offset

0x6B8

Physical address

0x2000 76B8

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sclk0_en_clkn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC175

Address offset

0x6BC

Physical address

0x2000 76BC

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sclk0_en_clkp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC176

Address offset

0x6C0

Physical address

0x2000 76C0

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sclk0_en_dq

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC177

Address offset

0x6C4

Physical address

0x2000 76C4

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sclk0_en_dqsn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC178

Address offset

0x6C8

Physical address

0x2000 76C8

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sclk0_en_dqsp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC179

Address offset

0x6CC

Physical address

0x2000 76CC

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sclk0_inv_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC180

Address offset

0x6D0

Physical address

0x2000 76D0

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sclk0_inv_clkn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC181

Address offset

0x6D4

Physical address

0x2000 76D4

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sclk0_inv_clkp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC182

Address offset

0x6D8

Physical address

0x2000 76D8

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sclk0_inv_dq

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC183

Address offset

0x6DC

Physical address

0x2000 76DC

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sclk0_inv_dqsn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC184

Address offset

0x6E0

Physical address

0x2000 76E0

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sclk0_inv_dqsp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC185

Address offset

0x6E4

Physical address

0x2000 76E4

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sclk1_en_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC186

Address offset

0x6E8

Physical address

0x2000 76E8

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sclk1_en_clkn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC187

Address offset

0x6EC

Physical address

0x2000 76EC

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sclk1_en_clkp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC188

Address offset

0x6F0

Physical address

0x2000 76F0

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sclk1_en_dq

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC189

Address offset

0x6F4

Physical address

0x2000 76F4

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sclk1_en_dqsn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC190

Address offset

0x6F8

Physical address

0x2000 76F8

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sclk1_en_dqsp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC191

Address offset

0x6FC

Physical address

0x2000 76FC

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sclk1_inv_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC192

Address offset

0x700

Physical address

0x2000 7700

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sclk1_inv_clkn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC193

Address offset

0x704

Physical address

0x2000 7704

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sclk1_inv_clkp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC194

Address offset

0x708

Physical address

0x2000 7708

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sclk1_inv_dq

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC195

Address offset

0x70C

Physical address

0x2000 770C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sclk1_inv_dqsn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC196

Address offset

0x710

Physical address

0x2000 7710

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sclk1_inv_dqsp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC197

Address offset

0x714

Physical address

0x2000 7714

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

soft_reset_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC198

Address offset

0x718

Physical address

0x2000 7718

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

soft_reset_data

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC199

Address offset

0x71C

Physical address

0x2000 771C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

spare_iog_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC200

Address offset

0x720

Physical address

0x2000 7720

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

spare_iog_clkn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC201

Address offset

0x724

Physical address

0x2000 7724

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

spare_iog_clkp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC202

Address offset

0x728

Physical address

0x2000 7728

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

spare_iog_dq

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC203

Address offset

0x72C

Physical address

0x2000 772C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

spare_iog_dqsn

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC204

Address offset

0x730

Physical address

0x2000 7730

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

spare_iog_dqsp

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC205

Address offset

0x734

Physical address

0x2000 7734

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

SPIO_sel_di_dqsn

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC206

Address offset

0x738

Physical address

0x2000 7738

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

SPIO_sel_di_dqsp

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC207

Address offset

0x73C

Physical address

0x2000 773C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

stop_sel_addcmd

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC208

Address offset

0x740

Physical address

0x2000 7740

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

stop_sel_data

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC209

Address offset

0x744

Physical address

0x2000 7744

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

txclk_sel_addcmd

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC210

Address offset

0x748

Physical address

0x2000 7748

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

txclk_sel_clkn

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC211

Address offset

0x74C

Physical address

0x2000 774C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

txclk_sel_clkp

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC212

Address offset

0x750

Physical address

0x2000 7750

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

txclk_sel_dq

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC213

Address offset

0x754

Physical address

0x2000 7754

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

txclk_sel_dqsn

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC214

Address offset

0x758

Physical address

0x2000 7758

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1:0

txclk_sel_dqsp

 

RW

0x0

 

CFG_DDR_SGMII_PHY : RPC215

Address offset

0x75C

Physical address

0x2000 775C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

Reserved

 

RO
Rreturns0s

0x000 0000

6:0

txdly_addcmd

 

RW

0x00

 

CFG_DDR_SGMII_PHY : RPC216

Address offset

0x760

Physical address

0x2000 7760

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

Reserved

 

RO
Rreturns0s

0x000 0000

6:0

txdly_clkn

 

RW

0x00

 

CFG_DDR_SGMII_PHY : RPC217

Address offset

0x764

Physical address

0x2000 7764

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

Reserved

 

RO
Rreturns0s

0x000 0000

6:0

txdly_clkp

 

RW

0x00

 

CFG_DDR_SGMII_PHY : RPC218

Address offset

0x768

Physical address

0x2000 7768

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

txdly_dir_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC219

Address offset

0x76C

Physical address

0x2000 776C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

txdly_dir_data

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC220

Address offset

0x770

Physical address

0x2000 7770

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

Reserved

 

RO
Rreturns0s

0x000 0000

6:0

txdly_dq

 

RW

0x00

 

CFG_DDR_SGMII_PHY : RPC221

Address offset

0x774

Physical address

0x2000 7774

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

Reserved

 

RO
Rreturns0s

0x000 0000

6:0

txdly_dqsn

 

RW

0x00

 

CFG_DDR_SGMII_PHY : RPC222

Address offset

0x778

Physical address

0x2000 7778

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

Reserved

 

RO
Rreturns0s

0x000 0000

6:0

txdly_dqsp

 

RW

0x00

 

CFG_DDR_SGMII_PHY : RPC223

Address offset

0x77C

Physical address

0x2000 777C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

txdly_en_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC224

Address offset

0x780

Physical address

0x2000 7780

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

txdly_en_data

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC225

Address offset

0x784

Physical address

0x2000 7784

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:8

Reserved

 

RO
Rreturns0s

0x00 0000

7:0

txdly_offset_addcmd

 

RW

0x00

 

CFG_DDR_SGMII_PHY : RPC226

Address offset

0x788

Physical address

0x2000 7788

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:8

Reserved

 

RO
Rreturns0s

0x00 0000

7:0

txdly_offset_data

 

RW

0x00

 

CFG_DDR_SGMII_PHY : RPC227

Address offset

0x78C

Physical address

0x2000 778C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

txmvdly_en_addcmd

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC228

Address offset

0x790

Physical address

0x2000 7790

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

txmvdly_en_data

 

RW

0

 

CFG_DDR_SGMII_PHY : RPC229

Address offset

0x794

Physical address

0x2000 7794

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

Reserved

 

RO
Rreturns0s

0x000 0000

6:0

tx_md_addcmd

 

RW

0x00

 

CFG_DDR_SGMII_PHY : RPC230

Address offset

0x798

Physical address

0x2000 7798

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

Reserved

 

RO
Rreturns0s

0x000 0000

6:0

tx_md_clkn

 

RW

0x00

 

CFG_DDR_SGMII_PHY : RPC231

Address offset

0x79C

Physical address

0x2000 779C

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

Reserved

 

RO
Rreturns0s

0x000 0000

6:0

tx_md_clkp

 

RW

0x00

 

CFG_DDR_SGMII_PHY : RPC232

Address offset

0x7A0

Physical address

0x2000 77A0

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

Reserved

 

RO
Rreturns0s

0x000 0000

6:0

tx_md_dq

 

RW

0x00

 

CFG_DDR_SGMII_PHY : RPC233

Address offset

0x7A4

Physical address

0x2000 77A4

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

Reserved

 

RO
Rreturns0s

0x000 0000

6:0

tx_md_dqsn

 

RW

0x00

 

CFG_DDR_SGMII_PHY : RPC234

Address offset

0x7A8

Physical address

0x2000 77A8

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

Reserved

 

RO
Rreturns0s

0x000 0000

6:0

tx_md_dqsp

 

RW

0x00

 

CFG_DDR_SGMII_PHY : RPC235

Address offset

0x7AC

Physical address

0x2000 77AC

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

wpd_addcmd0

 

RW

0x000

 

CFG_DDR_SGMII_PHY : RPC236

Address offset

0x7B0

Physical address

0x2000 77B0

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

wpd_addcmd1

 

RW

0x000

 

CFG_DDR_SGMII_PHY : RPC237

Address offset

0x7B4

Physical address

0x2000 77B4

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

wpd_addcmd2

 

RW

0x000

 

CFG_DDR_SGMII_PHY : RPC238

Address offset

0x7B8

Physical address

0x2000 77B8

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

wpd_data0

 

RW

0x000

 

CFG_DDR_SGMII_PHY : RPC239

Address offset

0x7BC

Physical address

0x2000 77BC

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

wpd_data1

 

RW

0x000

 

CFG_DDR_SGMII_PHY : RPC240

Address offset

0x7C0

Physical address

0x2000 77C0

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

wpd_data2

 

RW

0x000

 

CFG_DDR_SGMII_PHY : RPC241

Address offset

0x7C4

Physical address

0x2000 77C4

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

wpd_data3

 

RW

0x000

 

CFG_DDR_SGMII_PHY : RPC242

Address offset

0x7C8

Physical address

0x2000 77C8

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

wpd_ecc

 

RW

0x000

 

CFG_DDR_SGMII_PHY : RPC243

Address offset

0x7CC

Physical address

0x2000 77CC

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

wpu_addcmd0

 

RW

0x000

 

CFG_DDR_SGMII_PHY : RPC244

Address offset

0x7D0

Physical address

0x2000 77D0

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

wpu_addcmd1

 

RW

0x000

 

CFG_DDR_SGMII_PHY : RPC245

Address offset

0x7D4

Physical address

0x2000 77D4

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

wpu_addcmd2

 

RW

0x000

 

CFG_DDR_SGMII_PHY : RPC246

Address offset

0x7D8

Physical address

0x2000 77D8

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

wpu_data0

 

RW

0x000

 

CFG_DDR_SGMII_PHY : RPC247

Address offset

0x7DC

Physical address

0x2000 77DC

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

wpu_data1

 

RW

0x000

 

CFG_DDR_SGMII_PHY : RPC248

Address offset

0x7E0

Physical address

0x2000 77E0

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

wpu_data2

 

RW

0x000

 

CFG_DDR_SGMII_PHY : RPC249

Address offset

0x7E4

Physical address

0x2000 77E4

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

wpu_data3

 

RW

0x000

 

CFG_DDR_SGMII_PHY : RPC250

Address offset

0x7E8

Physical address

0x2000 77E8

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:12

Reserved

 

RO
Rreturns0s

0x0 0000

11:0

wpu_ecc

 

RW

0x000

 

CFG_DDR_SGMII_PHY : SPIO251

Address offset

0x7EC

Physical address

0x2000 77EC

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sel_refclk0

 

RW

0

 

CFG_DDR_SGMII_PHY : SPIO252

Address offset

0x7F0

Physical address

0x2000 77F0

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sel_refclk1

 

RW

0

 

CFG_DDR_SGMII_PHY : SPIO253

Address offset

0x7F4

Physical address

0x2000 77F4

Instance

CFG_DDR_SGMII_PHY

Description

-

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

sel_refclk2

 

RW

0

 

CFG_DDR_SGMII_PHY : SOFT_RESET_TIP

Address offset

0x800

Physical address

0x2000 7800

Instance

CFG_DDR_SGMII_PHY

Description

Compulsory register for all SCB slaves, facilitating global soft reset.

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

BLOCKID_TIP

This returns the block type and chip location. The form of BLOCKID = {4'h0, SLVTYPE, CHIPID, SUBID}. SLVTYPE=4'h2 for PCIESS MAIN. CHIPID=4'h0 for PCIESS. SUBID=4'h4 for the MAIN page.

RO

0x0000

15:9

Reserved

 

RO
Rreturns0s

0x00

8

PERIPH_TIP

This asserts functional reset of the peripheral block. It is asserted and left asserted at power-up.

WO

0

 

 

Write 0

[scb_periph_not_in_soft_reset_ddr_tip] Reset not asserted.

 

 

 

Write 1

[scb_periph_reset_ddr_tip] SCB registers reset pulsed.

 

7:2

Reserved

 

RO
Rreturns0s

0x00

1

V_MAP_TIP

Resets all the volatile register bits.

WO

0

 

 

Write 0

[scb_v_regs_not_in_soft_reset_ddr_tip] Reset not asserted.

 

 

 

Write 1

[scb_v_regs_reset_ddr_tip] SCB Volatile reset (i.e. RW-X registers are reset)

 

0

NV_MAP_TIP

Resets all the non-volatile register bits (e.g. RW-P bits).

WO

0

 

 

Write 0

[scb_nv_regs_not_in_soft_reset_ddr_tip] Reset not asserted.

 

 

 

Write 1

[scb_nv_regs_reset_ddr_tip] SCB Non-Volatile reset (i.e. RW-P registers are reset.

 

 

CFG_DDR_SGMII_PHY : rank_select

Address offset

0x804

Physical address

0x2000 7804

Instance

CFG_DDR_SGMII_PHY

Description

select rank 0 or 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

rank

TIP readback rank select

RW

0

 

CFG_DDR_SGMII_PHY : LANE_SELECT

Address offset

0x808

Physical address

0x2000 7808

Instance

CFG_DDR_SGMII_PHY

Description

select lane 0, 1, 2, 3 or 4

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

lane

TIP readback lane select

RW

0x0

 

CFG_DDR_SGMII_PHY : TRAINING_SKIP

Address offset

0x80C

Physical address

0x2000 780C

Instance

CFG_DDR_SGMII_PHY

Description

skip

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:8

Reserved

 

RO
Rreturns0s

0x00 0000

7

step7

 

RW

0

6

skip_vref_mr6

0 -> do not skip SET VREF
1 -> skip SET VREF

RW

0

5

skip_write_calibration

0 -> do not skip WRITE CALIBRATION
1 -> skip WRITE CALIBRATION

RW

0

4

SKIP_DQ_DQS_OPT

0 -> do not skip DQ/DQS Optimization
1 -> skip DQ/DQS Optimization

RW

0

3

skip_rdgate

0 -> do not skip READ GATE TRAINING
1 -> skip READ GATE TRAINING

RW

0

2

skip_wrlvl

0 -> do not skip WRITE LEVELING
1 -> skip WRITE LEVELING

RW

0

1

skip_addcmd

0 -> do not skip ADDRESS/CMD training
1 -> skip ADDRESS/CMD training

RW

0

0

skip_bclksclk

0 -> do not skip BCLK/SCLK training
1 -> skip BCLK/SCLK training

RW

0

 

CFG_DDR_SGMII_PHY : TRAINING_START

Address offset

0x810

Physical address

0x2000 7810

Instance

CFG_DDR_SGMII_PHY

Description

start

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

start

Starts training on 0->1 transition

RW

0

 

CFG_DDR_SGMII_PHY : TRAINING_STATUS

Address offset

0x814

Physical address

0x2000 7814

Instance

CFG_DDR_SGMII_PHY

Description

status

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:8

Reserved

 

RO
Rreturns0s

0x00 0000

7:0

status

Returns 1 on completion of non-skipped trainings.

RO

0x00

 

CFG_DDR_SGMII_PHY : TRAINING_RESET

Address offset

0x818

Physical address

0x2000 7818

Instance

CFG_DDR_SGMII_PHY

Description

reset

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:1

Reserved

 

RO
Rreturns0s

0x0000 0000

0

reset

Resets the TIP state machines.

RW

0

 

CFG_DDR_SGMII_PHY : GT_ERR_COMB

Address offset

0x81C

Physical address

0x2000 781C

Instance

CFG_DDR_SGMII_PHY

Description

set lane register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:6

Reserved

 

RO
Rreturns0s

0x000 0000

5:0

error_comb_lanex

TIP readback gate training error flags

RO

0x00

 

CFG_DDR_SGMII_PHY : GT_CLK_SEL

Address offset

0x820

Physical address

0x2000 7820

Instance

CFG_DDR_SGMII_PHY

Description

set lane/rank register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:3

Reserved

 

RO
Rreturns0s

0x0000 0000

2:0

clk_sel_lanex_rankx

TIP readback gate training clk_sel result

RO

0x0

 

CFG_DDR_SGMII_PHY : GT_TXDLY

Address offset

0x824

Physical address

0x2000 7824

Instance

CFG_DDR_SGMII_PHY

Description

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:24

txdly3_lanex

TIP readback gate training txdly @ clk_sel=3

RO

0x00

23:16

txdly2_lanex

TIP readback gate training txdly @ clk_sel=2

RO

0x00

15:8

txdly1_lanex

TIP readback gate training txdly @ clk_sel=1

RO

0x00

7:0

txdly0_lanex

TIP readback gate training txdly @ clk_sel=0

RO

0x00

 

CFG_DDR_SGMII_PHY : GT_STEPS_180

Address offset

0x828

Physical address

0x2000 7828

Instance

CFG_DDR_SGMII_PHY

Description

set lane/rank register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3:0

steps_180_lanex_rankx

TIP readback gate training steps_180

RO

0x0

 

CFG_DDR_SGMII_PHY : GT_STATE

Address offset

0x82C

Physical address

0x2000 782C

Instance

CFG_DDR_SGMII_PHY

Description

set lane register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3:0

GT_STATE_LANEX

TIP readback gate training state

RO

0x0

 

CFG_DDR_SGMII_PHY : wl_delay_0

Address offset

0x830

Physical address

0x2000 7830

Instance

CFG_DDR_SGMII_PHY

Description

set lane/rank register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:8

Reserved

 

RO
Rreturns0s

0x00 0000

7:0

wldelay_lanex_rankx

TIP readback write leveling delay

RO

0x00

 

CFG_DDR_SGMII_PHY : DQ_DQS_ERR_DONE

Address offset

0x834

Physical address

0x2000 7834

Instance

CFG_DDR_SGMII_PHY

Description

set lane/rank register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3:0

DQ_DQS_ERROR_DONE_LANEX_RANKX

TIP readback DQ/DQS optimization error flags

RO

0x0

 

CFG_DDR_SGMII_PHY : DQDQS_WINDOW

Address offset

0x838

Physical address

0x2000 7838

Instance

CFG_DDR_SGMII_PHY

Description

set rank register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:16

Reserved

 

RO
Rreturns0s

0x0000

15:8

irs_lanex_rankx

TIP readback DQ/DQS optimization state

RO

0x00

7:0

ils_lanex_rankx

TIP readback DQ/DQS optimization initial->left side of window delay

RO

0x00

 

CFG_DDR_SGMII_PHY : DQDQS_STATE

Address offset

0x83C

Physical address

0x2000 783C

Instance

CFG_DDR_SGMII_PHY

Description

set lane/rank register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:8

Reserved

 

RO
Rreturns0s

0x00 0000

7:0

state_lanex_rankx

TIP readback DQ/DQS optimization bit 0 (in lane) RX delay

RO

0x00

 

CFG_DDR_SGMII_PHY : DELTA0

Address offset

0x840

Physical address

0x2000 7840

Instance

CFG_DDR_SGMII_PHY

Description

set lane register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:24

delay3_lanex

TIP readback DQ/DQS optimization bit 3 (in lane) RX delay

RO

0x00

23:16

delay2_lanex

TIP readback DQ/DQS optimization bit 2 (in lane) RX delay

RO

0x00

15:8

delay1_lanex

TIP readback DQ/DQS optimization bit 1 (in lane) RX delay

RO

0x00

7:0

delay0_lanex

TIP readback DQ/DQS optimization bit 0 (in lane) RX delay

RO

0x00

 

CFG_DDR_SGMII_PHY : DELTA1

Address offset

0x844

Physical address

0x2000 7844

Instance

CFG_DDR_SGMII_PHY

Description

set lane register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:24

delay7_lanex

TIP readback DQ/DQS optimization bit 7 (in lane) RX delay

RO

0x00

23:16

delay6_lanex

TIP readback DQ/DQS optimization bit 6 (in lane) RX delay

RO

0x00

15:8

delay5_lanex

TIP readback DQ/DQS optimization bit 5 (in lane) RX delay

RO

0x00

7:0

delay4_lanex

TIP readback DQ/DQS optimization bit 4 (in lane) RX delay

RO

0x00

 

CFG_DDR_SGMII_PHY : DQDQS_STATUS0

Address offset

0x848

Physical address

0x2000 7848

Instance

CFG_DDR_SGMII_PHY

Description

set lane register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:8

Reserved

 

RO
Rreturns0s

0x00 0000

7:0

init_dly_lanex

Initial delay for right side of window

RO

0x00

 

CFG_DDR_SGMII_PHY : DQDQS_STATUS1

Address offset

0x84C

Physical address

0x2000 784C

Instance

CFG_DDR_SGMII_PHY

Description

set lane/rank register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:8

Reserved

 

RO
Rreturns0s

0x00 0000

7:0

dqs_dly_lanex_rankx

DQS delay

RO

0x00

 

CFG_DDR_SGMII_PHY : DQDQS_STATUS2

Address offset

0x850

Physical address

0x2000 7850

Instance

CFG_DDR_SGMII_PHY

Description

set lane register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:8

Reserved

 

RO
Rreturns0s

0x00 0000

7:0

bit_width_lanex

Data window width

RO

0x00

 

CFG_DDR_SGMII_PHY : DQDQS_STATUS3

Address offset

0x854

Physical address

0x2000 7854

Instance

CFG_DDR_SGMII_PHY

Description

set lane/rank register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:8

Reserved

 

RO
Rreturns0s

0x00 0000

7:0

initldqs_2_mid_lanex_rankx

Distance between the DQS start possition to the middle of data window

RO

0x00

 

CFG_DDR_SGMII_PHY : DQDQS_STATUS4

Address offset

0x858

Physical address

0x2000 7858

Instance

CFG_DDR_SGMII_PHY

Description

set lane/rank register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:8

Reserved

 

RO
Rreturns0s

0x00 0000

7:0

mid_2_initldqs_lanex_rankx

Distance between the calculated middle of the data window and DQS starting on the RHS

RO

0x00

 

CFG_DDR_SGMII_PHY : DQDQS_STATUS5

Address offset

0x85C

Physical address

0x2000 785C

Instance

CFG_DDR_SGMII_PHY

Description

set lane/rank register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:8

Reserved

 

RO
Rreturns0s

0x00 0000

7:0

stw_2_initldqs_lanex_rankx

Distance from the start of the data window to the initial DQS position

RO

0x00

 

CFG_DDR_SGMII_PHY : DQDQS_STATUS6

Address offset

0x860

Physical address

0x2000 7860

Instance

CFG_DDR_SGMII_PHY

Description

set lane/rank register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:8

Reserved

 

RO
Rreturns0s

0x00 0000

7:0

initldqs_2_stw_lanex_rankx

Distance between the DQS start position and the start of the data window

RO

0x00

 

CFG_DDR_SGMII_PHY : ADDCMD_STATUS0

Address offset

0x864

Physical address

0x2000 7864

Instance

CFG_DDR_SGMII_PHY

Description

Output delays at VCOPHS
offset values

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:24

delay_vcophs_sel3

Output delay @ VCOPHS=135 degrees

RO

0x00

23:16

delay_vcophs_sel2

Output delay @ VCOPHS=90 degrees

RO

0x00

15:8

delay_vcophs_sel1

Output delay @ VCOPHS=45 degrees

RO

0x00

7:0

delay_vcophs_sel0

Output delay @ VCOPHS=0 degrees

RO

0x00

 

CFG_DDR_SGMII_PHY : ADDCMD_STATUS1

Address offset

0x868

Physical address

0x2000 7868

Instance

CFG_DDR_SGMII_PHY

Description

Output delays at VCOPHS
offset values

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:24

delay_vcophs_sel7

Output delay @ VCOPHS=315 degrees

RO

0x00

23:16

delay_vcophs_sel6

Output delay @ VCOPHS=270 degrees

RO

0x00

15:8

delay_vcophs_sel5

Output delay @ VCOPHS=225 degrees

RO

0x00

7:0

delay_vcophs_sel4

Output delay @ VCOPHS=180 degrees

RO

0x00

 

CFG_DDR_SGMII_PHY : ADDCMD_ANSWER

Address offset

0x86C

Physical address

0x2000 786C

Instance

CFG_DDR_SGMII_PHY

Description

ADDCMD training result

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3:0

vcophs_sel_after_training

Chosen VCOPHS = value * 45 degrees

RO

0x0

 

CFG_DDR_SGMII_PHY : BCLKSCLK_ANSWER

Address offset

0x870

Physical address

0x2000 7870

Instance

CFG_DDR_SGMII_PHY

Description

BCLK/SCLK trainng result

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:4

Reserved

 

RO
Rreturns0s

0x000 0000

3:0

bclk0_vcophs_sel

BCLK/SCLK training result (45 degree offset count)

RO

0x0

 

CFG_DDR_SGMII_PHY : DQDQS_WRCALIB_OFFSET

Address offset

0x874

Physical address

0x2000 7874

Instance

CFG_DDR_SGMII_PHY

Description

set lane register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:8

Reserved

 

RO
Rreturns0s

0x00 0000

7:0

wrcalib_offset_lanex

WRITE CALIBRATION OFFSET RESULT

RO

0x00

 

CFG_DDR_SGMII_PHY : EXPERT_MODE_EN

Address offset

0x878

Physical address

0x2000 7878

Instance

CFG_DDR_SGMII_PHY

Description

enable override of dynamic delay control signals

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:6

Reserved

 

RO
Rreturns0s

0x000 0000

5

dyn_ovr_dfi_shim_en

1 -> enable MSS overide, 0 -> disable MSS override

RW

0

4

dyn_ovr_calif_en

1 -> enable MSS overide, 0 -> disable MSS override

RW

0

3

dyn_ovr_wrcalib_en

1 -> enable MSS overide, 0 -> disable MSS override

RW

0

2

dyn_ovr_rdgate_en

1 -> enable MSS overide, 0 -> disable MSS override

RW

0

1

dyn_ovr_pllcnt_en

1 -> enable MSS overide, 0 -> disable MSS override

RW

0

0

dyn_ovr_dlycnt_en

1 -> enable MSS overide, 0 -> disable MSS override

RW

0

 

CFG_DDR_SGMII_PHY : EXPERT_DLYCNT_MOVE_REG0

Address offset

0x87C

Physical address

0x2000 787C

Instance

CFG_DDR_SGMII_PHY

Description

delayline control

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:24

DYN_OVR_DLYCNT_DQ_MOVE3

DQ[31:24] MOVE

RW

0x00

23:16

DYN_OVR_DLYCNT_DQ_MOVE2

DQ[23:16] MOVE

RW

0x00

15:8

DYN_OVR_DLYCNT_DQ_MOVE1

DQ[15:8] move

RW

0x00

7:0

DYN_OVR_DLYCNT_DQ_MOVE0

DQ[7:0] move

RW

0x00

 

CFG_DDR_SGMII_PHY : EXPERT_DLYCNT_MOVE_REG1

Address offset

0x880

Physical address

0x2000 7880

Instance

CFG_DDR_SGMII_PHY

Description

delayline control

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:21

Reserved

 

RO
Rreturns0s

0x000

20

dyn_ovr_dlycnt_ca_move

Command/Address IOG move

RW

0

19

dyn_ovr_dlycnt_catrn_move

Command/Address IOG move (training site)

RW

0

18

dyn_ovr_dlycnt_dqsw_move4

dqsw lane 4 move

RW

0

17

dyn_ovr_dlycnt_dqsw_move3

dqsw lane 3 move

RW

0

16

dyn_ovr_dlycnt_dqsw_move2

dqsw lane 2 move

RW

0

15

dyn_ovr_dlycnt_dqsw_move1

dqsw lane 1 move

RW

0

14

dyn_ovr_dlycnt_dqsw_move0

dqsw lane 0 move

RW

0

13

dyn_ovr_dlycnt_dqsw270_move4

dqsw270 lane 4 move

RW

0

12

dyn_ovr_dlycnt_dqsw270_move3

dqsw270 lane 3 move

RW

0

11

dyn_ovr_dlycnt_dqsw270_move2

dqsw270 lane 2 move

RW

0

10

dyn_ovr_dlycnt_dqsw270_move1

dqsw270 lane 1 move

RW

0

9

dyn_ovr_dlycnt_dqsw270_move0

dqsw270 lane 0 move

RW

0

8

dyn_ovr_dlycnt_lanectrl_move4

lanectrl lane 4 move

RW

0

7

dyn_ovr_dlycnt_lanectrl_move3

lanectrl lane 3 move

RW

0

6

dyn_ovr_dlycnt_lanectrl_move2

lanectrl lane 2 move

RW

0

5

dyn_ovr_dlycnt_lanectrl_move1

lanectrl lane 1 move

RW

0

4

dyn_ovr_dlycnt_lanectrl_move0

lanectrl lane 0 move

RW

0

3:0

DYN_OVR_DLYCNT_DQ_MOVE4

DQ[35:32] MOVE

RW

0x0

 

CFG_DDR_SGMII_PHY : EXPERT_DLYCNT_DIRECTION_REG0

Address offset

0x884

Physical address

0x2000 7884

Instance

CFG_DDR_SGMII_PHY

Description

delayline control

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:24

DYN_OVR_DLYCNT_DQ_DIRECTION3

DQ[31:24] direction

RW

0x00

23:16

DYN_OVR_DLYCNT_DQ_DIRECTION2

DQ[23:16] direction

RW

0x00

15:8

DYN_OVR_DLYCNT_DQ_DIRECTION1

DQ[15:8] direction

RW

0x00

7:0

DYN_OVR_DLYCNT_DQ_DIRECTION0

DQ[7:0] direction

RW

0x00

 

CFG_DDR_SGMII_PHY : EXPERT_DLYCNT_DIRECTION_REG1

Address offset

0x888

Physical address

0x2000 7888

Instance

CFG_DDR_SGMII_PHY

Description

delayline control

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:21

Reserved

 

RO
Rreturns0s

0x000

20

dyn_ovr_dlycnt_ca_direction

Command/Address IOG direction

RW

0

19

dyn_ovr_dlycnt_catrn_direction

Command/Address IOG direction (training site)

RW

0

18

dyn_ovr_dlycnt_dqsw_direction4

dqsw lane 4 direction

RW

0

17

dyn_ovr_dlycnt_dqsw_direction3

dqsw lane 3 direction

RW

0

16

dyn_ovr_dlycnt_dqsw_direction2

dqsw lane 2 direction

RW

0

15

dyn_ovr_dlycnt_dqsw_direction1

dqsw lane 1 direction

RW

0

14

dyn_ovr_dlycnt_dqsw_direction0

dqsw lane 0 direction

RW

0

13

dyn_ovr_dlycnt_dqsw270_direction4

dqsw270 lane 4 direction

RW

0

12

dyn_ovr_dlycnt_dqsw270_direction3

dqsw270 lane 3 direction

RW

0

11

dyn_ovr_dlycnt_dqsw270_direction2

dqsw270 lane 2 direction

RW

0

10

dyn_ovr_dlycnt_dqsw270_direction1

dqsw270 lane 1 direction

RW

0

9

dyn_ovr_dlycnt_dqsw270_direction0

dqsw270 lane 0 direction

RW

0

8

dyn_ovr_dlycnt_lanectrl_direction4

lanectrl lane 4 direction

RW

0

7

dyn_ovr_dlycnt_lanectrl_direction3

lanectrl lane 3 direction

RW

0

6

dyn_ovr_dlycnt_lanectrl_direction2

lanectrl lane 2 direction

RW

0

5

dyn_ovr_dlycnt_lanectrl_direction1

lanectrl lane 1 direction

RW

0

4

dyn_ovr_dlycnt_lanectrl_direction0

lanectrl lane 0 direction

RW

0

3:0

DYN_OVR_DLYCNT_DQ_DIRECTION4

DQ[35:32] direction

RW

0x0

 

CFG_DDR_SGMII_PHY : EXPERT_DLYCNT_LOAD_REG0

Address offset

0x88C

Physical address

0x2000 788C

Instance

CFG_DDR_SGMII_PHY

Description

delayline control

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:24

DYN_OVR_DLYCNT_DQ_LOAD3

DQ[31:24] load

RW

0x00

23:16

DYN_OVR_DLYCNT_DQ_LOAD2

DQ[23:16] load

RW

0x00

15:8

DYN_OVR_DLYCNT_DQ_LOAD1

DQ[15:8] load

RW

0x00

7:0

DYN_OVR_DLYCNT_DQ_LOAD0

DQ[7:0] load

RW

0x00

 

CFG_DDR_SGMII_PHY : EXPERT_DLYCNT_LOAD_REG1

Address offset

0x890

Physical address

0x2000 7890

Instance

CFG_DDR_SGMII_PHY

Description

delayline control

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:21

Reserved

 

RO
Rreturns0s

0x000

20

dyn_ovr_dlycnt_ca_load

Command/Address IOG load

RW

0

19

dyn_ovr_dlycnt_catrn_load

Command/Address IOG load (training site)

RW

0

18

dyn_ovr_dlycnt_dqsw_load4

dqsw lane 4 load

RW

0

17

dyn_ovr_dlycnt_dqsw_load3

dqsw lane 3 load

RW

0

16

dyn_ovr_dlycnt_dqsw_load2

dqsw lane 2 load

RW

0

15

dyn_ovr_dlycnt_dqsw_load1

dqsw lane 1 load

RW

0

14

dyn_ovr_dlycnt_dqsw_load0

dqsw lane 0 load

RW

0

13

dyn_ovr_dlycnt_dqsw270_load4

dqsw270 lane 4 load

RW

0

12

dyn_ovr_dlycnt_dqsw270_load3

dqsw270 lane 3 load

RW

0

11

dyn_ovr_dlycnt_dqsw270_load2

dqsw270 lane 2 load

RW

0

10

dyn_ovr_dlycnt_dqsw270_load1

dqsw270 lane 1 load

RW

0

9

dyn_ovr_dlycnt_dqsw270_load0

dqsw270 lane 0 load

RW

0

8

dyn_ovr_dlycnt_lanectrl_load4

lanectrl lane 4 load

RW

0

7

dyn_ovr_dlycnt_lanectrl_load3

lanectrl lane 3 load

RW

0

6

dyn_ovr_dlycnt_lanectrl_load2

lanectrl lane 2 load

RW

0

5

dyn_ovr_dlycnt_lanectrl_load1

lanectrl lane 1 load

RW

0

4

dyn_ovr_dlycnt_lanectrl_load0

lanectrl lane 0 load

RW

0

3:0

DYN_OVR_DLYCNT_DQ_LOAD4

DQ[35:32] load

RW

0x0

 

CFG_DDR_SGMII_PHY : EXPERT_DLYCNT_OOR_REG0

Address offset

0x894

Physical address

0x2000 7894

Instance

CFG_DDR_SGMII_PHY

Description

delayline control

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:24

DYN_OVR_DLYCNT_DQ_OOR3

DQ[31:24] oor

RO

0x00

23:16

DYN_OVR_DLYCNT_DQ_OOR2

DQ[23:16] oor

RO

0x00

15:8

DYN_OVR_DLYCNT_DQ_OOR1

DQ[15:8] oor

RO

0x00

7:0

DYN_OVR_DLYCNT_DQ_OOR0

DQ[7:0] oor

RO

0x00

 

CFG_DDR_SGMII_PHY : EXPERT_DLYCNT_OOR_REG1

Address offset

0x898

Physical address

0x2000 7898

Instance

CFG_DDR_SGMII_PHY

Description

delayline control

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:21

Reserved

 

RO
Rreturns0s

0x000

20

dyn_ovr_dlycnt_ca_oor

Command/Address IOG oor

RO

0

19

dyn_ovr_dlycnt_catrn_oor

Command/Address IOG oor (training site)

RO

0

18

dyn_ovr_dlycnt_dqsw_oor4

dqsw lane 4 oor

RO

0

17

dyn_ovr_dlycnt_dqsw_oor3

dqsw lane 3 oor

RO

0

16

dyn_ovr_dlycnt_dqsw_oor2

dqsw lane 2 oor

RO

0

15

dyn_ovr_dlycnt_dqsw_oor1

dqsw lane 1 oor

RO

0

14

dyn_ovr_dlycnt_dqsw_oor0

dqsw lane 0 oor

RO

0

13

dyn_ovr_dlycnt_dqsw270_oor4

dqsw270 lane 4 oor

RO

0

12

dyn_ovr_dlycnt_dqsw270_oor3

dqsw270 lane 3 oor

RO

0

11

dyn_ovr_dlycnt_dqsw270_oor2

dqsw270 lane 2 oor

RO

0

10

dyn_ovr_dlycnt_dqsw270_oor1

dqsw270 lane 1 oor

RO

0

9

dyn_ovr_dlycnt_dqsw270_oor0

dqsw270 lane 0 oor

RO

0

8

dyn_ovr_dlycnt_lanectrl_oor4

lanectrl lane 4 oor

RO

0

7

dyn_ovr_dlycnt_lanectrl_oor3

lanectrl lane 3 oor

RO

0

6

dyn_ovr_dlycnt_lanectrl_oor2

lanectrl lane 2 oor

RO

0

5

dyn_ovr_dlycnt_lanectrl_oor1

lanectrl lane 1 oor

RO

0

4

dyn_ovr_dlycnt_lanectrl_oor0

lanectrl lane 0 oor

RO

0

3:0

DYN_OVR_DLYCNT_DQ_OOR4

DQ[35:32] oor

RO

0x0

 

CFG_DDR_SGMII_PHY : EXPERT_DLYCNT_MV_RD_DLY_REG

Address offset

0x89C

Physical address

0x2000 789C

Instance

CFG_DDR_SGMII_PHY

Description

delayline control

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:5

Reserved

 

RO
Rreturns0s

0x000 0000

4

dyn_ovr_dlycnt_lanectrl_mv_rd_dly4

lanectrl lane 4 mv_rd_dly

RW

0

3

dyn_ovr_dlycnt_lanectrl_mv_rd_dly3

lanectrl lane 3 mv_rd_dly

RW

0

2

dyn_ovr_dlycnt_lanectrl_mv_rd_dly2

lanectrl lane 2 mv_rd_dly

RW

0

1

dyn_ovr_dlycnt_lanectrl_mv_rd_dly1

lanectrl lane 1 mv_rd_dly

RW

0

0

dyn_ovr_dlycnt_lanectrl_mv_rd_dly0

lanectrl lane 0 mv_rd_dly

RW

0

 

CFG_DDR_SGMII_PHY : EXPERT_DLYCNT_PAUSE

Address offset

0x8A0

Physical address

0x2000 78A0

Instance

CFG_DDR_SGMII_PHY

Description

lane pause

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:6

Reserved

 

RO
Rreturns0s

0x000 0000

5

dyn_ovr_dlycnt_lanectrl_pause_data4

pause data lane 4

RW

0

4

dyn_ovr_dlycnt_lanectrl_pause_data3

pause data lane 3

RW

0

3

dyn_ovr_dlycnt_lanectrl_pause_data2

pause data lane 2

RW

0

2

dyn_ovr_dlycnt_lanectrl_pause_data1

pause data lane 1

RW

0

1

dyn_ovr_dlycnt_lanectrl_pause_data0

pause data lane 0

RW

0

0

dyn_ovr_dlycnt_lanectrl_pause_addcmd

addcmd lane pause

RW

0

 

CFG_DDR_SGMII_PHY : EXPERT_PLLCNT

Address offset

0x8A4

Physical address

0x2000 78A4

Instance

CFG_DDR_SGMII_PHY

Description

dynamic PLL controls

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:7

Reserved

 

RO
Rreturns0s

0x000 0000

6:3

dyn_ovr_dlycnt_phsel

[0] -> BCLK VCOPHS_SEL
[1] -> BCLK90 VCOPHS_SEL
[2] -> REFCLK VCOPHS_SEL
[3] -> SCLK VCOPHS_SEL

RW

0x0

2

dyn_ovr_dlycnt_loadphs_b

PLL LOADPHS_B (asynchronous load on 0)

RW

1

1

dyn_ovr_dlycnt_direction

PLL ROTATE DIRECTION (1-> add, 0-> subtract)

RW

0

0

dyn_ovr_dlycnt_rotate

PLL PHASE ROTATE (rotates on 0->1 edge)

RW

0

 

CFG_DDR_SGMII_PHY : EXPERT_DQLANE_READBACK

Address offset

0x8A8

Physical address

0x2000 78A8

Instance

CFG_DDR_SGMII_PHY

Description

DQ/DQS lane read back signals

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:15

Reserved

 

RO
Rreturns0s

0x0 0000

14:10

burst_valid

[0] -> valid burst detected (lane0)
[1] -> valid burst detected (lane1)
[2] -> valid burst detected (lane2)
[3] -> valid burst detected (lane3)
[4] -> valid burst detected (lane4)

RO

0x00

9:5

DQ_AND

[0] -> AND of all DQ bits (lane0)
[1] -> AND of all DQ bits (lane1)
[2] -> AND of all DQ bits (lane2)
[3] -> AND of all DQ bits (lane3)
[4] -> AND of all DQ bits (lane4)

RO

0x00

4:0

DQ_OR

[0] -> OR of all DQ bits (lane0)
[1] -> OR of all DQ bits (lane1)
[2] -> OR of all DQ bits (lane2)
[3] -> OR of all DQ bits (lane3)
[4] -> OR of all DQ bits (lane4)

RO

0x00

 

CFG_DDR_SGMII_PHY : EXPERT_ADDCMD_LN_READBACK

Address offset

0x8AC

Physical address

0x2000 78AC

Instance

CFG_DDR_SGMII_PHY

Description

ADDRESS/COMMAND LANE READBACK

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:14

Reserved

 

RO
Rreturns0s

0x0 0000

13:12

rx_bclksclk

RX from BCLK/SCLK training site

RO

0x0

11:8

rx_addcmd

RX from ADDCMD training site

RO

0x0

7:0

rx_refclk

[3:0] -> RX from CK0 training site
[7:4] -> RX from CK1 training site

RO

0x00

 

CFG_DDR_SGMII_PHY : EXPERT_READ_GATE_CONTROLS

Address offset

0x8B0

Physical address

0x2000 78B0

Instance

CFG_DDR_SGMII_PHY

Description

READ GATE TRAINING OVERRIDES

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:30

Reserved

 

RO
Rreturns0s

0x0

29:10

dyn_ovr_rdgate_steps180

[3:0] lane 0 read gate steps_180
[7:4] lane 1 read gate steps_180
[11:8] lane 2 read gate steps_180
[15:12] lane 3 read gate steps_180
[19:16] lane 4 read gate steps_180

RW

0x0 0000

9:0

dyn_ovr_rdgate_clksel

[1:0] lane 0 read gate clk_sel
[3:2] lane 1 read gate clk_sel
[5:4] lane 2 read gate clk_sel
[7:6] lane 3 read gate clk_sel
[9:8] lane 4 read gate clk_sel

RW

0x000

 

CFG_DDR_SGMII_PHY : EXPERT_DQ_DQS_OPTIMIZATION0

Address offset

0x8B4

Physical address

0x2000 78B4

Instance

CFG_DDR_SGMII_PHY

Description

DQ/DQS OPTIMIZATION READBACK REG 0

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:24

DYN_OVR_DQDQS_DATA_MATCH_LANE3

[n] -> bit n in lane matches read training pattern

RO

0x00

23:16

DYN_OVR_DQDQS_DATA_MATCH_LANE2

[n] -> bit n in lane matches read training pattern

RO

0x00

15:8

DYN_OVR_DQDQS_DATA_MATCH_LANE1

[n] -> bit n in lane matches read training pattern

RO

0x00

7:0

DYN_OVR_DQDQS_DATA_MATCH_LANE0

[n] -> bit n in lane matches read training pattern

RO

0x00

 

CFG_DDR_SGMII_PHY : EXPERT_DQ_DQS_OPTIMIZATION1

Address offset

0x8B8

Physical address

0x2000 78B8

Instance

CFG_DDR_SGMII_PHY

Description

DQ/DQS OPTIMIZATION READBACK REG 1

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:8

Reserved

 

RO
Rreturns0s

0x00 0000

7:0

DYN_OVR_DQDQS_DATA_MATCH_LANE4

[n] -> bit n in lane matches read training pattern

RO

0x00

 

CFG_DDR_SGMII_PHY : EXPERT_WRCALIB

Address offset

0x8BC

Physical address

0x2000 78BC

Instance

CFG_DDR_SGMII_PHY

Description

WRCALIB OFFSET

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:20

Reserved

 

RO
Rreturns0s

0x000

19:16

dyn_ovr_wrcalib_offset_lane4

write calibration offset lane 4

RW

0x0

15:12

dyn_ovr_wrcalib_offset_lane3

write calibration offset lane 3

RW

0x0

11:8

dyn_ovr_wrcalib_offset_lane2

write calibration offset lane 2

RW

0x0

7:4

dyn_ovr_wrcalib_offset_lane1

write calibration offset lane 1

RW

0x0

3:0

dyn_ovr_wrcalib_offset_lane0

write calibration offset lane 0

RW

0x0

 

CFG_DDR_SGMII_PHY : EXPERT_CALIF

Address offset

0x8C0

Physical address

0x2000 78C0

Instance

CFG_DDR_SGMII_PHY

Description

CAL INTERFACE CONTROL

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:6

Reserved

 

RO
Rreturns0s

0x000 0000

5:2

dyn_ovr_pattern_sel

CAL IF pattern select

RW

0x0

1

dyn_ovr_calif_write

initiate CAL IF write

RW

0

0

dyn_ovr_calif_read

initiate CAL IF read

RW

0

 

CFG_DDR_SGMII_PHY : EXPERT_CALIF_READBACK

Address offset

0x8C4

Physical address

0x2000 78C4

Instance

CFG_DDR_SGMII_PHY

Description

CAL INTERFACE READBACK0

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:24

wrcalib_pattern_match_lane3

[n] -> bit n in lane matches selected pattern

RO

0x00

23:16

wrcalib_pattern_match_lane2

[n] -> bit n in lane matches selected pattern

RO

0x00

15:8

wrcalib_pattern_match_lane1

[n] -> bit n in lane matches selected pattern

RO

0x00

7:0

wrcalib_pattern_match_lane0

[n] -> bit n in lane matches selected pattern

RO

0x00

 

CFG_DDR_SGMII_PHY : EXPERT_CALIF_READBACK1

Address offset

0x8C8

Physical address

0x2000 78C8

Instance

CFG_DDR_SGMII_PHY

Description

CAL INTERFACE READBACK1

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:8

Reserved

 

RO
Rreturns0s

0x00 0000

7:0

wrcalib_pattern_match_lane4

[n] -> bit n in lane matches selected pattern

RO

0x00

 

CFG_DDR_SGMII_PHY : EXPERT_DFI_STATUS_OVERRIDE_TO_SHIM

Address offset

0x8CC

Physical address

0x2000 78CC

Instance

CFG_DDR_SGMII_PHY

Description

DFI signals are used by the SHIM to
put signalling in special training modes

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:5

Reserved

 

RO
Rreturns0s

0x000 0000

4

dfi_rdlvl_gate_en_shim

dfi_rdlvl_en override in shim

RW

0

3

dfi_rdlvl_en_shim

dfi_wrlvl_en override in shim

RW

0

2

dfi_wrlvl_en_shim

dfi_training_complete override in shim

RW

0

1

dfi_training_complete_shim

dfi_init_complete override in shim

RW

0

0

dfi_init_complete_shim

dfi status signals to shim override

RW

0

 

CFG_DDR_SGMII_PHY : TIP_CFG_PARAMS

Address offset

0x8D0

Physical address

0x2000 78D0

Instance

CFG_DDR_SGMII_PHY

Description

TIP STATIC PARAMETERS 0

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

Reserved

 

RO
Rreturns0s

0

30:22

addrcmd_wait_count

Number of VCO Phase offsets between BCLK and SCLK

RW

0x000

21:13

read_gate_min_reads

Number of VCO Phase offsets between BCLK and SCLK

RW

0x000

12:6

wrcalib_write_count

Number of VCO Phase offsets between BCLK and SCLK

RW

0x00

5:3

bcklsclk_offset

Number of VCO Phase offsets between BCLK and SCLK

RW

0x0

2:0

ADDCMD_OFFSET

Number of VCO Phase offsets between REFCLK and ADDCMD bits

RW

0x0

 

CFG_DDR_SGMII_PHY : TIP_VREF_PARAM

Address offset

0x8D4

Physical address

0x2000 78D4

Instance

CFG_DDR_SGMII_PHY

Description

TIP STATIC PARAMETERS 1

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:17

Reserved

 

RO
Rreturns0s

0x0000

16:9

ca_vref

COMMAND/ADDRESS memory VREF

RW

0x00

8:1

data_vref

DATA memory VREF

RW

0x00

0

vref_override

Override VREF default value

RW

0

 

CFG_DDR_SGMII_PHY : LANE_ALIGNMENT_FIFO_CONTROL

Address offset

0x8D8

Physical address

0x2000 78D8

Instance

CFG_DDR_SGMII_PHY

Description

Control signals for lane alignment FIFO

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:2

Reserved

 

RO
Rreturns0s

0x0000 0000

1

fifo_reset_n

Reset lane alignment FIFO

RW

1

0

block_fifo

Block FIFO from receiving data valid pulses

RW

0

 

CFG_DDR_SGMII_PHY : SOFT_RESET_SGMII

Address offset

0xC00

Physical address

0x2000 7C00

Instance

CFG_DDR_SGMII_PHY

Description

SGMII Reset control (SEU)

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

blockid_SGMII

not used

RO

0x0000

15:9

Reserved

 

RO
Rreturns0s

0x00

8

periph_SGMII

assert peripheral block resets

WO

0

7:2

Reserved

 

RO
Rreturns0s

0x00

1

v_map_SGMII

not used

WO

0

0

nv_map_SGMII

reset all the RW-P register bits in this map

WO

0

 

CFG_DDR_SGMII_PHY : SGMII_MODE

Address offset

0xC04

Physical address

0x2000 7C04

Instance

CFG_DDR_SGMII_PHY

Description

SGMII mode control (SEU)

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

reg_refclk_en_ins_hyst_n

REFCLK N input hysterisis enable

RW

0

30

reg_refclk_en_udrive_n

REFCLK N input drive enable

RW

0

29

reg_refclk_en_ins_hyst_p

REFCLK P input hysterisis enable

RW

0

28

reg_refclk_en_udrive_p

REFCLK P input drive enable

RW

0

27:24

reg_bc_vs

GPIO Calibrator modes for normal IOs

RW

0x0

23

reg_refclk_en_rdiff

REFCLK input pad enable differential mode

RW

0

22

reg_cdr_move_step

CDR jump step 3 or 2, default 3

RW

1

21:16

reg_bc_vrgen

Bank controller voltage reference modes

RW

0x00

15

reg_rx1_cdr_reset_b

RX1 CDR data input start if 1

RW

1

14

reg_rx0_cdr_reset_b

RX0 CDR data input start if 1

RW

1

13:10

reg_dll_adj_code

Add 9 taps to DLL delay code to compensate for generic mux delay

RW

0x9

9:8

reg_dll_lock_flt

DLL phase lock tolerance of gitter

RW

0x2

7

reg_rx1_en

enable RX1 channel

RW

0

6

reg_tx1_en

enable TX1 channel

RW

0

5

reg_rx0_en

enable RX0 channel

RW

0

4

reg_tx0_en

enable TX0 channel

RW

0

3

reg_bc_vrgen_en

enable Bank Controller Vref

RW

1

2

reg_pvt_en

enable GPIO PVT calibrator by releasing calib_reset

RW

1

1

reg_dll_en

enable DLL

RW

0

0

reg_pll_en

enable PLL

RW

0

 

CFG_DDR_SGMII_PHY : PLL_CNTL

Address offset

0xC08

Physical address

0x2000 7C08

Instance

CFG_DDR_SGMII_PHY

Description

PLL control register (SEU)

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:30

reg_pll_bwp

PLL proportional path loop bandwidth control

RW

0x2

29:28

reg_pll_bwi

PLL integral path loop bandwidth control

RW

0x0

27:16

reg_pll_intin

PLL feedback multiplier (multiplied by 20)

RW

0x014

15

reg_pll_lp_requires_lock

PLL lock to exit flash-freeze

RW

0

14

reg_pll_reg_rfclk_sel

PLL select refclk0 by default

RW

0

13:8

reg_pll_rfdiv

PLL reference clock division

RW

0x01

7

aro_pll0_lock

PLL lock from SCB

RO

0

6:0

reg_pll_postdiv

PLL post-division for all four outputs (divided by 4)

RW

0x01

 

CFG_DDR_SGMII_PHY : CH0_CNTL

Address offset

0xC0C

Physical address

0x2000 7C0C

Instance

CFG_DDR_SGMII_PHY

Description

Channel0 control register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

Reserved

 

RO
Rreturns0s

0

30:28

reg_rx0_odt_static_p

RX0 termination modes

RW

0x0

27:24

reg_rx0_odt_p

RX0 termination modes

RW

0x0

23:21

reg_rx0_eyewidth_p

RX0 eye monitor width

RW

0x4

20:18

reg_rx0_ibufmd_p

RX0 pad input buffer mode

RW

0x7

17

reg_rx0_wpd_p

RX0 pad weak pull-down

RW

0

16

reg_rx0_wpu_p

RX0 pad weak pull-up

RW

0

15

reg_rx0_tim_long

RX0 comma detection timeout long (1) or short (0), 8ms or 1ms

RW

0

14:12

reg_tx0_odt_static_p

TX0 termination modes

RW

0x0

11:8

reg_tx0_odt_p

TX0 termination modes

RW

0x0

7:4

reg_tx0_drv_p

TX0 drive strength

RW

0x0

3:2

reg_tx0_slew_p

TX0 pad slew mode

RW

0x0

1

reg_tx0_wpd_p

TX0 pad weak pull-down

RW

0

0

reg_tx0_wpu_p

TX0 pad weak pull-up

RW

0

 

CFG_DDR_SGMII_PHY : CH1_CNTL

Address offset

0xC10

Physical address

0x2000 7C10

Instance

CFG_DDR_SGMII_PHY

Description

Channel1 control register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

Reserved

 

RO
Rreturns0s

0

30:28

reg_rx1_odt_static_p

RX1 termination modes

RW

0x0

27:24

reg_rx1_odt_p

RX1 termination modes

RW

0x0

23:21

reg_rx1_eyewidth_p

RX1 eye monitor width

RW

0x4

20:18

reg_rx1_ibufmd_p

RX1 pad input buffer mode

RW

0x7

17

reg_rx1_wpd_p

RX1 pad weak pull-down

RW

0

16

reg_rx1_wpu_p

RX1 pad weak pull-up

RW

0

15

reg_rx1_tim_long

RX1 comma detection timeout long (1) or short (0), 8ms or 1ms

RW

0

14:12

reg_tx1_odt_static_p

TX1 termination modes

RW

0x0

11:8

reg_tx1_odt_p

TX1 termination modes

RW

0x0

7:4

reg_tx1_drv_p

TX1 drive strength

RW

0x0

3:2

reg_tx1_slew_p

TX1 pad slew mode

RW

0x0

1

reg_tx1_wpd_p

TX1 pad weak pull-down

RW

0

0

reg_tx1_wpu_p

TX1 pad weak pull-up

RW

0

 

CFG_DDR_SGMII_PHY : RECAL_CNTL

Address offset

0xC14

Physical address

0x2000 7C14

Instance

CFG_DDR_SGMII_PHY

Description

Recalibration control register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

sro_recal_start

recalibration interrupt when difference range is exceeded

RO

0

30:24

sro_dll_st_code

stored DLL code since the last recalibration

RO

0x00

23

sro_dll_lock

DLL lock

RO

0

22:16

sro_dll_90_code

DLL delay code for 90 degree

RO

0x00

15:14

reg_pvt_reg_calib_diffr_vsel

GPIO Calibrator modes for differential IOs

RW

0x0

13:12

reg_pvt_reg_calib_clkdiv

GPIO Calibrator clock divider after power-up

RW

0x0

11

bc_vrgen_move

Bank Controller voltage reference move

RW

0

10

bc_vrgen_load

Bank Controller voltage reference load

RW

0

9

bc_vrgen_direction

Bank Controller voltage reference move direction

RW

0

8

reg_recal_upd

update dll_st_code when written 1 after recalibration

RW

0

7

reg_pvt_calib_lock

PVT calibration lock in new code

RW

0

6

reg_pvt_calib_start

PVT calibration start new run

RW

0

5

reg_recal_start_en

recalibration interrupt enable

RW

0

4:0

reg_recal_diff_range

recalibration difference range between dll_90_code and dll_st_code

RW

0x08

 

CFG_DDR_SGMII_PHY : CLK_CNTL

Address offset

0xC18

Physical address

0x2000 7C18

Instance

CFG_DDR_SGMII_PHY

Description

Clock input and routing control registers

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:16

reg_clkmux_spare0

spare SEU registers

RW

0xF000

15:14

reg_clkmux_pll0_rfclk1_sel

PLL reference clock input1 selection

RW

0x0

13:12

reg_clkmux_pll0_rfclk0_sel

PLL reference clock input0 selection

RW

0x0

11:9

reg_clkmux_fclk_sel

SGMII clock selection for fabric

RW

0x0

8

reg_refclk_clkbuf_en_pullup

REFCLK input pad enable pullup

RW

0

7:6

reg_refclk_en_rxmode_n

REFCLK N input mode enable

RW

0x0

5:4

reg_refclk_en_term_n

REFCLK N input termination enable

RW

0x0

3:2

reg_refclk_en_rxmode_p

REFCLK P input mode enable

RW

0x0

1:0

reg_refclk_en_term_p

REFCLK P input termination enable

RW

0x0

 

CFG_DDR_SGMII_PHY : DYN_CNTL

Address offset

0xC1C

Physical address

0x2000 7C1C

Instance

CFG_DDR_SGMII_PHY

Description

Dynamic control registers

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:28

aro_ref_diffr

PVT DIFFR calibration code from SCB

RO

0x0

27:25

aro_pll0_vco3ph_sel

PLL VCO phase3 selection

RO

0x0

24:22

aro_pll0_vco2ph_sel

PLL VCO phase2 selection

RO

0x0

21:19

aro_pll0_vco1ph_sel

PLL VCO phase1 selection

RO

0x0

18:16

aro_pll0_vco0ph_sel

PLL VCO phase0 selection

RO

0x0

15

pvt_calib_status

PVT calibration status

RO

0

14

reg_lane1_soft_reset_periph

Lane1 soft reset

RW

0

13

reg_lane0_soft_reset_periph

Lane0 soft reset

RW

0

12

reg_clkmux_soft_reset_periph

CLKMUX soft reset

RW

0

11

reg_bc_soft_reset_periph

Bank controller soft reset

RW

0

10

reg_pvt_soft_reset_periph

PVT soft reset

RW

1

9

reg_dll_soft_reset_periph

DLL soft reset

RW

0

8

reg_pll_soft_reset_periph

PLL soft reset

RW

0

7

bc_vrgen_oor

Bank controller voltage reference out of range

RO

0

6

reg_lane1_dynen

Lane1 dynamic control enable

RW

0

5

reg_lane0_dynen

Lane0 dynamic control enable

RW

0

4

reg_clkmux_dynen

CLKMUX dynamic control enable

RW

0

3

reg_bc_dynen

Bank controller dynamic control enable

RW

0

2

reg_pvt_dynen

PVT calibrator dynamic control enable

RW

0

1

reg_dll_dynen

DLL dynamic control enable

RW

0

0

reg_pll_dynen

PLL dynamic control enable

RW

0

 

CFG_DDR_SGMII_PHY : PVT_STAT

Address offset

0xC20

Physical address

0x2000 7C20

Instance

CFG_DDR_SGMII_PHY

Description

PVT calibrator status registers

Type

RW

 

Bits

Field Name

Description

Type

Reset

31

pvt_calib_start

PVT calibration start new run

RW

1

30

pvt_calib_lock

PVT calibration lock in new code

RW

0

29:24

aro_ncode

PVT calibrator N-code to IO lane

RO

0x00

23

pvt_calib_intrpt

PVT calibration interrupt

RO

0

22

aro_calib_intrpt

PVT calibration interrupt

RO

0

21:16

aro_pcode

PVT calibrator P-code to IO lane

RO

0x00

15

aro_calib_status_b

PVT calibration status_b

RO

0

14

aro_calib_status

PVT calibration status

RO

0

13:8

aro_ref_ncode

PVT calibrator N-code to reference

RO

0x00

7

aro_ioen_bnk_b

PVT calibrator IOEN_B

RO

0

6

aro_ioen_bnk

PVT calibrator IOEN

RO

0

5:0

aro_ref_pcode

PVT calibrator P-code to reference

RO

0x00

 

CFG_DDR_SGMII_PHY : SPARE_CNTL

Address offset

0xC24

Physical address

0x2000 7C24

Instance

CFG_DDR_SGMII_PHY

Description

Spare control register

Type

RW

 

Bits

Field Name

Description

Type

Reset

31:0

reg_spare

spare SEU registers

RW

0xFF00 0000

 

CFG_DDR_SGMII_PHY : SPARE_STAT

Address offset

0xC28

Physical address

0x2000 7C28

Instance

CFG_DDR_SGMII_PHY

Description

Spare status register

Type

RO

 

Bits

Field Name

Description

Type

Reset

31:0

sro_spare

spare status bits

RO

0x0000 0000

 

CFG_DDR_SGMII_PHY has no common memories.