This section
provides information on the DDR_CSR_APB Module Instance. Each of the module
registers is described below.
Register Name |
Type |
Register Width (Bits)
|
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0 2400 |
0x2008 2400 |
|
RW |
32 |
0x0000 0000 |
0x0 2404 |
0x2008 2404 |
|
RW |
32 |
0x0000 0000 |
0x0 2408 |
0x2008 2408 |
|
RW |
32 |
0x0000 0004 |
0x0 240C |
0x2008 240C |
|
RW |
32 |
0x0000 000A |
0x0 2410 |
0x2008 2410 |
|
RW |
32 |
0x0000 0000 |
0x0 2414 |
0x2008 2414 |
|
RW |
32 |
0x0000 0000 |
0x0 2418 |
0x2008 2418 |
|
RW |
32 |
0x0000 0000 |
0x0 241C |
0x2008 241C |
|
RW |
32 |
0x0000 0000 |
0x0 2420 |
0x2008 2420 |
|
RW |
32 |
0x0000 0000 |
0x0 2424 |
0x2008 2424 |
|
RW |
32 |
0x0000 0000 |
0x0 2428 |
0x2008 2428 |
|
RW |
32 |
0x0000 0000 |
0x0 242C |
0x2008 242C |
|
RW |
32 |
0x0000 0000 |
0x0 2430 |
0x2008 2430 |
|
RW |
32 |
0x0000 0000 |
0x0 2434 |
0x2008 2434 |
|
RW |
32 |
0x0000 0140 |
0x0 2800 |
0x2008 2800 |
|
RW |
32 |
0x0000 00A0 |
0x0 2804 |
0x2008 2804 |
|
RW |
32 |
0x0000 0000 |
0x0 2808 |
0x2008 2808 |
|
RW |
32 |
0x0000 0000 |
0x0 280C |
0x2008 280C |
|
RW |
32 |
0x0000 0000 |
0x0 2810 |
0x2008 2810 |
|
RW |
32 |
0x0000 0000 |
0x0 2814 |
0x2008 2814 |
|
RW |
32 |
0x0000 0000 |
0x0 2818 |
0x2008 2818 |
|
RW |
32 |
0x0000 0000 |
0x0 281C |
0x2008 281C |
|
RW |
32 |
0x0000 0000 |
0x0 2820 |
0x2008 2820 |
|
RW |
32 |
0x0000 0001 |
0x0 2824 |
0x2008 2824 |
|
RW |
32 |
0x0000 0016 |
0x0 2828 |
0x2008 2828 |
|
RW |
32 |
0x0000 0016 |
0x0 282C |
0x2008 282C |
|
RW |
32 |
0x0000 0000 |
0x0 2830 |
0x2008 2830 |
|
RW |
32 |
0x0000 0000 |
0x0 3C00 |
0x2008 3C00 |
|
RW |
32 |
0x0000 0000 |
0x0 3C04 |
0x2008 3C04 |
|
RW |
32 |
0x0000 0000 |
0x0 3C08 |
0x2008 3C08 |
|
RW |
32 |
0x0000 0000 |
0x0 3C0C |
0x2008 3C0C |
|
RW |
32 |
0x0000 0000 |
0x0 3C10 |
0x2008 3C10 |
|
RW |
32 |
0x0000 0000 |
0x0 3C14 |
0x2008 3C14 |
|
RW |
32 |
0x0000 0000 |
0x0 3C18 |
0x2008 3C18 |
|
RW |
32 |
0x0000 0000 |
0x0 3C1C |
0x2008 3C1C |
|
RW |
32 |
0x0000 0000 |
0x0 3C20 |
0x2008 3C20 |
|
RW |
32 |
0x0000 0000 |
0x0 3C24 |
0x2008 3C24 |
|
RW |
32 |
0x0000 0000 |
0x0 3C28 |
0x2008 3C28 |
|
RW |
32 |
0x0000 0000 |
0x0 3C2C |
0x2008 3C2C |
|
RW |
32 |
0x0000 0000 |
0x0 3C30 |
0x2008 3C30 |
|
RW |
32 |
0x0000 0000 |
0x0 3C34 |
0x2008 3C34 |
|
RW |
32 |
0x0000 0000 |
0x0 3C38 |
0x2008 3C38 |
|
RW |
32 |
0x0000 0000 |
0x0 3C3C |
0x2008 3C3C |
|
RW |
32 |
0x0000 0000 |
0x0 3C40 |
0x2008 3C40 |
|
RW |
32 |
0x0000 0000 |
0x0 3C44 |
0x2008 3C44 |
|
RW |
32 |
0x0000 0001 |
0x0 3C48 |
0x2008 3C48 |
|
RW |
32 |
0x0000 0000 |
0x0 3C4C |
0x2008 3C4C |
|
RW |
32 |
0x0000 0000 |
0x0 3C50 |
0x2008 3C50 |
|
RW |
32 |
0x0000 0000 |
0x0 3C54 |
0x2008 3C54 |
|
RW |
32 |
0x0000 0000 |
0x0 3C58 |
0x2008 3C58 |
|
RW |
32 |
0x0000 0000 |
0x0 3C5C |
0x2008 3C5C |
|
RW |
32 |
0x0000 0000 |
0x0 3C60 |
0x2008 3C60 |
|
RW |
32 |
0x0000 0000 |
0x0 3C64 |
0x2008 3C64 |
|
RW |
32 |
0x0000 0000 |
0x0 3C68 |
0x2008 3C68 |
|
RW |
32 |
0x0000 0000 |
0x0 3C6C |
0x2008 3C6C |
|
RW |
32 |
0x0000 0000 |
0x0 3C70 |
0x2008 3C70 |
|
RW |
32 |
0x0000 0000 |
0x0 3C74 |
0x2008 3C74 |
|
RW |
32 |
0x0000 0003 |
0x0 3C78 |
0x2008 3C78 |
|
RW |
32 |
0x0000 0003 |
0x0 3C7C |
0x2008 3C7C |
|
RW |
32 |
0x0000 0002 |
0x0 3C80 |
0x2008 3C80 |
|
RW |
32 |
0x0000 0002 |
0x0 3C84 |
0x2008 3C84 |
|
RW |
32 |
0x0000 0002 |
0x0 3C88 |
0x2008 3C88 |
|
RW |
32 |
0x0000 0002 |
0x0 3C8C |
0x2008 3C8C |
|
RW |
32 |
0x0000 0004 |
0x0 3C90 |
0x2008 3C90 |
|
RW |
32 |
0x0000 0022 |
0x0 3C94 |
0x2008 3C94 |
|
RW |
32 |
0x0000 0022 |
0x0 3C98 |
0x2008 3C98 |
|
RW |
32 |
0x0000 0022 |
0x0 3C9C |
0x2008 3C9C |
|
RW |
32 |
0x0000 0000 |
0x0 3CC4 |
0x2008 3CC4 |
|
RW |
32 |
0x0000 0000 |
0x0 3CE0 |
0x2008 3CE0 |
|
RW |
32 |
0x0000 0000 |
0x0 3CE4 |
0x2008 3CE4 |
|
RW |
32 |
0x0000 0000 |
0x0 3CE8 |
0x2008 3CE8 |
|
RW |
32 |
0x0000 0000 |
0x0 3CEC |
0x2008 3CEC |
|
RW |
32 |
0x0000 0000 |
0x0 3CF0 |
0x2008 3CF0 |
|
RW |
32 |
0x0000 0000 |
0x0 3CF4 |
0x2008 3CF4 |
|
RW |
32 |
0x0000 0000 |
0x0 3CF8 |
0x2008 3CF8 |
|
RW |
32 |
0x0000 0000 |
0x0 3CFC |
0x2008 3CFC |
|
RW |
32 |
0x0000 0000 |
0x0 3D00 |
0x2008 3D00 |
|
RW |
32 |
0x0000 0000 |
0x0 3D04 |
0x2008 3D04 |
|
RW |
32 |
0x0000 0000 |
0x0 3D08 |
0x2008 3D08 |
|
RW |
32 |
0x0000 0000 |
0x0 3D0C |
0x2008 3D0C |
|
RW |
32 |
0x0000 0000 |
0x0 3D10 |
0x2008 3D10 |
|
RW |
32 |
0x0000 0000 |
0x0 3D14 |
0x2008 3D14 |
|
RW |
32 |
0x0000 0000 |
0x0 3D18 |
0x2008 3D18 |
|
RW |
32 |
0x0000 0000 |
0x0 3D1C |
0x2008 3D1C |
|
RW |
32 |
0x0000 0000 |
0x0 3D20 |
0x2008 3D20 |
|
RW |
32 |
0x0000 0000 |
0x0 3D24 |
0x2008 3D24 |
|
RW |
32 |
0x0000 0000 |
0x0 3D28 |
0x2008 3D28 |
|
RW |
32 |
0x0000 0000 |
0x0 3D2C |
0x2008 3D2C |
|
RW |
32 |
0x0000 0000 |
0x0 3D30 |
0x2008 3D30 |
|
RW |
32 |
0x0000 0000 |
0x0 3D34 |
0x2008 3D34 |
|
RW |
32 |
0x0000 0000 |
0x0 3D38 |
0x2008 3D38 |
|
RW |
32 |
0x0000 0000 |
0x0 3D3C |
0x2008 3D3C |
|
RW |
32 |
0x0000 0000 |
0x0 3D40 |
0x2008 3D40 |
|
RW |
32 |
0x0000 0000 |
0x0 3D44 |
0x2008 3D44 |
|
RW |
32 |
0x0000 0000 |
0x0 3D48 |
0x2008 3D48 |
|
RW |
32 |
0x0000 0000 |
0x0 3D4C |
0x2008 3D4C |
|
RW |
32 |
0x0000 0000 |
0x0 3D50 |
0x2008 3D50 |
|
RW |
32 |
0x0000 0000 |
0x0 3D54 |
0x2008 3D54 |
|
RW |
32 |
0x0000 0000 |
0x0 3D58 |
0x2008 3D58 |
|
RW |
32 |
0x0000 0000 |
0x0 3D5C |
0x2008 3D5C |
|
RW |
32 |
0x0000 0000 |
0x0 3D60 |
0x2008 3D60 |
|
RW |
32 |
0x0000 0048 |
0x0 3D64 |
0x2008 3D64 |
|
RW |
32 |
0x0000 002C |
0x0 3D68 |
0x2008 3D68 |
|
RW |
32 |
0x0000 0020 |
0x0 3D6C |
0x2008 3D6C |
|
RW |
32 |
0x0000 0004 |
0x0 3D70 |
0x2008 3D70 |
|
RW |
32 |
0x0000 0010 |
0x0 3D74 |
0x2008 3D74 |
|
RW |
32 |
0x0000 0000 |
0x0 3D98 |
0x2008 3D98 |
|
RW |
32 |
0x0000 0000 |
0x0 4000 |
0x2008 4000 |
|
RW |
32 |
0x0000 0001 |
0x0 4008 |
0x2008 4008 |
|
RW |
32 |
0x0000 0001 |
0x0 400C |
0x2008 400C |
|
RW |
32 |
0x0000 0000 |
0x0 4010 |
0x2008 4010 |
|
RW |
32 |
0x0000 0000 |
0x0 4014 |
0x2008 4014 |
|
RW |
32 |
0x0000 0000 |
0x0 4018 |
0x2008 4018 |
|
RW |
32 |
0x0000 0000 |
0x0 401C |
0x2008 401C |
|
RW |
32 |
0x0000 0000 |
0x0 4020 |
0x2008 4020 |
|
RW |
32 |
0x0000 0000 |
0x0 4024 |
0x2008 4024 |
|
RW |
32 |
0x0000 0000 |
0x0 4028 |
0x2008 4028 |
|
RW |
32 |
0x0000 0000 |
0x0 402C |
0x2008 402C |
|
RO |
32 |
0x0000 0000 |
0x0 4030 |
0x2008 4030 |
|
RW |
32 |
0x0000 0000 |
0x0 4034 |
0x2008 4034 |
|
RW |
32 |
0x0000 0000 |
0x0 4038 |
0x2008 4038 |
|
RO |
32 |
0x0000 0000 |
0x0 403C |
0x2008 403C |
|
RW |
32 |
0x0000 0001 |
0x0 4040 |
0x2008 4040 |
|
RW |
32 |
0x0000 001C |
0x0 4044 |
0x2008 4044 |
|
RW |
32 |
0x0000 000B |
0x0 4048 |
0x2008 4048 |
|
RW |
32 |
0x0000 0005 |
0x0 404C |
0x2008 404C |
|
RW |
32 |
0x0000 000B |
0x0 4050 |
0x2008 4050 |
|
RW |
32 |
0x0000 0027 |
0x0 4054 |
0x2008 4054 |
|
RW |
32 |
0x0000 0018 |
0x0 4058 |
0x2008 4058 |
|
RW |
32 |
0x0000 0118 |
0x0 405C |
0x2008 405C |
|
RW |
32 |
0x0000 0006 |
0x0 4060 |
0x2008 4060 |
|
RW |
32 |
0x0000 000C |
0x0 4064 |
0x2008 4064 |
|
RW |
32 |
0x0000 0006 |
0x0 4068 |
0x2008 4068 |
|
RW |
32 |
0x0000 0000 |
0x0 4070 |
0x2008 4070 |
|
RW |
32 |
0x0000 0002 |
0x0 4074 |
0x2008 4074 |
|
RW |
32 |
0x0000 0002 |
0x0 4078 |
0x2008 4078 |
|
RW |
32 |
0x0000 000B |
0x0 4080 |
0x2008 4080 |
|
RW |
32 |
0x0000 0002 |
0x0 4088 |
0x2008 4088 |
|
RW |
32 |
0x0000 0003 |
0x0 408C |
0x2008 408C |
|
RW |
32 |
0x0000 0003 |
0x0 4090 |
0x2008 4090 |
|
RW |
32 |
0x0000 0002 |
0x0 4094 |
0x2008 4094 |
|
RW |
32 |
0x0000 0002 |
0x0 4098 |
0x2008 4098 |
|
RW |
32 |
0x0000 0003 |
0x0 409C |
0x2008 409C |
|
RW |
32 |
0x0000 0003 |
0x0 40A0 |
0x2008 40A0 |
|
RW |
32 |
0x0000 0002 |
0x0 40A4 |
0x2008 40A4 |
|
RW |
32 |
0x0000 0000 |
0x0 40A8 |
0x2008 40A8 |
|
RW |
32 |
0x0000 000C |
0x0 40AC |
0x2008 40AC |
|
RW |
32 |
0x0000 0000 |
0x0 40B0 |
0x2008 40B0 |
|
RW |
32 |
0x0000 0000 |
0x0 40B4 |
0x2008 40B4 |
|
RW |
32 |
0x0000 0000 |
0x0 40B8 |
0x2008 40B8 |
|
RW |
32 |
0x0000 0001 |
0x0 40C4 |
0x2008 40C4 |
|
RW |
32 |
0x0000 0000 |
0x0 40C8 |
0x2008 40C8 |
|
RW |
32 |
0x0000 1860 |
0x0 40CC |
0x2008 40CC |
|
RW |
32 |
0x0002 7100 |
0x0 40D0 |
0x2008 40D0 |
|
RW |
32 |
0x0000 000B |
0x0 40D4 |
0x2008 40D4 |
|
RW |
32 |
0x0000 0010 |
0x0 40D8 |
0x2008 40D8 |
|
RW |
32 |
0x0000 0003 |
0x0 40DC |
0x2008 40DC |
|
RW |
32 |
0x0000 0002 |
0x0 40E0 |
0x2008 40E0 |
|
RW |
32 |
0x0000 0001 |
0x0 40E4 |
0x2008 40E4 |
|
RW |
32 |
0x0000 0008 |
0x0 40E8 |
0x2008 40E8 |
|
RW |
32 |
0x0000 0004 |
0x0 40EC |
0x2008 40EC |
|
RW |
32 |
0x0000 0020 |
0x0 40F0 |
0x2008 40F0 |
|
RW |
32 |
0x0000 0010 |
0x0 40F4 |
0x2008 40F4 |
|
RW |
32 |
0x0000 0080 |
0x0 40F8 |
0x2008 40F8 |
|
RW |
32 |
0x0000 0040 |
0x0 40FC |
0x2008 40FC |
|
RW |
32 |
0x0000 0001 |
0x0 4120 |
0x2008 4120 |
|
RW |
32 |
0x0000 0002 |
0x0 4124 |
0x2008 4124 |
|
RW |
32 |
0x0000 0004 |
0x0 4128 |
0x2008 4128 |
|
RW |
32 |
0x0000 0008 |
0x0 412C |
0x2008 412C |
|
RW |
32 |
0x0000 0010 |
0x0 4130 |
0x2008 4130 |
|
RW |
32 |
0x0000 0020 |
0x0 4134 |
0x2008 4134 |
|
RW |
32 |
0x0000 0040 |
0x0 4138 |
0x2008 4138 |
|
RW |
32 |
0x0000 0080 |
0x0 413C |
0x2008 413C |
|
RW |
32 |
0x0000 0000 |
0x0 4160 |
0x2008 4160 |
|
RW |
32 |
0x0000 0000 |
0x0 4164 |
0x2008 4164 |
|
RW |
32 |
0x0000 0000 |
0x0 4168 |
0x2008 4168 |
|
RW |
32 |
0x0000 0000 |
0x0 416C |
0x2008 416C |
|
RW |
32 |
0x0000 0000 |
0x0 4178 |
0x2008 4178 |
|
RW |
32 |
0x0000 0000 |
0x0 417C |
0x2008 417C |
|
RW |
32 |
0x0000 0000 |
0x0 4180 |
0x2008 4180 |
|
RW |
32 |
0x0000 0000 |
0x0 4184 |
0x2008 4184 |
|
RW |
32 |
0x0000 000C |
0x0 4188 |
0x2008 4188 |
|
RW |
32 |
0x0000 0120 |
0x0 418C |
0x2008 418C |
|
RW |
32 |
0x0000 0200 |
0x0 4190 |
0x2008 4190 |
|
RW |
32 |
0x0000 0120 |
0x0 4194 |
0x2008 4194 |
|
RW |
32 |
0x0000 0000 |
0x0 4198 |
0x2008 4198 |
|
RW |
32 |
0x0000 0008 |
0x0 419C |
0x2008 419C |
|
RW |
32 |
0x0000 0000 |
0x0 41A0 |
0x2008 41A0 |
|
RW |
32 |
0x0000 0000 |
0x0 41A4 |
0x2008 41A4 |
|
RW |
32 |
0x0000 0000 |
0x0 41A8 |
0x2008 41A8 |
|
RW |
32 |
0x0000 0000 |
0x0 41AC |
0x2008 41AC |
|
RW |
32 |
0x0000 0000 |
0x0 41B0 |
0x2008 41B0 |
|
RW |
32 |
0x0000 0000 |
0x0 41B4 |
0x2008 41B4 |
|
RW |
32 |
0x0000 0000 |
0x0 41B8 |
0x2008 41B8 |
|
RW |
32 |
0x0000 0000 |
0x0 41BC |
0x2008 41BC |
|
RW |
32 |
0x0000 3F40 |
0x0 41C0 |
0x2008 41C0 |
|
RW |
32 |
0x0000 0001 |
0x0 41C4 |
0x2008 41C4 |
|
RW |
32 |
0x0000 0008 |
0x0 41C8 |
0x2008 41C8 |
|
RW |
32 |
0x0000 0000 |
0x0 41CC |
0x2008 41CC |
|
RW |
32 |
0x0000 0002 |
0x0 41D0 |
0x2008 41D0 |
|
RW |
32 |
0x0000 0000 |
0x0 41D4 |
0x2008 41D4 |
|
RW |
32 |
0x0000 0000 |
0x0 41DC |
0x2008 41DC |
|
RW |
32 |
0x0000 0000 |
0x0 41E0 |
0x2008 41E0 |
|
RW |
32 |
0x0000 0000 |
0x0 41E4 |
0x2008 41E4 |
|
RW |
32 |
0x0000 0000 |
0x0 41E8 |
0x2008 41E8 |
|
RW |
32 |
0x0000 0000 |
0x0 41EC |
0x2008 41EC |
|
RW |
32 |
0x0000 0000 |
0x0 41F0 |
0x2008 41F0 |
|
RW |
32 |
0x0000 0000 |
0x0 41F4 |
0x2008 41F4 |
|
RW |
32 |
0x0000 0000 |
0x0 41F8 |
0x2008 41F8 |
|
RW |
32 |
0x0000 0000 |
0x0 41FC |
0x2008 41FC |
|
RW |
32 |
0x0000 0000 |
0x0 4200 |
0x2008 4200 |
|
RW |
32 |
0x0000 29B0 |
0x0 4204 |
0x2008 4204 |
|
RW |
32 |
0x0000 0200 |
0x0 4208 |
0x2008 4208 |
|
RW |
32 |
0x0000 0100 |
0x0 420C |
0x2008 420C |
|
RW |
32 |
0x0000 0040 |
0x0 4210 |
0x2008 4210 |
|
RW |
32 |
0x0000 0035 |
0x0 4214 |
0x2008 4214 |
|
RW |
32 |
0x0000 0002 |
0x0 4218 |
0x2008 4218 |
|
RW |
32 |
0x0000 000C |
0x0 421C |
0x2008 421C |
|
RW |
32 |
0x0000 0000 |
0x0 4220 |
0x2008 4220 |
|
RW |
32 |
0x0000 0008 |
0x0 4224 |
0x2008 4224 |
|
RW |
32 |
0x0000 000B |
0x0 4228 |
0x2008 4228 |
|
RW |
32 |
0x0000 0000 |
0x0 422C |
0x2008 422C |
|
RW |
32 |
0x0000 0000 |
0x0 4230 |
0x2008 4230 |
|
RW |
32 |
0x0000 0000 |
0x0 4234 |
0x2008 4234 |
|
RO |
32 |
0x0000 0000 |
0x0 4238 |
0x2008 4238 |
|
RW |
32 |
0x0000 0000 |
0x0 423C |
0x2008 423C |
|
RO |
32 |
0x0000 0000 |
0x0 4240 |
0x2008 4240 |
|
RW |
32 |
0x0000 0000 |
0x0 4244 |
0x2008 4244 |
|
RW |
32 |
0x0000 0000 |
0x0 4248 |
0x2008 4248 |
|
RW |
32 |
0x0000 0000 |
0x0 424C |
0x2008 424C |
|
RO |
32 |
0x0000 0000 |
0x0 4250 |
0x2008 4250 |
|
RO |
32 |
0x0000 0000 |
0x0 4254 |
0x2008 4254 |
|
RW |
32 |
0x0000 0000 |
0x0 4258 |
0x2008 4258 |
|
RW |
32 |
0x0000 0000 |
0x0 425C |
0x2008 425C |
|
RW |
32 |
0x0000 0001 |
0x0 4260 |
0x2008 4260 |
|
RW |
32 |
0x0000 0000 |
0x0 4264 |
0x2008 4264 |
|
RW |
32 |
0x0000 0000 |
0x0 4268 |
0x2008 4268 |
|
RW |
32 |
0x0000 0000 |
0x0 426C |
0x2008 426C |
|
RW |
32 |
0x0000 0000 |
0x0 4270 |
0x2008 4270 |
|
RW |
32 |
0x0000 0000 |
0x0 4274 |
0x2008 4274 |
|
RW |
32 |
0x0000 0000 |
0x0 4278 |
0x2008 4278 |
|
RW |
32 |
0x0000 0000 |
0x0 427C |
0x2008 427C |
|
RW |
32 |
0x0000 0030 |
0x0 4280 |
0x2008 4280 |
|
RW |
32 |
0x0000 0000 |
0x0 4284 |
0x2008 4284 |
|
RW |
32 |
0x0000 0000 |
0x0 4288 |
0x2008 4288 |
|
RW |
32 |
0x0000 0000 |
0x0 428C |
0x2008 428C |
|
RO |
32 |
0x0000 0000 |
0x0 4290 |
0x2008 4290 |
|
RO |
32 |
0x0000 0000 |
0x0 4294 |
0x2008 4294 |
|
RW |
32 |
0x0000 0000 |
0x0 42A0 |
0x2008 42A0 |
|
RW |
32 |
0x0000 0000 |
0x0 42A4 |
0x2008 42A4 |
|
RW |
32 |
0x0000 0000 |
0x0 42A8 |
0x2008 42A8 |
|
RW |
32 |
0x0000 0000 |
0x0 42AC |
0x2008 42AC |
|
RW |
32 |
0x0000 0000 |
0x0 42B0 |
0x2008 42B0 |
|
RW |
32 |
0x0000 0000 |
0x0 42B4 |
0x2008 42B4 |
|
RW |
32 |
0x0000 0000 |
0x0 42BC |
0x2008 42BC |
|
RW |
32 |
0x0000 0000 |
0x0 42C0 |
0x2008 42C0 |
|
RW |
32 |
0x0000 0001 |
0x0 42C4 |
0x2008 42C4 |
|
RW |
32 |
0x0000 0016 |
0x0 42C8 |
0x2008 42C8 |
|
RW |
32 |
0x0000 00C8 |
0x0 42CC |
0x2008 42CC |
|
RW |
32 |
0x0000 0000 |
0x0 42D0 |
0x2008 42D0 |
|
RW |
32 |
0x0000 0000 |
0x0 42D4 |
0x2008 42D4 |
|
RW |
32 |
0x0000 0000 |
0x0 42D8 |
0x2008 42D8 |
|
RW |
32 |
0x0000 0000 |
0x0 42DC |
0x2008 42DC |
|
RW |
32 |
0x0000 0000 |
0x0 42E0 |
0x2008 42E0 |
|
RW |
32 |
0x0000 0001 |
0x0 42E4 |
0x2008 42E4 |
|
RW |
32 |
0x0000 0000 |
0x0 42E8 |
0x2008 42E8 |
|
RW |
32 |
0x0000 0000 |
0x0 42EC |
0x2008 42EC |
|
RW |
32 |
0x0000 0640 |
0x0 42F0 |
0x2008 42F0 |
|
RW |
32 |
0x0000 0000 |
0x0 42F4 |
0x2008 42F4 |
|
RW |
32 |
0x0000 0000 |
0x0 42F8 |
0x2008 42F8 |
|
RW |
32 |
0x0000 0000 |
0x0 42FC |
0x2008 42FC |
|
RW |
32 |
0x0000 0000 |
0x0 4300 |
0x2008 4300 |
|
RW |
32 |
0x0000 0000 |
0x0 4304 |
0x2008 4304 |
|
RW |
32 |
0x0000 0000 |
0x0 4308 |
0x2008 4308 |
|
RW |
32 |
0x0000 0000 |
0x0 430C |
0x2008 430C |
|
RW |
32 |
0x0000 0000 |
0x0 4310 |
0x2008 4310 |
|
RW |
32 |
0x0000 0008 |
0x0 4314 |
0x2008 4314 |
|
RW |
32 |
0x0000 0008 |
0x0 4318 |
0x2008 4318 |
|
RW |
32 |
0x0000 0000 |
0x0 431C |
0x2008 431C |
|
RW |
32 |
0x0000 0000 |
0x0 4320 |
0x2008 4320 |
|
RW |
32 |
0x0000 0000 |
0x0 4324 |
0x2008 4324 |
|
RW |
32 |
0x0000 0000 |
0x0 4328 |
0x2008 4328 |
|
RW |
32 |
0x0000 0000 |
0x0 432C |
0x2008 432C |
|
RW |
32 |
0x0000 0000 |
0x0 4330 |
0x2008 4330 |
|
RO |
32 |
0x0000 0000 |
0x0 4334 |
0x2008 4334 |
|
RW |
32 |
0x0000 0001 |
0x0 4384 |
0x2008 4384 |
|
RW |
32 |
0x0000 0000 |
0x0 43FC |
0x2008 43FC |
|
RW |
32 |
0x0000 0000 |
0x0 4400 |
0x2008 4400 |
|
RW |
32 |
0x0000 0000 |
0x0 4404 |
0x2008 4404 |
|
RW |
32 |
0x0000 0000 |
0x0 4408 |
0x2008 4408 |
|
RW |
32 |
0x0000 0000 |
0x0 440C |
0x2008 440C |
|
RW |
32 |
0x0000 0000 |
0x0 4410 |
0x2008 4410 |
|
RW |
32 |
0x0000 0000 |
0x0 4414 |
0x2008 4414 |
|
RW |
32 |
0x0000 0000 |
0x0 4418 |
0x2008 4418 |
|
RW |
32 |
0x0000 0000 |
0x0 441C |
0x2008 441C |
|
RW |
32 |
0x0000 0008 |
0x0 4420 |
0x2008 4420 |
|
RO |
32 |
0x0000 0000 |
0x0 4424 |
0x2008 4424 |
|
RO |
32 |
0x0000 0000 |
0x0 4428 |
0x2008 4428 |
|
RW |
32 |
0x0000 0000 |
0x0 44B4 |
0x2008 44B4 |
|
RW |
32 |
0x0000 0000 |
0x0 44B8 |
0x2008 44B8 |
|
RW |
32 |
0x0000 0000 |
0x0 44BC |
0x2008 44BC |
|
RW |
32 |
0x0000 0000 |
0x0 44C0 |
0x2008 44C0 |
|
RW |
32 |
0x0000 0000 |
0x0 44C4 |
0x2008 44C4 |
|
RW |
32 |
0x0000 0000 |
0x0 44C8 |
0x2008 44C8 |
|
RW |
32 |
0x0000 0000 |
0x0 44CC |
0x2008 44CC |
|
RW |
32 |
0x0000 0000 |
0x0 4670 |
0x2008 4670 |
|
RW |
32 |
0x0000 0000 |
0x0 467C |
0x2008 467C |
|
RW |
32 |
0x0000 0000 |
0x0 4C00 |
0x2008 4C00 |
|
RW |
32 |
0x0000 0000 |
0x0 4C04 |
0x2008 4C04 |
|
RW |
32 |
0x0000 0000 |
0x0 4C08 |
0x2008 4C08 |
|
RW |
32 |
0x0000 0000 |
0x0 4C0C |
0x2008 4C0C |
|
RW |
32 |
0x0000 0000 |
0x0 4C10 |
0x2008 4C10 |
|
RW |
32 |
0x0000 0000 |
0x0 4C14 |
0x2008 4C14 |
|
RW |
32 |
0x0000 0000 |
0x0 4C18 |
0x2008 4C18 |
|
RW |
32 |
0x0000 0000 |
0x0 4C1C |
0x2008 4C1C |
|
RW |
32 |
0x0000 0001 |
0x0 5000 |
0x2008 5000 |
|
RW |
32 |
0x0000 0001 |
0x0 5004 |
0x2008 5004 |
|
RW |
32 |
0x0000 0001 |
0x0 5008 |
0x2008 5008 |
|
RW |
32 |
0x0000 0001 |
0x0 500C |
0x2008 500C |
|
RW |
32 |
0x0000 00FF |
0x0 5010 |
0x2008 5010 |
|
RW |
32 |
0x0000 0000 |
0x0 5018 |
0x2008 5018 |
|
RW |
32 |
0x0000 0000 |
0x0 501C |
0x2008 501C |
|
RW |
32 |
0x0000 0000 |
0x0 5020 |
0x2008 5020 |
|
RW |
32 |
0x0000 0001 |
0x0 5400 |
0x2008 5400 |
|
RW |
32 |
0x0000 0001 |
0x0 5404 |
0x2008 5404 |
|
RW |
32 |
0x0000 0001 |
0x0 5800 |
0x2008 5800 |
|
RW |
32 |
0x0000 0000 |
0x0 5840 |
0x2008 5840 |
|
RW |
32 |
0x0000 0000 |
0x0 5844 |
0x2008 5844 |
|
RW |
32 |
0x0000 0000 |
0x0 5848 |
0x2008 5848 |
|
RW |
32 |
0x0000 0000 |
0x0 585C |
0x2008 585C |
|
RO |
32 |
0x0000 0000 |
0x0 5860 |
0x2008 5860 |
|
RW |
32 |
0x0000 0000 |
0x0 5C00 |
0x2008 5C00 |
|
RO |
32 |
0x0000 0000 |
0x0 5C04 |
0x2008 5C04 |
|
RO |
32 |
0x0000 0000 |
0x0 5C08 |
0x2008 5C08 |
|
RO |
32 |
0x0000 0000 |
0x0 5C0C |
0x2008 5C0C |
|
RO |
32 |
0x0000 0000 |
0x0 5C10 |
0x2008 5C10 |
|
RO |
32 |
0x0000 0000 |
0x0 5C14 |
0x2008 5C14 |
|
RW |
32 |
0x0000 0000 |
0x0 6400 |
0x2008 6400 |
|
RW |
32 |
0x0000 0000 |
0x0 6404 |
0x2008 6404 |
|
RW |
32 |
0x0000 0000 |
0x0 6408 |
0x2008 6408 |
|
RW |
32 |
0x0000 0000 |
0x0 640C |
0x2008 640C |
|
RW |
32 |
0x0000 0000 |
0x0 6410 |
0x2008 6410 |
|
RW |
32 |
0x0000 0000 |
0x0 6414 |
0x2008 6414 |
|
RW |
32 |
0x0000 0000 |
0x0 6418 |
0x2008 6418 |
|
RO |
32 |
0x0000 0000 |
0x0 641C |
0x2008 641C |
|
RO |
32 |
0x0000 0000 |
0x0 6420 |
0x2008 6420 |
|
RO |
32 |
0x0000 0000 |
0x0 6424 |
0x2008 6424 |
|
RO |
32 |
0x0000 0000 |
0x0 6428 |
0x2008 6428 |
|
RO |
32 |
0x0000 0000 |
0x0 642C |
0x2008 642C |
|
RW |
32 |
0x0000 0000 |
0x0 6430 |
0x2008 6430 |
|
RW |
32 |
0x0000 0000 |
0x0 6434 |
0x2008 6434 |
|
RW |
32 |
0x0000 0000 |
0x0 6438 |
0x2008 6438 |
|
RW |
32 |
0x0000 0000 |
0x0 643C |
0x2008 643C |
|
RW |
32 |
0x0000 0000 |
0x0 6440 |
0x2008 6440 |
|
RW |
32 |
0x0000 0000 |
0x0 6444 |
0x2008 6444 |
|
RW |
32 |
0x0000 0000 |
0x0 6448 |
0x2008 6448 |
|
RW |
32 |
0x0000 0000 |
0x0 644C |
0x2008 644C |
|
RW |
32 |
0x0000 0000 |
0x0 6450 |
0x2008 6450 |
|
RW |
32 |
0x0000 0000 |
0x0 6454 |
0x2008 6454 |
|
RO |
32 |
0x0000 0000 |
0x0 6458 |
0x2008 6458 |
|
RO |
32 |
0x0000 0000 |
0x0 645C |
0x2008 645C |
|
RO |
32 |
0x0000 0000 |
0x0 6460 |
0x2008 6460 |
|
RW |
32 |
0x0000 0000 |
0x0 652C |
0x2008 652C |
|
RO |
32 |
0x0000 0000 |
0x0 6538 |
0x2008 6538 |
|
RO |
32 |
0x0000 0000 |
0x0 6544 |
0x2008 6544 |
|
RW |
32 |
0x0000 0000 |
0x0 6550 |
0x2008 6550 |
|
RW |
32 |
0x0000 0000 |
0x0 7C00 |
0x2008 7C00 |
|
RW |
32 |
0x0000 0000 |
0x0 7C04 |
0x2008 7C04 |
|
RO |
32 |
0x0000 0000 |
0x0 8000 |
0x2008 8000 |
|
RW |
32 |
0x0000 0000 |
0x0 800C |
0x2008 800C |
|
RW |
32 |
0x0000 0000 |
0x0 8010 |
0x2008 8010 |
|
RO |
32 |
0x0000 0000 |
0x0 8014 |
0x2008 8014 |
|
RW |
32 |
0x0000 0014 |
0x1 0000 |
0x2009 0000 |
|
RW |
32 |
0x0000 0005 |
0x1 0004 |
0x2009 0004 |
|
RW |
32 |
0x0000 0005 |
0x1 0008 |
0x2009 0008 |
|
RW |
32 |
0x0000 0001 |
0x1 000C |
0x2009 000C |
|
RW |
32 |
0x0000 0000 |
0x1 0010 |
0x2009 0010 |
|
RW |
32 |
0x0000 0000 |
0x1 0014 |
0x2009 0014 |
|
RO |
32 |
0x0000 0000 |
0x1 0018 |
0x2009 0018 |
|
RW |
32 |
0x0000 0000 |
0x1 001C |
0x2009 001C |
|
RW |
32 |
0x0000 0000 |
0x1 0020 |
0x2009 0020 |
|
RO |
32 |
0x0000 0000 |
0x1 0024 |
0x2009 0024 |
|
RO |
32 |
0x0000 0000 |
0x1 0028 |
0x2009 0028 |
|
RO |
32 |
0x0000 0000 |
0x1 002C |
0x2009 002C |
|
RW |
32 |
0x0000 0000 |
0x1 0030 |
0x2009 0030 |
|
RO |
32 |
0x0000 0000 |
0x1 0034 |
0x2009 0034 |
|
RO |
32 |
0x0000 0000 |
0x1 0038 |
0x2009 0038 |
|
RW |
32 |
0x0000 0000 |
0x1 003C |
0x2009 003C |
|
RW |
32 |
0x0000 0000 |
0x1 0040 |
0x2009 0040 |
|
RW |
32 |
0x0000 0000 |
0x1 0044 |
0x2009 0044 |
|
RW |
32 |
0x0000 0000 |
0x1 0050 |
0x2009 0050 |
|
RW |
32 |
0x0000 0000 |
0x1 2C18 |
0x2009 2C18 |
|
RW |
32 |
0x0000 0000 |
0x1 2C1C |
0x2009 2C1C |
|
RW |
32 |
0x0000 0000 |
0x1 2C20 |
0x2009 2C20 |
|
RW |
32 |
0x0000 0000 |
0x1 2C24 |
0x2009 2C24 |
|
RW |
32 |
0xFFFF FFFF |
0x1 2F18 |
0x2009 2F18 |
|
RW |
32 |
0x0000 0003 |
0x1 2F1C |
0x2009 2F1C |
|
RW |
32 |
0xFFFF FFFF |
0x1 2F20 |
0x2009 2F20 |
|
RW |
32 |
0x0000 0003 |
0x1 2F24 |
0x2009 2F24 |
|
RW |
32 |
0x0000 0000 |
0x1 3218 |
0x2009 3218 |
|
RW |
32 |
0x0000 0000 |
0x1 321C |
0x2009 321C |
|
RW |
32 |
0x0000 0000 |
0x1 3220 |
0x2009 3220 |
|
RW |
32 |
0x0000 0000 |
0x1 3224 |
0x2009 3224 |
|
RW |
32 |
0x0000 0000 |
0x1 3514 |
0x2009 3514 |
|
RW |
32 |
0x0000 0000 |
0x1 3518 |
0x2009 3518 |
|
RW |
32 |
0x0000 0000 |
0x1 3690 |
0x2009 3690 |
|
RW |
32 |
0x0000 000D |
0x3 C000 |
0x200B C000 |
|
RW |
32 |
0x0000 0000 |
0x3 C004 |
0x200B C004 |
|
RW |
32 |
0x0000 0000 |
0x3 C008 |
0x200B C008 |
|
RW |
32 |
0x0000 0000 |
0x3 C00C |
0x200B C00C |
|
RO |
32 |
0x0000 0000 |
0x3 C010 |
0x200B C010 |
|
RW |
32 |
0x0000 0000 |
0x3 C014 |
0x200B C014 |
|
RO |
32 |
0x0000 0000 |
0x3 C018 |
0x200B C018 |
|
RW |
32 |
0x0000 0000 |
0x3 C01C |
0x200B C01C |
|
RW |
32 |
0x0000 0000 |
0x3 C020 |
0x200B C020 |
|
RW |
32 |
0x0000 0000 |
0x3 C024 |
0x200B C024 |
|
RW |
32 |
0x0000 0000 |
0x3 C028 |
0x200B C028 |
|
RW |
32 |
0x0000 0000 |
0x3 C02C |
0x200B C02C |
|
RW |
32 |
0x0000 0000 |
0x3 C030 |
0x200B C030 |
|
RW |
32 |
0x0000 0000 |
0x3 C034 |
0x200B C034 |
|
RW |
32 |
0x0000 0000 |
0x3 C038 |
0x200B C038 |
|
RW |
32 |
0x0000 0000 |
0x3 C03C |
0x200B C03C |
|
RW |
32 |
0x0000 0000 |
0x3 C040 |
0x200B C040 |
|
RW |
32 |
0x0000 0000 |
0x3 C044 |
0x200B C044 |
Address offset |
0x0 2400 |
||
Physical address |
0x2008 2400 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_manual_address_map |
|
RW |
0 |
Address offset |
0x0 2404 |
||
Physical address |
0x2008 2404 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:24 |
reserved |
|
RO |
0x00 |
23:0 |
cfg_chipaddr_map |
|
RW |
0x00 0000 |
Address offset |
0x0 2408 |
||
Physical address |
0x2008 2408 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:18 |
reserved |
|
RO |
0x0000 |
17:0 |
cfg_cidaddr_map |
|
RW |
0x0 0000 |
Address offset |
0x0 240C |
||
Physical address |
0x2008 240C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
reserved |
|
RO |
0x0000 0000 |
2:0 |
cfg_mb_autopch_col_bit_pos_low |
|
RW |
0x4 |
Address offset |
0x0 2410 |
||
Physical address |
0x2008 2410 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
cfg_mb_autopch_col_bit_pos_high |
|
RW |
0xA |
Address offset |
0x0 2414 |
||
Physical address |
0x2008 2414 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_bankaddr_map_0 |
|
RW |
0x0000 0000 |
Address offset |
0x0 2418 |
||
Physical address |
0x2008 2418 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
cfg_bankaddr_map_1 |
|
RW |
0x0 |
Address offset |
0x0 241C |
||
Physical address |
0x2008 241C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_rowaddr_map_0 |
|
RW |
0x0000 0000 |
Address offset |
0x0 2420 |
||
Physical address |
0x2008 2420 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_rowaddr_map_1 |
|
RW |
0x0000 0000 |
Address offset |
0x0 2424 |
||
Physical address |
0x2008 2424 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_rowaddr_map_2 |
|
RW |
0x0000 0000 |
Address offset |
0x0 2428 |
||
Physical address |
0x2008 2428 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:12 |
reserved |
|
RO |
0x0 0000 |
11:0 |
cfg_rowaddr_map_3 |
|
RW |
0x000 |
Address offset |
0x0 242C |
||
Physical address |
0x2008 242C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_coladdr_map_0 |
|
RW |
0x0000 0000 |
Address offset |
0x0 2430 |
||
Physical address |
0x2008 2430 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_coladdr_map_1 |
|
RW |
0x0000 0000 |
Address offset |
0x0 2434 |
||
Physical address |
0x2008 2434 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_coladdr_map_2 |
|
RW |
0x0000 0000 |
Address offset |
0x0 2800 |
||
Physical address |
0x2008 2800 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
reserved |
|
RO |
0x00 0000 |
9:0 |
cfg_vrcg_enable |
|
RW |
0x140 |
Address offset |
0x0 2804 |
||
Physical address |
0x2008 2804 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
reserved |
|
RO |
0x00 0000 |
9:0 |
cfg_vrcg_disable |
|
RW |
0x0A0 |
Address offset |
0x0 2808 |
||
Physical address |
0x2008 2808 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_write_latency_set |
|
RW |
0 |
Address offset |
0x0 280C |
||
Physical address |
0x2008 280C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:2 |
reserved |
|
RO |
0x0000 0000 |
1:0 |
cfg_thermal_offset |
|
RW |
0x0 |
Address offset |
0x0 2810 |
||
Physical address |
0x2008 2810 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
reserved |
|
RO |
0x0000 0000 |
2:0 |
cfg_soc_odt |
|
RW |
0x0 |
Address offset |
0x0 2814 |
||
Physical address |
0x2008 2814 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_odte_ck |
|
RW |
0 |
Address offset |
0x0 2818 |
||
Physical address |
0x2008 2818 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_odte_cs |
|
RW |
0 |
Address offset |
0x0 281C |
||
Physical address |
0x2008 281C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_odtd_ca |
|
RW |
0 |
Address offset |
0x0 2820 |
||
Physical address |
0x2008 2820 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_lpddr4_fsp_op |
|
RW |
0 |
Address offset |
0x0 2824 |
||
Physical address |
0x2008 2824 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_generate_refresh_on_srx |
|
RW |
1 |
Address offset |
0x0 2828 |
||
Physical address |
0x2008 2828 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
reserved |
|
RO |
0x000 0000 |
5:0 |
cfg_dbi_cl |
|
RW |
0x16 |
Address offset |
0x0 282C |
||
Physical address |
0x2008 282C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
reserved |
|
RO |
0x000 0000 |
5:0 |
cfg_non_dbi_cl |
|
RW |
0x16 |
Address offset |
0x0 2830 |
||
Physical address |
0x2008 2830 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:9 |
reserved |
|
RO |
0x00 0000 |
8:0 |
init_force_write_data_0 |
|
RW |
0x000 |
Address offset |
0x0 3C00 |
||
Physical address |
0x2008 3C00 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_write_crc |
|
RW |
0 |
Address offset |
0x0 3C04 |
||
Physical address |
0x2008 3C04 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:2 |
reserved |
|
RO |
0x0000 0000 |
1:0 |
cfg_mpr_read_format |
|
RW |
0x0 |
Address offset |
0x0 3C08 |
||
Physical address |
0x2008 3C08 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:2 |
reserved |
|
RO |
0x0000 0000 |
1:0 |
cfg_wr_cmd_lat_crc_dm |
|
RW |
0x0 |
Address offset |
0x0 3C0C |
||
Physical address |
0x2008 3C0C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
reserved |
|
RO |
0x0000 0000 |
2:0 |
cfg_fine_gran_ref_mode |
|
RW |
0x0 |
Address offset |
0x0 3C10 |
||
Physical address |
0x2008 3C10 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_temp_sensor_readout |
|
RW |
0 |
Address offset |
0x0 3C14 |
||
Physical address |
0x2008 3C14 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_per_dram_addr_en |
|
RW |
0 |
Address offset |
0x0 3C18 |
||
Physical address |
0x2008 3C18 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_geardown_mode |
|
RW |
0 |
Address offset |
0x0 3C1C |
||
Physical address |
0x2008 3C1C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_wr_preamble |
|
RW |
0 |
Address offset |
0x0 3C20 |
||
Physical address |
0x2008 3C20 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_rd_preamble |
|
RW |
0 |
Address offset |
0x0 3C24 |
||
Physical address |
0x2008 3C24 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_rd_preamb_trn_mode |
|
RW |
0 |
Address offset |
0x0 3C28 |
||
Physical address |
0x2008 3C28 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_sr_abort |
|
RW |
0 |
Address offset |
0x0 3C2C |
||
Physical address |
0x2008 3C2C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
reserved |
|
RO |
0x0000 0000 |
2:0 |
cfg_cs_to_cmdaddr_latency |
|
RW |
0x0 |
Address offset |
0x0 3C30 |
||
Physical address |
0x2008 3C30 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_int_vref_mon |
|
RW |
0 |
Address offset |
0x0 3C34 |
||
Physical address |
0x2008 3C34 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_temp_ctrl_ref_mode |
|
RW |
0 |
Address offset |
0x0 3C38 |
||
Physical address |
0x2008 3C38 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_temp_ctrl_ref_range |
|
RW |
0 |
Address offset |
0x0 3C3C |
||
Physical address |
0x2008 3C3C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_max_pwr_down_mode |
|
RW |
0 |
Address offset |
0x0 3C40 |
||
Physical address |
0x2008 3C40 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_read_dbi |
|
RW |
0 |
Address offset |
0x0 3C44 |
||
Physical address |
0x2008 3C44 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_write_dbi |
|
RW |
0 |
Address offset |
0x0 3C48 |
||
Physical address |
0x2008 3C48 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_data_mask |
|
RW |
1 |
Address offset |
0x0 3C4C |
||
Physical address |
0x2008 3C4C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_ca_parity_persist_err |
|
RW |
0 |
Address offset |
0x0 3C50 |
||
Physical address |
0x2008 3C50 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
reserved |
|
RO |
0x0000 0000 |
2:0 |
cfg_rtt_park |
|
RW |
0x0 |
Address offset |
0x0 3C54 |
||
Physical address |
0x2008 3C54 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_odt_inbuf_4_pd |
|
RW |
0 |
Address offset |
0x0 3C58 |
||
Physical address |
0x2008 3C58 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_ca_parity_err_status |
|
RW |
0 |
Address offset |
0x0 3C5C |
||
Physical address |
0x2008 3C5C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_crc_error_clear |
|
RW |
0 |
Address offset |
0x0 3C60 |
||
Physical address |
0x2008 3C60 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
reserved |
|
RO |
0x0000 0000 |
2:0 |
cfg_ca_parity_latency |
|
RW |
0x0 |
Address offset |
0x0 3C64 |
||
Physical address |
0x2008 3C64 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
reserved |
|
RO |
0x0000 0000 |
2:0 |
cfg_ccd_s |
|
RW |
0x0 |
Address offset |
0x0 3C68 |
||
Physical address |
0x2008 3C68 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
cfg_ccd_l |
|
RW |
0x0 |
Address offset |
0x0 3C6C |
||
Physical address |
0x2008 3C6C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_vrefdq_trn_enable |
|
RW |
0 |
Address offset |
0x0 3C70 |
||
Physical address |
0x2008 3C70 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_vrefdq_trn_range |
|
RW |
0 |
Address offset |
0x0 3C74 |
||
Physical address |
0x2008 3C74 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
reserved |
|
RO |
0x000 0000 |
5:0 |
cfg_vrefdq_trn_value |
|
RW |
0x00 |
Address offset |
0x0 3C78 |
||
Physical address |
0x2008 3C78 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:5 |
reserved |
|
RO |
0x000 0000 |
4:0 |
cfg_rrd_s |
|
RW |
0x03 |
Address offset |
0x0 3C7C |
||
Physical address |
0x2008 3C7C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:5 |
reserved |
|
RO |
0x000 0000 |
4:0 |
cfg_rrd_l |
|
RW |
0x03 |
Address offset |
0x0 3C80 |
||
Physical address |
0x2008 3C80 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
cfg_wtr_s |
|
RW |
0x2 |
Address offset |
0x0 3C84 |
||
Physical address |
0x2008 3C84 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
cfg_wtr_l |
|
RW |
0x2 |
Address offset |
0x0 3C88 |
||
Physical address |
0x2008 3C88 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
cfg_wtr_s_crc_dm |
|
RW |
0x2 |
Address offset |
0x0 3C8C |
||
Physical address |
0x2008 3C8C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:5 |
reserved |
|
RO |
0x000 0000 |
4:0 |
cfg_wtr_l_crc_dm |
|
RW |
0x02 |
Address offset |
0x0 3C90 |
||
Physical address |
0x2008 3C90 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
reserved |
|
RO |
0x000 0000 |
5:0 |
cfg_wr_crc_dm |
|
RW |
0x04 |
Address offset |
0x0 3C94 |
||
Physical address |
0x2008 3C94 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
reserved |
|
RO |
0x00 0000 |
9:0 |
cfg_rfc1 |
|
RW |
0x022 |
Address offset |
0x0 3C98 |
||
Physical address |
0x2008 3C98 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
reserved |
|
RO |
0x00 0000 |
9:0 |
cfg_rfc2 |
|
RW |
0x022 |
Address offset |
0x0 3C9C |
||
Physical address |
0x2008 3C9C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
reserved |
|
RO |
0x00 0000 |
9:0 |
cfg_rfc4 |
|
RW |
0x022 |
Address offset |
0x0 3CC4 |
||
Physical address |
0x2008 3CC4 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_nibble_devices |
|
RW |
0 |
Address offset |
0x0 3CE0 |
||
Physical address |
0x2008 3CE0 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_bit_map_index_cs0_0 |
|
RW |
0x0000 0000 |
Address offset |
0x0 3CE4 |
||
Physical address |
0x2008 3CE4 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:22 |
reserved |
|
RO |
0x000 |
21:0 |
cfg_bit_map_index_cs0_1 |
|
RW |
0x00 0000 |
Address offset |
0x0 3CE8 |
||
Physical address |
0x2008 3CE8 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_bit_map_index_cs1_0 |
|
RW |
0x0000 0000 |
Address offset |
0x0 3CEC |
||
Physical address |
0x2008 3CEC |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:22 |
reserved |
|
RO |
0x000 |
21:0 |
cfg_bit_map_index_cs1_1 |
|
RW |
0x00 0000 |
Address offset |
0x0 3CF0 |
||
Physical address |
0x2008 3CF0 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_bit_map_index_cs2_0 |
|
RW |
0x0000 0000 |
Address offset |
0x0 3CF4 |
||
Physical address |
0x2008 3CF4 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:22 |
reserved |
|
RO |
0x000 |
21:0 |
cfg_bit_map_index_cs2_1 |
|
RW |
0x00 0000 |
Address offset |
0x0 3CF8 |
||
Physical address |
0x2008 3CF8 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_bit_map_index_cs3_0 |
|
RW |
0x0000 0000 |
Address offset |
0x0 3CFC |
||
Physical address |
0x2008 3CFC |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:22 |
reserved |
|
RO |
0x000 |
21:0 |
cfg_bit_map_index_cs3_1 |
|
RW |
0x00 0000 |
Address offset |
0x0 3D00 |
||
Physical address |
0x2008 3D00 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_bit_map_index_cs4_0 |
|
RW |
0x0000 0000 |
Address offset |
0x0 3D04 |
||
Physical address |
0x2008 3D04 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:22 |
reserved |
|
RO |
0x000 |
21:0 |
cfg_bit_map_index_cs4_1 |
|
RW |
0x00 0000 |
Address offset |
0x0 3D08 |
||
Physical address |
0x2008 3D08 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_bit_map_index_cs5_0 |
|
RW |
0x0000 0000 |
Address offset |
0x0 3D0C |
||
Physical address |
0x2008 3D0C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:22 |
reserved |
|
RO |
0x000 |
21:0 |
cfg_bit_map_index_cs5_1 |
|
RW |
0x00 0000 |
Address offset |
0x0 3D10 |
||
Physical address |
0x2008 3D10 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_bit_map_index_cs6_0 |
|
RW |
0x0000 0000 |
Address offset |
0x0 3D14 |
||
Physical address |
0x2008 3D14 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:22 |
reserved |
|
RO |
0x000 |
21:0 |
cfg_bit_map_index_cs6_1 |
|
RW |
0x00 0000 |
Address offset |
0x0 3D18 |
||
Physical address |
0x2008 3D18 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_bit_map_index_cs7_0 |
|
RW |
0x0000 0000 |
Address offset |
0x0 3D1C |
||
Physical address |
0x2008 3D1C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:22 |
reserved |
|
RO |
0x000 |
21:0 |
cfg_bit_map_index_cs7_1 |
|
RW |
0x00 0000 |
Address offset |
0x0 3D20 |
||
Physical address |
0x2008 3D20 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_bit_map_index_cs8_0 |
|
RW |
0x0000 0000 |
Address offset |
0x0 3D24 |
||
Physical address |
0x2008 3D24 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:22 |
reserved |
|
RO |
0x000 |
21:0 |
cfg_bit_map_index_cs8_1 |
|
RW |
0x00 0000 |
Address offset |
0x0 3D28 |
||
Physical address |
0x2008 3D28 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_bit_map_index_cs9_0 |
|
RW |
0x0000 0000 |
Address offset |
0x0 3D2C |
||
Physical address |
0x2008 3D2C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:22 |
reserved |
|
RO |
0x000 |
21:0 |
cfg_bit_map_index_cs9_1 |
|
RW |
0x00 0000 |
Address offset |
0x0 3D30 |
||
Physical address |
0x2008 3D30 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_bit_map_index_cs10_0 |
|
RW |
0x0000 0000 |
Address offset |
0x0 3D34 |
||
Physical address |
0x2008 3D34 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:22 |
reserved |
|
RO |
0x000 |
21:0 |
cfg_bit_map_index_cs10_1 |
|
RW |
0x00 0000 |
Address offset |
0x0 3D38 |
||
Physical address |
0x2008 3D38 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_bit_map_index_cs11_0 |
|
RW |
0x0000 0000 |
Address offset |
0x0 3D3C |
||
Physical address |
0x2008 3D3C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:22 |
reserved |
|
RO |
0x000 |
21:0 |
cfg_bit_map_index_cs11_1 |
|
RW |
0x00 0000 |
Address offset |
0x0 3D40 |
||
Physical address |
0x2008 3D40 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_bit_map_index_cs12_0 |
|
RW |
0x0000 0000 |
Address offset |
0x0 3D44 |
||
Physical address |
0x2008 3D44 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:22 |
reserved |
|
RO |
0x000 |
21:0 |
cfg_bit_map_index_cs12_1 |
|
RW |
0x00 0000 |
Address offset |
0x0 3D48 |
||
Physical address |
0x2008 3D48 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_bit_map_index_cs13_0 |
|
RW |
0x0000 0000 |
Address offset |
0x0 3D4C |
||
Physical address |
0x2008 3D4C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:22 |
reserved |
|
RO |
0x000 |
21:0 |
cfg_bit_map_index_cs13_1 |
|
RW |
0x00 0000 |
Address offset |
0x0 3D50 |
||
Physical address |
0x2008 3D50 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_bit_map_index_cs14_0 |
|
RW |
0x0000 0000 |
Address offset |
0x0 3D54 |
||
Physical address |
0x2008 3D54 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:22 |
reserved |
|
RO |
0x000 |
21:0 |
cfg_bit_map_index_cs14_1 |
|
RW |
0x00 0000 |
Address offset |
0x0 3D58 |
||
Physical address |
0x2008 3D58 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_bit_map_index_cs15_0 |
|
RW |
0x0000 0000 |
Address offset |
0x0 3D5C |
||
Physical address |
0x2008 3D5C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:22 |
reserved |
|
RO |
0x000 |
21:0 |
cfg_bit_map_index_cs15_1 |
|
RW |
0x00 0000 |
Address offset |
0x0 3D60 |
||
Physical address |
0x2008 3D60 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
cfg_num_logical_ranks_per_3ds |
|
RW |
0x0 |
Address offset |
0x0 3D64 |
||
Physical address |
0x2008 3D64 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
reserved |
|
RO |
0x00 0000 |
9:0 |
cfg_rfc_dlr1 |
|
RW |
0x048 |
Address offset |
0x0 3D68 |
||
Physical address |
0x2008 3D68 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
reserved |
|
RO |
0x00 0000 |
9:0 |
cfg_rfc_dlr2 |
|
RW |
0x02C |
Address offset |
0x0 3D6C |
||
Physical address |
0x2008 3D6C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
reserved |
|
RO |
0x00 0000 |
9:0 |
cfg_rfc_dlr4 |
|
RW |
0x020 |
Address offset |
0x0 3D70 |
||
Physical address |
0x2008 3D70 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
cfg_rrd_dlr |
|
RW |
0x4 |
Address offset |
0x0 3D74 |
||
Physical address |
0x2008 3D74 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:7 |
reserved |
|
RO |
0x000 0000 |
6:0 |
cfg_faw_dlr |
|
RW |
0x10 |
Address offset |
0x0 3D98 |
||
Physical address |
0x2008 3D98 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
cfg_advance_activate_ready |
|
RW |
0x0 |
Address offset |
0x0 4000 |
||
Physical address |
0x2008 4000 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
ctrlr_soft_reset_n |
|
RW |
0 |
Address offset |
0x0 4008 |
||
Physical address |
0x2008 4008 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_lookahead_pch |
|
RW |
1 |
Address offset |
0x0 400C |
||
Physical address |
0x2008 400C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_lookahead_act |
|
RW |
1 |
Address offset |
0x0 4010 |
||
Physical address |
0x2008 4010 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_autoinit_disable |
|
RW |
0 |
Address offset |
0x0 4014 |
||
Physical address |
0x2008 4014 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_force_reset |
|
RW |
0 |
Address offset |
0x0 4018 |
||
Physical address |
0x2008 4018 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_geardown_en |
|
RW |
0 |
Address offset |
0x0 401C |
||
Physical address |
0x2008 401C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_disable_cke |
|
RW |
0 |
Address offset |
0x0 4020 |
||
Physical address |
0x2008 4020 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
init_cs |
|
RW |
0x00 |
Address offset |
0x0 4024 |
||
Physical address |
0x2008 4024 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_precharge_all |
|
RW |
0 |
Address offset |
0x0 4028 |
||
Physical address |
0x2008 4028 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_refresh |
|
RW |
0 |
Address offset |
0x0 402C |
||
Physical address |
0x2008 402C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_zq_cal_req |
|
RW |
0 |
Address offset |
0x0 4030 |
||
Physical address |
0x2008 4030 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_ack |
|
RO |
0 |
Address offset |
0x0 4034 |
||
Physical address |
0x2008 4034 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:2 |
reserved |
|
RO |
0x0000 0000 |
1:0 |
cfg_bl |
|
RW |
0x0 |
Address offset |
0x0 4038 |
||
Physical address |
0x2008 4038 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
ctrlr_init |
|
RW |
0 |
Address offset |
0x0 403C |
||
Physical address |
0x2008 403C |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
ctrlr_init_done |
|
RO |
0 |
Address offset |
0x0 4040 |
||
Physical address |
0x2008 4040 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_auto_ref_en |
|
RW |
1 |
Address offset |
0x0 4044 |
||
Physical address |
0x2008 4044 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:7 |
reserved |
|
RO |
0x000 0000 |
6:0 |
cfg_ras |
|
RW |
0x1C |
Address offset |
0x0 4048 |
||
Physical address |
0x2008 4048 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:7 |
reserved |
|
RO |
0x000 0000 |
6:0 |
cfg_rcd |
|
RW |
0x0B |
Address offset |
0x0 404C |
||
Physical address |
0x2008 404C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:5 |
reserved |
|
RO |
0x000 0000 |
4:0 |
cfg_rrd |
|
RW |
0x05 |
Address offset |
0x0 4050 |
||
Physical address |
0x2008 4050 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
reserved |
|
RO |
0x000 0000 |
5:0 |
cfg_rp |
|
RW |
0x0B |
Address offset |
0x0 4054 |
||
Physical address |
0x2008 4054 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
cfg_rc |
|
RW |
0x27 |
Address offset |
0x0 4058 |
||
Physical address |
0x2008 4058 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:9 |
reserved |
|
RO |
0x00 0000 |
8:0 |
cfg_faw |
|
RW |
0x018 |
Address offset |
0x0 405C |
||
Physical address |
0x2008 405C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
reserved |
|
RO |
0x00 0000 |
9:0 |
cfg_rfc |
|
RW |
0x118 |
Address offset |
0x0 4060 |
||
Physical address |
0x2008 4060 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:5 |
reserved |
|
RO |
0x000 0000 |
4:0 |
cfg_rtp |
|
RW |
0x06 |
Address offset |
0x0 4064 |
||
Physical address |
0x2008 4064 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
reserved |
|
RO |
0x000 0000 |
5:0 |
cfg_wr |
|
RW |
0x0C |
Address offset |
0x0 4068 |
||
Physical address |
0x2008 4068 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:5 |
reserved |
|
RO |
0x000 0000 |
4:0 |
cfg_wtr |
|
RW |
0x06 |
Address offset |
0x0 4070 |
||
Physical address |
0x2008 4070 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
reserved |
|
RO |
0x0000 0000 |
2:0 |
cfg_pasr |
|
RW |
0x0 |
Address offset |
0x0 4074 |
||
Physical address |
0x2008 4074 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:5 |
reserved |
|
RO |
0x000 0000 |
4:0 |
cfg_xp |
|
RW |
0x02 |
Address offset |
0x0 4078 |
||
Physical address |
0x2008 4078 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
reserved |
|
RO |
0x00 0000 |
9:0 |
cfg_xsr |
|
RW |
0x002 |
Address offset |
0x0 4080 |
||
Physical address |
0x2008 4080 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
reserved |
|
RO |
0x000 0000 |
5:0 |
cfg_cl |
|
RW |
0x0B |
Address offset |
0x0 4088 |
||
Physical address |
0x2008 4088 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
cfg_read_to_write |
|
RW |
0x2 |
Address offset |
0x0 408C |
||
Physical address |
0x2008 408C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
cfg_write_to_write |
|
RW |
0x3 |
Address offset |
0x0 4090 |
||
Physical address |
0x2008 4090 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
cfg_read_to_read |
|
RW |
0x3 |
Address offset |
0x0 4094 |
||
Physical address |
0x2008 4094 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:5 |
reserved |
|
RO |
0x000 0000 |
4:0 |
cfg_write_to_read |
|
RW |
0x02 |
Address offset |
0x0 4098 |
||
Physical address |
0x2008 4098 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
cfg_read_to_write_odt |
|
RW |
0x2 |
Address offset |
0x0 409C |
||
Physical address |
0x2008 409C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
cfg_write_to_write_odt |
|
RW |
0x3 |
Address offset |
0x0 40A0 |
||
Physical address |
0x2008 40A0 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
cfg_read_to_read_odt |
|
RW |
0x3 |
Address offset |
0x0 40A4 |
||
Physical address |
0x2008 40A4 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:5 |
reserved |
|
RO |
0x000 0000 |
4:0 |
cfg_write_to_read_odt |
|
RW |
0x02 |
Address offset |
0x0 40A8 |
||
Physical address |
0x2008 40A8 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
reserved |
|
RO |
0x0000 0000 |
2:0 |
cfg_min_read_idle |
|
RW |
0x0 |
Address offset |
0x0 40AC |
||
Physical address |
0x2008 40AC |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:7 |
reserved |
|
RO |
0x000 0000 |
6:0 |
cfg_mrd |
|
RW |
0x0C |
Address offset |
0x0 40B0 |
||
Physical address |
0x2008 40B0 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_bt |
|
RW |
0 |
Address offset |
0x0 40B4 |
||
Physical address |
0x2008 40B4 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
cfg_ds |
|
RW |
0x0 |
Address offset |
0x0 40B8 |
||
Physical address |
0x2008 40B8 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_qoff |
|
RW |
0 |
Address offset |
0x0 40C4 |
||
Physical address |
0x2008 40C4 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
reserved |
|
RO |
0x0000 0000 |
2:0 |
cfg_rtt |
|
RW |
0x1 |
Address offset |
0x0 40C8 |
||
Physical address |
0x2008 40C8 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_dll_disable |
|
RW |
0 |
Address offset |
0x0 40CC |
||
Physical address |
0x2008 40CC |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
reserved |
|
RO |
0x0000 |
15:0 |
cfg_ref_per |
|
RW |
0x1860 |
Address offset |
0x0 40D0 |
||
Physical address |
0x2008 40D0 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:19 |
reserved |
|
RO |
0x0000 |
18:0 |
cfg_startup_delay |
|
RW |
0x2 7100 |
Address offset |
0x0 40D4 |
||
Physical address |
0x2008 40D4 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
cfg_mem_colbits |
|
RW |
0xB |
Address offset |
0x0 40D8 |
||
Physical address |
0x2008 40D8 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:5 |
reserved |
|
RO |
0x000 0000 |
4:0 |
cfg_mem_rowbits |
|
RW |
0x10 |
Address offset |
0x0 40DC |
||
Physical address |
0x2008 40DC |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
reserved |
|
RO |
0x0000 0000 |
2:0 |
cfg_mem_bankbits |
|
RW |
0x3 |
Address offset |
0x0 40E0 |
||
Physical address |
0x2008 40E0 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
cfg_odt_rd_map_cs0 |
|
RW |
0x02 |
Address offset |
0x0 40E4 |
||
Physical address |
0x2008 40E4 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
cfg_odt_rd_map_cs1 |
|
RW |
0x01 |
Address offset |
0x0 40E8 |
||
Physical address |
0x2008 40E8 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
cfg_odt_rd_map_cs2 |
|
RW |
0x08 |
Address offset |
0x0 40EC |
||
Physical address |
0x2008 40EC |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
cfg_odt_rd_map_cs3 |
|
RW |
0x04 |
Address offset |
0x0 40F0 |
||
Physical address |
0x2008 40F0 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
cfg_odt_rd_map_cs4 |
|
RW |
0x20 |
Address offset |
0x0 40F4 |
||
Physical address |
0x2008 40F4 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
cfg_odt_rd_map_cs5 |
|
RW |
0x10 |
Address offset |
0x0 40F8 |
||
Physical address |
0x2008 40F8 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
cfg_odt_rd_map_cs6 |
|
RW |
0x80 |
Address offset |
0x0 40FC |
||
Physical address |
0x2008 40FC |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
cfg_odt_rd_map_cs7 |
|
RW |
0x40 |
Address offset |
0x0 4120 |
||
Physical address |
0x2008 4120 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
cfg_odt_wr_map_cs0 |
|
RW |
0x01 |
Address offset |
0x0 4124 |
||
Physical address |
0x2008 4124 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
cfg_odt_wr_map_cs1 |
|
RW |
0x02 |
Address offset |
0x0 4128 |
||
Physical address |
0x2008 4128 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
cfg_odt_wr_map_cs2 |
|
RW |
0x04 |
Address offset |
0x0 412C |
||
Physical address |
0x2008 412C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
cfg_odt_wr_map_cs3 |
|
RW |
0x08 |
Address offset |
0x0 4130 |
||
Physical address |
0x2008 4130 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
cfg_odt_wr_map_cs4 |
|
RW |
0x10 |
Address offset |
0x0 4134 |
||
Physical address |
0x2008 4134 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
cfg_odt_wr_map_cs5 |
|
RW |
0x20 |
Address offset |
0x0 4138 |
||
Physical address |
0x2008 4138 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
cfg_odt_wr_map_cs6 |
|
RW |
0x40 |
Address offset |
0x0 413C |
||
Physical address |
0x2008 413C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
cfg_odt_wr_map_cs7 |
|
RW |
0x80 |
Address offset |
0x0 4160 |
||
Physical address |
0x2008 4160 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
cfg_odt_rd_turn_on |
|
RW |
0x0 |
Address offset |
0x0 4164 |
||
Physical address |
0x2008 4164 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
cfg_odt_wr_turn_on |
|
RW |
0x0 |
Address offset |
0x0 4168 |
||
Physical address |
0x2008 4168 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
cfg_odt_rd_turn_off |
|
RW |
0x0 |
Address offset |
0x0 416C |
||
Physical address |
0x2008 416C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
cfg_odt_wr_turn_off |
|
RW |
0x0 |
Address offset |
0x0 4178 |
||
Physical address |
0x2008 4178 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
reserved |
|
RO |
0x0000 |
15:0 |
cfg_emr3 |
|
RW |
0x0000 |
Address offset |
0x0 417C |
||
Physical address |
0x2008 417C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_two_t |
|
RW |
0 |
Address offset |
0x0 4180 |
||
Physical address |
0x2008 4180 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_two_t_sel_cycle |
|
RW |
0 |
Address offset |
0x0 4184 |
||
Physical address |
0x2008 4184 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_regdimm |
|
RW |
0 |
Address offset |
0x0 4188 |
||
Physical address |
0x2008 4188 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:5 |
reserved |
|
RO |
0x000 0000 |
4:0 |
cfg_mod |
|
RW |
0x0C |
Address offset |
0x0 418C |
||
Physical address |
0x2008 418C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
reserved |
|
RO |
0x00 0000 |
9:0 |
cfg_xs |
|
RW |
0x120 |
Address offset |
0x0 4190 |
||
Physical address |
0x2008 4190 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:11 |
reserved |
|
RO |
0x00 0000 |
10:0 |
cfg_xsdll |
|
RW |
0x200 |
Address offset |
0x0 4194 |
||
Physical address |
0x2008 4194 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
reserved |
|
RO |
0x00 0000 |
9:0 |
cfg_xpr |
|
RW |
0x120 |
Address offset |
0x0 4198 |
||
Physical address |
0x2008 4198 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:2 |
reserved |
|
RO |
0x0000 0000 |
1:0 |
cfg_al_mode |
|
RW |
0x0 |
Address offset |
0x0 419C |
||
Physical address |
0x2008 419C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:5 |
reserved |
|
RO |
0x000 0000 |
4:0 |
cfg_cwl |
|
RW |
0x08 |
Address offset |
0x0 41A0 |
||
Physical address |
0x2008 41A0 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:2 |
reserved |
|
RO |
0x0000 0000 |
1:0 |
cfg_bl_mode |
|
RW |
0x0 |
Address offset |
0x0 41A4 |
||
Physical address |
0x2008 41A4 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_tdqs |
|
RW |
0 |
Address offset |
0x0 41A8 |
||
Physical address |
0x2008 41A8 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
reserved |
|
RO |
0x0000 0000 |
2:0 |
cfg_rtt_wr |
|
RW |
0x0 |
Address offset |
0x0 41AC |
||
Physical address |
0x2008 41AC |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:2 |
reserved |
|
RO |
0x0000 0000 |
1:0 |
cfg_lp_asr |
|
RW |
0x0 |
Address offset |
0x0 41B0 |
||
Physical address |
0x2008 41B0 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_auto_sr |
|
RW |
0 |
Address offset |
0x0 41B4 |
||
Physical address |
0x2008 41B4 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_srt |
|
RW |
0 |
Address offset |
0x0 41B8 |
||
Physical address |
0x2008 41B8 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
cfg_addr_mirror |
|
RW |
0x00 |
Address offset |
0x0 41BC |
||
Physical address |
0x2008 41BC |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:2 |
reserved |
|
RO |
0x0000 0000 |
1:0 |
cfg_zq_cal_type |
|
RW |
0x0 |
Address offset |
0x0 41C0 |
||
Physical address |
0x2008 41C0 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_zq_cal_per |
|
RW |
0x0000 3F40 |
Address offset |
0x0 41C4 |
||
Physical address |
0x2008 41C4 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_auto_zq_cal_en |
|
RW |
1 |
Address offset |
0x0 41C8 |
||
Physical address |
0x2008 41C8 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
reserved |
|
RO |
0x0000 |
15:0 |
cfg_memory_type |
|
RW |
0x0008 |
Address offset |
0x0 41CC |
||
Physical address |
0x2008 41CC |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_only_srank_cmds |
|
RW |
0 |
Address offset |
0x0 41D0 |
||
Physical address |
0x2008 41D0 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:5 |
reserved |
|
RO |
0x000 0000 |
4:0 |
cfg_num_ranks |
|
RW |
0x02 |
Address offset |
0x0 41D4 |
||
Physical address |
0x2008 41D4 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_quad_rank |
|
RW |
0 |
Address offset |
0x0 41DC |
||
Physical address |
0x2008 41DC |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
reserved |
|
RO |
0x0000 0000 |
2:0 |
cfg_early_rank_to_wr_start |
|
RW |
0x0 |
Address offset |
0x0 41E0 |
||
Physical address |
0x2008 41E0 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
reserved |
|
RO |
0x0000 0000 |
2:0 |
cfg_early_rank_to_rd_start |
|
RW |
0x0 |
Address offset |
0x0 41E4 |
||
Physical address |
0x2008 41E4 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
cfg_pasr_bank |
|
RW |
0x00 |
Address offset |
0x0 41E8 |
||
Physical address |
0x2008 41E8 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
cfg_pasr_seg |
|
RW |
0x00 |
Address offset |
0x0 41EC |
||
Physical address |
0x2008 41EC |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_mrr_mode |
|
RW |
0 |
Address offset |
0x0 41F0 |
||
Physical address |
0x2008 41F0 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_mr_w_req |
|
RW |
0 |
Address offset |
0x0 41F4 |
||
Physical address |
0x2008 41F4 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
init_mr_addr |
|
RW |
0x00 |
Address offset |
0x0 41F8 |
||
Physical address |
0x2008 41F8 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:18 |
reserved |
|
RO |
0x0000 |
17:0 |
init_mr_wr_data |
|
RW |
0x0 0000 |
Address offset |
0x0 41FC |
||
Physical address |
0x2008 41FC |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:18 |
reserved |
|
RO |
0x0000 |
17:0 |
init_mr_wr_mask |
|
RW |
0x0 0000 |
Address offset |
0x0 4200 |
||
Physical address |
0x2008 4200 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_nop |
|
RW |
0 |
Address offset |
0x0 4204 |
||
Physical address |
0x2008 4204 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
reserved |
|
RO |
0x0000 |
15:0 |
cfg_init_duration |
|
RW |
0x29B0 |
Address offset |
0x0 4208 |
||
Physical address |
0x2008 4208 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:12 |
reserved |
|
RO |
0x0 0000 |
11:0 |
cfg_zqinit_cal_duration |
|
RW |
0x200 |
Address offset |
0x0 420C |
||
Physical address |
0x2008 420C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:11 |
reserved |
|
RO |
0x00 0000 |
10:0 |
cfg_zq_cal_l_duration |
|
RW |
0x100 |
Address offset |
0x0 4210 |
||
Physical address |
0x2008 4210 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:11 |
reserved |
|
RO |
0x00 0000 |
10:0 |
cfg_zq_cal_s_duration |
|
RW |
0x040 |
Address offset |
0x0 4214 |
||
Physical address |
0x2008 4214 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:11 |
reserved |
|
RO |
0x00 0000 |
10:0 |
cfg_zq_cal_r_duration |
|
RW |
0x035 |
Address offset |
0x0 4218 |
||
Physical address |
0x2008 4218 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
cfg_mrr |
|
RW |
0x2 |
Address offset |
0x0 421C |
||
Physical address |
0x2008 421C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:5 |
reserved |
|
RO |
0x000 0000 |
4:0 |
cfg_mrw |
|
RW |
0x0C |
Address offset |
0x0 4220 |
||
Physical address |
0x2008 4220 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_odt_powerdown |
|
RW |
0 |
Address offset |
0x0 4224 |
||
Physical address |
0x2008 4224 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
reserved |
|
RO |
0x000 0000 |
5:0 |
cfg_wl |
|
RW |
0x08 |
Address offset |
0x0 4228 |
||
Physical address |
0x2008 4228 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
reserved |
|
RO |
0x000 0000 |
5:0 |
cfg_rl |
|
RW |
0x0B |
Address offset |
0x0 422C |
||
Physical address |
0x2008 422C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:22 |
reserved |
|
RO |
0x000 |
21:0 |
cfg_cal_read_period |
|
RW |
0x00 0000 |
Address offset |
0x0 4230 |
||
Physical address |
0x2008 4230 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:2 |
reserved |
|
RO |
0x0000 0000 |
1:0 |
cfg_num_cal_reads |
|
RW |
0x0 |
Address offset |
0x0 4234 |
||
Physical address |
0x2008 4234 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
init_self_refresh |
|
RW |
0x00 |
Address offset |
0x0 4238 |
||
Physical address |
0x2008 4238 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
init_self_refresh_status |
|
RO |
0x00 |
Address offset |
0x0 423C |
||
Physical address |
0x2008 423C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
init_power_down |
|
RW |
0x00 |
Address offset |
0x0 4240 |
||
Physical address |
0x2008 4240 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
init_power_down_status |
|
RO |
0x00 |
Address offset |
0x0 4244 |
||
Physical address |
0x2008 4244 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_force_write |
|
RW |
0 |
Address offset |
0x0 4248 |
||
Physical address |
0x2008 4248 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
init_force_write_cs |
|
RW |
0x00 |
Address offset |
0x0 424C |
||
Physical address |
0x2008 424C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_ctrlr_init_disable |
|
RW |
0 |
Address offset |
0x0 4250 |
||
Physical address |
0x2008 4250 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
ctrlr_ready |
|
RO |
0 |
Address offset |
0x0 4254 |
||
Physical address |
0x2008 4254 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_rdimm_ready |
|
RO |
0 |
Address offset |
0x0 4258 |
||
Physical address |
0x2008 4258 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_rdimm_complete |
|
RW |
0 |
Address offset |
0x0 425C |
||
Physical address |
0x2008 425C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
reserved |
|
RO |
0x0000 0000 |
2:0 |
cfg_rdimm_lat |
|
RW |
0x0 |
Address offset |
0x0 4260 |
||
Physical address |
0x2008 4260 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_rdimm_bside_invert |
|
RW |
1 |
Address offset |
0x0 4264 |
||
Physical address |
0x2008 4264 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_lrdimm |
|
RW |
0 |
Address offset |
0x0 4268 |
||
Physical address |
0x2008 4268 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_memory_reset_mask |
|
RW |
0 |
Address offset |
0x0 426C |
||
Physical address |
0x2008 426C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_rd_preamb_toggle |
|
RW |
0 |
Address offset |
0x0 4270 |
||
Physical address |
0x2008 4270 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_rd_postamble |
|
RW |
0 |
Address offset |
0x0 4274 |
||
Physical address |
0x2008 4274 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_pu_cal |
|
RW |
0 |
Address offset |
0x0 4278 |
||
Physical address |
0x2008 4278 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
reserved |
|
RO |
0x0000 0000 |
2:0 |
cfg_dq_odt |
|
RW |
0x0 |
Address offset |
0x0 427C |
||
Physical address |
0x2008 427C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
reserved |
|
RO |
0x0000 0000 |
2:0 |
cfg_ca_odt |
|
RW |
0x0 |
Address offset |
0x0 4280 |
||
Physical address |
0x2008 4280 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
cfg_zqlatch_duration |
|
RW |
0x30 |
Address offset |
0x0 4284 |
||
Physical address |
0x2008 4284 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_cal_select |
|
RW |
0 |
Address offset |
0x0 4288 |
||
Physical address |
0x2008 4288 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_cal_l_r_req |
|
RW |
0 |
Address offset |
0x0 428C |
||
Physical address |
0x2008 428C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
init_cal_l_b_size |
|
RW |
0x0 |
Address offset |
0x0 4290 |
||
Physical address |
0x2008 4290 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_cal_l_r_ack |
|
RO |
0 |
Address offset |
0x0 4294 |
||
Physical address |
0x2008 4294 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_cal_l_read_complete |
|
RO |
0 |
Address offset |
0x0 42A0 |
||
Physical address |
0x2008 42A0 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_rwfifo |
|
RW |
0 |
Address offset |
0x0 42A4 |
||
Physical address |
0x2008 42A4 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_rd_dqcal |
|
RW |
0 |
Address offset |
0x0 42A8 |
||
Physical address |
0x2008 42A8 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_start_dqsosc |
|
RW |
0 |
Address offset |
0x0 42AC |
||
Physical address |
0x2008 42AC |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_stop_dqsosc |
|
RW |
0 |
Address offset |
0x0 42B0 |
||
Physical address |
0x2008 42B0 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_zq_cal_start |
|
RW |
0 |
Address offset |
0x0 42B4 |
||
Physical address |
0x2008 42B4 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_wr_postamble |
|
RW |
0 |
Address offset |
0x0 42BC |
||
Physical address |
0x2008 42BC |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
init_cal_l_addr_0 |
|
RW |
0x0000 0000 |
Address offset |
0x0 42C0 |
||
Physical address |
0x2008 42C0 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:7 |
reserved |
|
RO |
0x000 0000 |
6:0 |
init_cal_l_addr_1 |
|
RW |
0x00 |
Address offset |
0x0 42C4 |
||
Physical address |
0x2008 42C4 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
reserved |
|
RO |
0x0000 0000 |
2:0 |
cfg_ctrlupd_trig |
|
RW |
0x1 |
Address offset |
0x0 42C8 |
||
Physical address |
0x2008 42C8 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
reserved |
|
RO |
0x00 0000 |
9:0 |
cfg_ctrlupd_start_delay |
|
RW |
0x016 |
Address offset |
0x0 42CC |
||
Physical address |
0x2008 42CC |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
reserved |
|
RO |
0x00 0000 |
9:0 |
cfg_dfi_t_ctrlupd_max |
|
RW |
0x0C8 |
Address offset |
0x0 42D0 |
||
Physical address |
0x2008 42D0 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_ctrlr_busy_sel |
|
RW |
0 |
Address offset |
0x0 42D4 |
||
Physical address |
0x2008 42D4 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_ctrlr_busy_value |
|
RW |
0 |
Address offset |
0x0 42D8 |
||
Physical address |
0x2008 42D8 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:9 |
reserved |
|
RO |
0x00 0000 |
8:0 |
cfg_ctrlr_busy_turn_off_delay |
|
RW |
0x000 |
Address offset |
0x0 42DC |
||
Physical address |
0x2008 42DC |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:7 |
reserved |
|
RO |
0x000 0000 |
6:0 |
cfg_ctrlr_busy_slow_restart_window |
|
RW |
0x00 |
Address offset |
0x0 42E0 |
||
Physical address |
0x2008 42E0 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:7 |
reserved |
|
RO |
0x000 0000 |
6:0 |
cfg_ctrlr_busy_restart_holdoff |
|
RW |
0x00 |
Address offset |
0x0 42E4 |
||
Physical address |
0x2008 42E4 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_parity_rdimm_delay |
|
RW |
1 |
Address offset |
0x0 42E8 |
||
Physical address |
0x2008 42E8 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_ctrlr_busy_enable |
|
RW |
0 |
Address offset |
0x0 42EC |
||
Physical address |
0x2008 42EC |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_async_odt |
|
RW |
0 |
Address offset |
0x0 42F0 |
||
Physical address |
0x2008 42F0 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:12 |
reserved |
|
RO |
0x0 0000 |
11:0 |
cfg_zq_cal_duration |
|
RW |
0x640 |
Address offset |
0x0 42F4 |
||
Physical address |
0x2008 42F4 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
reserved |
|
RO |
0x000 0000 |
5:0 |
cfg_mrri |
|
RW |
0x00 |
Address offset |
0x0 42F8 |
||
Physical address |
0x2008 42F8 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_odt_force_en |
|
RW |
0 |
Address offset |
0x0 42FC |
||
Physical address |
0x2008 42FC |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
reserved |
|
RO |
0x0000 0000 |
2:0 |
init_odt_force_rank |
|
RW |
0x0 |
Address offset |
0x0 4300 |
||
Physical address |
0x2008 4300 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
reserved |
|
RO |
0x00 0000 |
9:0 |
cfg_phyupd_ack_delay |
|
RW |
0x000 |
Address offset |
0x0 4304 |
||
Physical address |
0x2008 4304 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_mirror_x16_bg0_bg1 |
|
RW |
0 |
Address offset |
0x0 4308 |
||
Physical address |
0x2008 4308 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_pda_mr_w_req |
|
RW |
0 |
Address offset |
0x0 430C |
||
Physical address |
0x2008 430C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:18 |
reserved |
|
RO |
0x0000 |
17:0 |
init_pda_nibble_select |
|
RW |
0x0 0000 |
Address offset |
0x0 4310 |
||
Physical address |
0x2008 4310 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_dram_clk_disable_in_self_refresh |
|
RW |
0 |
Address offset |
0x0 4314 |
||
Physical address |
0x2008 4314 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:5 |
reserved |
|
RO |
0x000 0000 |
4:0 |
cfg_cksre |
|
RW |
0x08 |
Address offset |
0x0 4318 |
||
Physical address |
0x2008 4318 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:5 |
reserved |
|
RO |
0x000 0000 |
4:0 |
cfg_cksrx |
|
RW |
0x08 |
Address offset |
0x0 431C |
||
Physical address |
0x2008 431C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:14 |
reserved |
|
RO |
0x0 0000 |
13:0 |
cfg_rcd_stab |
|
RW |
0x0000 |
Address offset |
0x0 4320 |
||
Physical address |
0x2008 4320 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
cfg_dfi_t_ctrl_delay |
|
RW |
0x00 |
Address offset |
0x0 4324 |
||
Physical address |
0x2008 4324 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
cfg_dfi_t_dram_clk_enable |
|
RW |
0x00 |
Address offset |
0x0 4328 |
||
Physical address |
0x2008 4328 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_idle_time_to_self_refresh |
|
RW |
0x0000 0000 |
Address offset |
0x0 432C |
||
Physical address |
0x2008 432C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_idle_time_to_power_down |
|
RW |
0x0000 0000 |
Address offset |
0x0 4330 |
||
Physical address |
0x2008 4330 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_burst_rw_refresh_holdoff |
|
RW |
0 |
Address offset |
0x0 4334 |
||
Physical address |
0x2008 4334 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
reserved |
|
RO |
0x000 0000 |
5:0 |
init_refresh_count |
|
RO |
0x00 |
Address offset |
0x0 4384 |
||
Physical address |
0x2008 4384 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_bg_interleave |
|
RW |
1 |
Address offset |
0x0 43FC |
||
Physical address |
0x2008 43FC |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_refresh_during_phy_training |
|
RW |
0 |
Address offset |
0x0 4400 |
||
Physical address |
0x2008 4400 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
mt_en |
|
RW |
0 |
Address offset |
0x0 4404 |
||
Physical address |
0x2008 4404 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
mt_en_single |
|
RW |
0 |
Address offset |
0x0 4408 |
||
Physical address |
0x2008 4408 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
mt_stop_on_error |
|
RW |
0 |
Address offset |
0x0 440C |
||
Physical address |
0x2008 440C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
mt_rd_only |
|
RW |
0 |
Address offset |
0x0 4410 |
||
Physical address |
0x2008 4410 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
mt_wr_only |
|
RW |
0 |
Address offset |
0x0 4414 |
||
Physical address |
0x2008 4414 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
mt_data_pattern |
|
RW |
0x0 |
Address offset |
0x0 4418 |
||
Physical address |
0x2008 4418 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:2 |
reserved |
|
RO |
0x0000 0000 |
1:0 |
mt_addr_pattern |
|
RW |
0x0 |
Address offset |
0x0 441C |
||
Physical address |
0x2008 441C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
mt_data_invert |
|
RW |
0 |
Address offset |
0x0 4420 |
||
Physical address |
0x2008 4420 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
reserved |
|
RO |
0x000 0000 |
5:0 |
mt_addr_bits |
|
RW |
0x08 |
Address offset |
0x0 4424 |
||
Physical address |
0x2008 4424 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
mt_error_sts |
|
RO |
0 |
Address offset |
0x0 4428 |
||
Physical address |
0x2008 4428 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
mt_done_ack |
|
RO |
0 |
Address offset |
0x0 44B4 |
||
Physical address |
0x2008 44B4 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
mt_start_addr_0 |
|
RW |
0x0000 0000 |
Address offset |
0x0 44B8 |
||
Physical address |
0x2008 44B8 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:7 |
reserved |
|
RO |
0x000 0000 |
6:0 |
mt_start_addr_1 |
|
RW |
0x00 |
Address offset |
0x0 44BC |
||
Physical address |
0x2008 44BC |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
mt_error_mask_0 |
|
RW |
0x0000 0000 |
Address offset |
0x0 44C0 |
||
Physical address |
0x2008 44C0 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
mt_error_mask_1 |
|
RW |
0x0000 0000 |
Address offset |
0x0 44C4 |
||
Physical address |
0x2008 44C4 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
mt_error_mask_2 |
|
RW |
0x0000 0000 |
Address offset |
0x0 44C8 |
||
Physical address |
0x2008 44C8 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
mt_error_mask_3 |
|
RW |
0x0000 0000 |
Address offset |
0x0 44CC |
||
Physical address |
0x2008 44CC |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
reserved |
|
RO |
0x0000 |
15:0 |
mt_error_mask_4 |
|
RW |
0x0000 |
Address offset |
0x0 4670 |
||
Physical address |
0x2008 4670 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
mt_user_data_pattern |
|
RW |
0x00 |
Address offset |
0x0 467C |
||
Physical address |
0x2008 467C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
mt_alg_auto_pch |
|
RW |
0 |
Address offset |
0x0 4C00 |
||
Physical address |
0x2008 4C00 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:12 |
reserved |
|
RO |
0x0 0000 |
11:0 |
cfg_starve_timeout_p0 |
|
RW |
0x000 |
Address offset |
0x0 4C04 |
||
Physical address |
0x2008 4C04 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:12 |
reserved |
|
RO |
0x0 0000 |
11:0 |
cfg_starve_timeout_p1 |
|
RW |
0x000 |
Address offset |
0x0 4C08 |
||
Physical address |
0x2008 4C08 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:12 |
reserved |
|
RO |
0x0 0000 |
11:0 |
cfg_starve_timeout_p2 |
|
RW |
0x000 |
Address offset |
0x0 4C0C |
||
Physical address |
0x2008 4C0C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:12 |
reserved |
|
RO |
0x0 0000 |
11:0 |
cfg_starve_timeout_p3 |
|
RW |
0x000 |
Address offset |
0x0 4C10 |
||
Physical address |
0x2008 4C10 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:12 |
reserved |
|
RO |
0x0 0000 |
11:0 |
cfg_starve_timeout_p4 |
|
RW |
0x000 |
Address offset |
0x0 4C14 |
||
Physical address |
0x2008 4C14 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:12 |
reserved |
|
RO |
0x0 0000 |
11:0 |
cfg_starve_timeout_p5 |
|
RW |
0x000 |
Address offset |
0x0 4C18 |
||
Physical address |
0x2008 4C18 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:12 |
reserved |
|
RO |
0x0 0000 |
11:0 |
cfg_starve_timeout_p6 |
|
RW |
0x000 |
Address offset |
0x0 4C1C |
||
Physical address |
0x2008 4C1C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:12 |
reserved |
|
RO |
0x0 0000 |
11:0 |
cfg_starve_timeout_p7 |
|
RW |
0x000 |
Address offset |
0x0 5000 |
||
Physical address |
0x2008 5000 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_reorder_en |
|
RW |
1 |
Address offset |
0x0 5004 |
||
Physical address |
0x2008 5004 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_reorder_queue_en |
|
RW |
1 |
Address offset |
0x0 5008 |
||
Physical address |
0x2008 5008 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_intraport_reorder_en |
|
RW |
1 |
Address offset |
0x0 500C |
||
Physical address |
0x2008 500C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_maintain_coherency |
|
RW |
1 |
Address offset |
0x0 5010 |
||
Physical address |
0x2008 5010 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
cfg_q_age_limit |
|
RW |
0xFF |
Address offset |
0x0 5018 |
||
Physical address |
0x2008 5018 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_ro_closed_page_policy |
|
RW |
0 |
Address offset |
0x0 501C |
||
Physical address |
0x2008 501C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_reorder_rw_only |
|
RW |
0 |
Address offset |
0x0 5020 |
||
Physical address |
0x2008 5020 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_ro_priority_en |
|
RW |
0 |
Address offset |
0x0 5400 |
||
Physical address |
0x2008 5400 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_dm_en |
|
RW |
1 |
Address offset |
0x0 5404 |
||
Physical address |
0x2008 5404 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_rmw_en |
|
RW |
1 |
Address offset |
0x0 5800 |
||
Physical address |
0x2008 5800 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_ecc_correction_en |
|
RW |
1 |
Address offset |
0x0 5840 |
||
Physical address |
0x2008 5840 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_ecc_bypass |
|
RW |
0 |
Address offset |
0x0 5844 |
||
Physical address |
0x2008 5844 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:2 |
reserved |
|
RO |
0x0000 0000 |
1:0 |
init_write_data_1b_ecc_error_gen |
|
RW |
0x0 |
Address offset |
0x0 5848 |
||
Physical address |
0x2008 5848 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:2 |
reserved |
|
RO |
0x0000 0000 |
1:0 |
init_write_data_2b_ecc_error_gen |
|
RW |
0x0 |
Address offset |
0x0 585C |
||
Physical address |
0x2008 585C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
cfg_ecc_1bit_int_thresh |
|
RW |
0x00 |
Address offset |
0x0 5860 |
||
Physical address |
0x2008 5860 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
stat_int_ecc_1bit_thresh |
|
RO |
0 |
Address offset |
0x0 5C00 |
||
Physical address |
0x2008 5C00 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
init_read_capture_addr |
|
RW |
0x0 |
Address offset |
0x0 5C04 |
||
Physical address |
0x2008 5C04 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
init_read_capture_data_0 |
|
RO |
0x0000 0000 |
Address offset |
0x0 5C08 |
||
Physical address |
0x2008 5C08 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
init_read_capture_data_1 |
|
RO |
0x0000 0000 |
Address offset |
0x0 5C0C |
||
Physical address |
0x2008 5C0C |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
init_read_capture_data_2 |
|
RO |
0x0000 0000 |
Address offset |
0x0 5C10 |
||
Physical address |
0x2008 5C10 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
init_read_capture_data_3 |
|
RO |
0x0000 0000 |
Address offset |
0x0 5C14 |
||
Physical address |
0x2008 5C14 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
reserved |
|
RO |
0x0000 |
15:0 |
init_read_capture_data_4 |
|
RO |
0x0000 |
Address offset |
0x0 6400 |
||
Physical address |
0x2008 6400 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_error_group_sel |
|
RW |
0 |
Address offset |
0x0 6404 |
||
Physical address |
0x2008 6404 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:7 |
reserved |
|
RO |
0x000 0000 |
6:0 |
cfg_data_sel |
|
RW |
0x00 |
Address offset |
0x0 6408 |
||
Physical address |
0x2008 6408 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_trig_mode |
|
RW |
0 |
Address offset |
0x0 640C |
||
Physical address |
0x2008 640C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:7 |
reserved |
|
RO |
0x000 0000 |
6:0 |
cfg_post_trig_cycs |
|
RW |
0x00 |
Address offset |
0x0 6410 |
||
Physical address |
0x2008 6410 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:3 |
reserved |
|
RO |
0x0000 0000 |
2:0 |
cfg_trig_mask |
|
RW |
0x0 |
Address offset |
0x0 6414 |
||
Physical address |
0x2008 6414 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:2 |
reserved |
|
RO |
0x0000 0000 |
1:0 |
cfg_en_mask |
|
RW |
0x0 |
Address offset |
0x0 6418 |
||
Physical address |
0x2008 6418 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
reserved |
|
RO |
0x000 0000 |
5:0 |
mtc_acq_addr |
|
RW |
0x00 |
Address offset |
0x0 641C |
||
Physical address |
0x2008 641C |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:7 |
reserved |
|
RO |
0x000 0000 |
6:0 |
mtc_acq_cycs_stored |
|
RO |
0x00 |
Address offset |
0x0 6420 |
||
Physical address |
0x2008 6420 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
mtc_acq_trig_detect |
|
RO |
0 |
Address offset |
0x0 6424 |
||
Physical address |
0x2008 6424 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
reserved |
|
RO |
0x000 0000 |
5:0 |
mtc_acq_mem_trig_addr |
|
RO |
0x00 |
Address offset |
0x0 6428 |
||
Physical address |
0x2008 6428 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
reserved |
|
RO |
0x000 0000 |
5:0 |
mtc_acq_mem_last_addr |
|
RO |
0x00 |
Address offset |
0x0 642C |
||
Physical address |
0x2008 642C |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
mtc_ack |
|
RO |
0 |
Address offset |
0x0 6430 |
||
Physical address |
0x2008 6430 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_trig_mt_addr_0 |
|
RW |
0x0000 0000 |
Address offset |
0x0 6434 |
||
Physical address |
0x2008 6434 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:7 |
reserved |
|
RO |
0x000 0000 |
6:0 |
cfg_trig_mt_addr_1 |
|
RW |
0x00 |
Address offset |
0x0 6438 |
||
Physical address |
0x2008 6438 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_trig_err_mask_0 |
|
RW |
0x0000 0000 |
Address offset |
0x0 643C |
||
Physical address |
0x2008 643C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_trig_err_mask_1 |
|
RW |
0x0000 0000 |
Address offset |
0x0 6440 |
||
Physical address |
0x2008 6440 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_trig_err_mask_2 |
|
RW |
0x0000 0000 |
Address offset |
0x0 6444 |
||
Physical address |
0x2008 6444 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_trig_err_mask_3 |
|
RW |
0x0000 0000 |
Address offset |
0x0 6448 |
||
Physical address |
0x2008 6448 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
reserved |
|
RO |
0x0000 |
15:0 |
cfg_trig_err_mask_4 |
|
RW |
0x0000 |
Address offset |
0x0 644C |
||
Physical address |
0x2008 644C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
mtc_acq_wr_data_0 |
|
RW |
0x0000 0000 |
Address offset |
0x0 6450 |
||
Physical address |
0x2008 6450 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
mtc_acq_wr_data_1 |
|
RW |
0x0000 0000 |
Address offset |
0x0 6454 |
||
Physical address |
0x2008 6454 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
mtc_acq_wr_data_2 |
|
RW |
0x00 |
Address offset |
0x0 6458 |
||
Physical address |
0x2008 6458 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
mtc_acq_rd_data_0 |
|
RO |
0x0000 0000 |
Address offset |
0x0 645C |
||
Physical address |
0x2008 645C |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
mtc_acq_rd_data_1 |
|
RO |
0x0000 0000 |
Address offset |
0x0 6460 |
||
Physical address |
0x2008 6460 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
mtc_acq_rd_data_2 |
|
RO |
0x00 |
Address offset |
0x0 652C |
||
Physical address |
0x2008 652C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
reserved |
|
RO |
0x0000 |
15:0 |
cfg_pre_trig_cycs |
|
RW |
0x0000 |
Address offset |
0x0 6538 |
||
Physical address |
0x2008 6538 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:10 |
reserved |
|
RO |
0x00 0000 |
9:0 |
mtc_acq_error_cnt |
|
RO |
0x000 |
Address offset |
0x0 6544 |
||
Physical address |
0x2008 6544 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
mtc_acq_error_cnt_ovfl |
|
RO |
0 |
Address offset |
0x0 6550 |
||
Physical address |
0x2008 6550 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_data_sel_first_error |
|
RW |
0 |
Address offset |
0x0 7C00 |
||
Physical address |
0x2008 7C00 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:2 |
reserved |
|
RO |
0x0000 0000 |
1:0 |
cfg_dq_width |
|
RW |
0x0 |
Address offset |
0x0 7C04 |
||
Physical address |
0x2008 7C04 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:2 |
reserved |
|
RO |
0x0000 0000 |
1:0 |
cfg_active_dq_sel |
|
RW |
0x0 |
Address offset |
0x0 8000 |
||
Physical address |
0x2008 8000 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
stat_ca_parity_error |
|
RO |
0 |
Address offset |
0x0 800C |
||
Physical address |
0x2008 800C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_ca_parity_error_gen_req |
|
RW |
0 |
Address offset |
0x0 8010 |
||
Physical address |
0x2008 8010 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
init_ca_parity_error_gen_cmd |
|
RW |
0x0 |
Address offset |
0x0 8014 |
||
Physical address |
0x2008 8014 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_ca_parity_error_gen_ack |
|
RO |
0 |
Address offset |
0x1 0000 |
||
Physical address |
0x2009 0000 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
reserved |
|
RO |
0x000 0000 |
5:0 |
cfg_dfi_t_rddata_en |
|
RW |
0x14 |
Address offset |
0x1 0004 |
||
Physical address |
0x2009 0004 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:5 |
reserved |
|
RO |
0x000 0000 |
4:0 |
cfg_dfi_t_phy_rdlat |
|
RW |
0x05 |
Address offset |
0x1 0008 |
||
Physical address |
0x2009 0008 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
reserved |
|
RO |
0x000 0000 |
5:0 |
cfg_dfi_t_phy_wrlat |
|
RW |
0x05 |
Address offset |
0x1 000C |
||
Physical address |
0x2009 000C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_dfi_phyupd_en |
|
RW |
1 |
Address offset |
0x1 0010 |
||
Physical address |
0x2009 0010 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_dfi_lp_data_req |
|
RW |
0 |
Address offset |
0x1 0014 |
||
Physical address |
0x2009 0014 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
init_dfi_lp_ctrl_req |
|
RW |
0 |
Address offset |
0x1 0018 |
||
Physical address |
0x2009 0018 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
stat_dfi_lp_ack |
|
RO |
0 |
Address offset |
0x1 001C |
||
Physical address |
0x2009 001C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
init_dfi_lp_wakeup |
|
RW |
0x0 |
Address offset |
0x1 0020 |
||
Physical address |
0x2009 0020 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:2 |
reserved |
|
RO |
0x0000 0000 |
1:0 |
init_dfi_dram_clk_disable |
|
RW |
0x0 |
Address offset |
0x1 0024 |
||
Physical address |
0x2009 0024 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
stat_dfi_training_error |
|
RO |
0 |
Address offset |
0x1 0028 |
||
Physical address |
0x2009 0028 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
stat_dfi_error |
|
RO |
0 |
Address offset |
0x1 002C |
||
Physical address |
0x2009 002C |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
stat_dfi_error_info |
|
RO |
0x0 |
Address offset |
0x1 0030 |
||
Physical address |
0x2009 0030 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:5 |
reserved |
|
RO |
0x000 0000 |
4:0 |
cfg_dfi_data_byte_disable |
|
RW |
0x00 |
Address offset |
0x1 0034 |
||
Physical address |
0x2009 0034 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
stat_dfi_init_complete |
|
RO |
0 |
Address offset |
0x1 0038 |
||
Physical address |
0x2009 0038 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
stat_dfi_training_complete |
|
RO |
0 |
Address offset |
0x1 003C |
||
Physical address |
0x2009 003C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_dfi_lvl_sel |
|
RW |
0 |
Address offset |
0x1 0040 |
||
Physical address |
0x2009 0040 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_dfi_lvl_periodic |
|
RW |
0 |
Address offset |
0x1 0044 |
||
Physical address |
0x2009 0044 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
cfg_dfi_lvl_pattern |
|
RW |
0x0 |
Address offset |
0x1 0050 |
||
Physical address |
0x2009 0050 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
phy_dfi_init_start |
|
RW |
0 |
Address offset |
0x1 2C18 |
||
Physical address |
0x2009 2C18 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_axi_start_address_axi1_0 |
|
RW |
0x0000 0000 |
Address offset |
0x1 2C1C |
||
Physical address |
0x2009 2C1C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:2 |
reserved |
|
RO |
0x0000 0000 |
1:0 |
cfg_axi_start_address_axi1_1 |
|
RW |
0x0 |
Address offset |
0x1 2C20 |
||
Physical address |
0x2009 2C20 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_axi_start_address_axi2_0 |
|
RW |
0x0000 0000 |
Address offset |
0x1 2C24 |
||
Physical address |
0x2009 2C24 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:2 |
reserved |
|
RO |
0x0000 0000 |
1:0 |
cfg_axi_start_address_axi2_1 |
|
RW |
0x0 |
Address offset |
0x1 2F18 |
||
Physical address |
0x2009 2F18 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_axi_end_address_axi1_0 |
|
RW |
0xFFFF FFFF |
Address offset |
0x1 2F1C |
||
Physical address |
0x2009 2F1C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:2 |
reserved |
|
RO |
0x0000 0000 |
1:0 |
cfg_axi_end_address_axi1_1 |
|
RW |
0x3 |
Address offset |
0x1 2F20 |
||
Physical address |
0x2009 2F20 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_axi_end_address_axi2_0 |
|
RW |
0xFFFF FFFF |
Address offset |
0x1 2F24 |
||
Physical address |
0x2009 2F24 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:2 |
reserved |
|
RO |
0x0000 0000 |
1:0 |
cfg_axi_end_address_axi2_1 |
|
RW |
0x3 |
Address offset |
0x1 3218 |
||
Physical address |
0x2009 3218 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_mem_start_address_axi1_0 |
|
RW |
0x0000 0000 |
Address offset |
0x1 321C |
||
Physical address |
0x2009 321C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:2 |
reserved |
|
RO |
0x0000 0000 |
1:0 |
cfg_mem_start_address_axi1_1 |
|
RW |
0x0 |
Address offset |
0x1 3220 |
||
Physical address |
0x2009 3220 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_mem_start_address_axi2_0 |
|
RW |
0x0000 0000 |
Address offset |
0x1 3224 |
||
Physical address |
0x2009 3224 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:2 |
reserved |
|
RO |
0x0000 0000 |
1:0 |
cfg_mem_start_address_axi2_1 |
|
RW |
0x0 |
Address offset |
0x1 3514 |
||
Physical address |
0x2009 3514 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_enable_bus_hold_axi1 |
|
RW |
0 |
Address offset |
0x1 3518 |
||
Physical address |
0x2009 3518 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
cfg_enable_bus_hold_axi2 |
|
RW |
0 |
Address offset |
0x1 3690 |
||
Physical address |
0x2009 3690 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:0 |
cfg_axi_auto_pch |
|
RW |
0x0000 0000 |
Address offset |
0x3 C000 |
||
Physical address |
0x200B C000 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
reserved |
|
RO |
0x0000 |
15:0 |
phy_reset_control |
Reset control register |
RW |
0x000D |
Address offset |
0x3 C004 |
||
Physical address |
0x200B C004 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:4 |
reserved |
|
RO |
0x000 0000 |
3:0 |
phy_pc_rank |
Select which rank to be trained. |
RW |
0x0 |
Address offset |
0x3 C008 |
||
Physical address |
0x200B C008 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:16 |
reserved |
|
RO |
0x0000 |
15:0 |
phy_ranks_to_train |
One hot encoding of which ranks to train during automatic
initialization. |
RW |
0x0000 |
Address offset |
0x3 C00C |
||
Physical address |
0x200B C00C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
phy_write_request |
Request the memory controller to write to the SDRAM.
Writes the eye training pattern into location 0 in the SDRAM |
RW |
0 |
Address offset |
0x3 C010 |
||
Physical address |
0x200B C010 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
phy_write_request_done |
Indicate write request is completed |
RO |
0 |
Address offset |
0x3 C014 |
||
Physical address |
0x200B C014 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
phy_read_request |
Request the memory controller to read from the SDRAM.
Intended for gate training and eye training |
RW |
0 |
Address offset |
0x3 C018 |
||
Physical address |
0x200B C018 |
Instance |
DDRCFG |
Description |
|||
Type |
RO |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
phy_read_request_done |
Indicate read request is completed |
RO |
0 |
Address offset |
0x3 C01C |
||
Physical address |
0x200B C01C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
reserved |
|
RO |
0x000 0000 |
5:0 |
phy_write_level_delay |
Number of cycles to allow PHY response before sending
another strobe. |
RW |
0x00 |
Address offset |
0x3 C020 |
||
Physical address |
0x200B C020 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
reserved |
|
RO |
0x000 0000 |
5:0 |
phy_gate_train_delay |
Number of cycles to allow PHY response before sending the
next read command. |
RW |
0x00 |
Address offset |
0x3 C024 |
||
Physical address |
0x200B C024 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
reserved |
|
RO |
0x000 0000 |
5:0 |
phy_eye_train_delay |
Number of cycles to allow PHY response before sending the
next read command. |
RW |
0x00 |
Address offset |
0x3 C028 |
||
Physical address |
0x200B C028 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:8 |
reserved |
|
RO |
0x00 0000 |
7:0 |
phy_eye_pat |
Eye training pattern to be loaded into the phy and the
SDRAM |
RW |
0x00 |
Address offset |
0x3 C02C |
||
Physical address |
0x200B C02C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
phy_start_recal |
Rerun write leveling, gate training, and eye training. |
RW |
0 |
Address offset |
0x3 C030 |
||
Physical address |
0x200B C030 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
phy_clr_dfi_lvl_periodic |
Clear PHY init SM Periodic Training incremental enable |
RW |
0 |
Address offset |
0x3 C034 |
||
Physical address |
0x200B C034 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:6 |
reserved |
|
RO |
0x000 0000 |
5:0 |
phy_train_step_enable |
PHY init state machine training step/stage enables, [5]:
CA training, [4]: write leveling, [3]: read leveling, [2:0]: reserved |
RW |
0x00 |
Address offset |
0x3 C038 |
||
Physical address |
0x200B C038 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
phy_lpddr_dq_cal_pat |
LPDDR2/3 DQ training pattern, 0:A,1010_1010,MR32
1:B,0011_0011,MR40 |
RW |
0 |
Address offset |
0x3 C03C |
||
Physical address |
0x200B C03C |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
phy_indpndt_training |
Set to 1'b1 to indicate that the PHY will perform training
without requiring interaction from the MC. The PHY will start training at the
assertion of ctrlr_init_done and will signal completion with
dfi_training_complete. |
RW |
0 |
Address offset |
0x3 C040 |
||
Physical address |
0x200B C040 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
phy_encoded_quad_cs |
Set to indicate configuration with DDR4 RDIMMs that have
four ranks that encode chip-select down to 3 bits. When this port is set to
'1', sd_cs_n[2:0] will only be used to designate rank selection to the RCD
device. Refer to the JEDEC DDR4RCD01 DDR4 Registering Clock Driver (RCD)
specification for details on how the Encoded Quad CS is used in an RDIMM
application. |
RW |
0 |
Address offset |
0x3 C044 |
||
Physical address |
0x200B C044 |
Instance |
DDRCFG |
Description |
|||
Type |
RW |
Bits |
Field Name |
Description |
Type |
Reset |
31:1 |
reserved |
|
RO |
0x0000 0000 |
0 |
phy_half_clk_dly_enable |
Set to enable 1/2 clock output delay of DQ/DQS datapath.
Used to Align with RCD 1/2 clock delay. |
RW |
0 |
DDR_CSR_APB has no common memories.